EP0063638B1 - Digital telecommunication system - Google Patents

Digital telecommunication system Download PDF

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Publication number
EP0063638B1
EP0063638B1 EP81109138A EP81109138A EP0063638B1 EP 0063638 B1 EP0063638 B1 EP 0063638B1 EP 81109138 A EP81109138 A EP 81109138A EP 81109138 A EP81109138 A EP 81109138A EP 0063638 B1 EP0063638 B1 EP 0063638B1
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EP
European Patent Office
Prior art keywords
signal
wire line
store
wire
compensation
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EP81109138A
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German (de)
French (fr)
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EP0063638A3 (en
EP0063638A2 (en
Inventor
Herbert Dipl.-Ing. Strehl
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Siemens AG
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Siemens AG
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Priority to AT81109138T priority Critical patent/ATE18482T1/en
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Publication of EP0063638A3 publication Critical patent/EP0063638A3/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
    • H04B3/23—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
    • H04B3/231—Echo cancellers using readout of a memory to provide the echo replica

Definitions

  • Such an echo canceller requires a relatively high level of circuit complexity, in particular for a second memory, a multiplication circuit and an integration circuit. Instead, it is also possible, as is also already known (from AGARD Conference Proceedings No. 103 (1972), 12-1 ... 12-16), to generate the compensation signal with the aid of a variable filter, which is used when establishing each connection is set to provide the same impulse response as the echo path upon a test signal; however, the correlation between the transmit and receive signals can play a disruptive role.
  • the control circuit is formed by a decoder for sampling the transmission signal element sequences that occur in each case, which selects a compensation signal corresponding to this transmission signal element sequence from the compensation signal memory as a function of the respective transmission signal element sequence.
  • the required compensation signal elements can be calculated in an externally connected computer when the relevant remote control system is put into operation and written into the compensation signal memory.
  • the invention is based on the object of specifying a digital telecommunication system with a hybrid circuit and a compensation circuit provided in parallel, in which the desired interference signal compensation is advantageously made possible without great additional circuitry outlay, while avoiding disadvantages as mentioned above .
  • the invention relates to a digital telecommunication system with at least one hybrid circuit between a four-wire line section and a two-wire line section, in particular for subscriber-side or exchange-side termination of a two-wire subscriber line, and with a cross-talk provided between the four-wire line branch arriving at the multi-line circuit and the four-wire line branch coming from the hybrid circuit. u./o.
  • Echo compensation circuit with a compensation signal memory which can be controlled in accordance with the transmission signal pulses which occur in the four-wire line branch arriving at the hybrid circuit and which leads on the output side to the four-wire line branch leaving the hybrid circuit, an interference signal which is free on a signal pulse to be transmitted in the opposite direction
  • Two-wire line occurs in the incoming four-wire line branch, the first transmission signal pulse occurring in the outgoing four-wire line branch, is written serially into the compensation signal memory and is read out therefrom as a compensation signal at least during the subsequent connection on each further transmission signal pulse;
  • the compensation signal memory is formed by a circulation memory with a circulation time equal to a multiple of a bit time period and has a corresponding plurality of successive outputs, each corresponding to a bit time period, which are summarized by a subsequent adding circuit the individual outputs can be connected to the outgoing four-wire line branch in a sequence corresponding to a series of transmission signal pulses, each for the duration of a multiple of
  • the invention in which the time available for storing the interference signal when the two-wire line is free from signal pulses transmitted in the opposite direction can be caused by the double signal propagation time on the line or also by a delay procedure in the generation of a response signal and with which more or less quickly successive transmission signal pulses and - due to long echo propagation times - a longer than one bit period of the compensation signal, a superimposition of compensation signals obtained by multiple readings of the same compensation signal memory, connected among themselves, allows a very simple and at the same time unaffected by a correlation between transmit and receive signals a compensation signal , which advantageously does not have to be calculated separately, so that time difficulties associated with a compensation signal calculation are avoided.
  • the specified compensation principle can also be used with higher transmission bit rates of e.g. B. 128 kbit / s application.
  • the invention also opens up the possibility of the compensation circuit being able to be remotely fed, as is particularly desirable in the case of a compensation circuit to be provided on the subscriber side.
  • Another advantage is the suitability of the invention for subscriber-side compensation signal generation also in the context of remote switching connections running over two-wire exchanges with consequent line conditions changing from connection to connection, in that at the beginning of the transmission both telecommunication subscriber stations involved in a connection are in succession each can generate the compensation signal in a procedure, the duration of which corresponds to twice the signal propagation time is negligibly small in comparison with adaptation procedures that would otherwise be required.
  • such a first transmission signal pulse is generated each time the remote supply voltage is switched on, and the resulting interference signal is written into the associated compensation signal memory, from which it is then repeated each time a transmission signal pulse is read out as a compensation signal; this can suitably take into account the possibility of an interruption in the supply circuit and a resultant loss of the interference signal stored up to that point, for example due to a line rearrangement in the switching center or a transfer of a subscriber set from one connection socket to another.
  • the invention can take into account the fact that the Change echoes and mismatch-related interference signals at most when the subscriber line is rearranged, in such a way that the compensation signal is written into the associated compensation signal memory during the first connection establishment initiated by the subscriber, in particular, for example, during the first test call originating from the subscriber station, and from there during later connections running over the two-wire subscriber line are read out again as a compensation signal.
  • the compensation signal can be written into the associated compensation signal memory when the first connection is made to the subscriber concerned, in particular, for example, when the test call is first called back to the subscriber station concerned therefrom can be read out again as compensation signal during later connections veverender on the two-wire subscriber line.
  • the interference signal is expediently first quantized and encoded and then written into the compensation signal memory in the form of the binary signal thus obtained, which then leads via a subsequent digital / analog converter circuit to the outgoing four-wire line branch; the interference signal is preferably written via a delta modulator in the form of the AM signal thus obtained into the compensation signal memory which then leads via a delta modulator circuit to the outgoing four-wire line branch.
  • the compensation signal memory can be formed in a further embodiment of the invention by a circulation shift register.
  • a static memory in addition to the circulation memory, a static memory can be provided, into which the compensation signal is also written, so that it can be read into the circulation memory again at the beginning of a new transmission process.
  • a telecommunications system is shown schematically with a two-wire line ZL lying between two four-wire line sections VL T , VL v , closed on both sides with a hook-up circuit G T or G v , whereby it is indicated that this two-wire line ZL, for example, by changes in diameter of the Has conduction joints R conditional.
  • an interference signal occurs, as is shown, for example, in FIG. 1 below;
  • the front part of such an interference signal can also contain a signal component which is directly attributable to crosstalk from the four-wire line branch VS to the four-wire line branch VE, which is caused by insufficient fork blocking.
  • Such an interference signal occurring in response to a first transmission signal pulse in a time period that is not available for signal transmission in the opposite direction is now serially written into a compensation signal memory and is read out therefrom as a compensation signal at least during the subsequent signal transmission upon each further transmission signal pulse, which is then read out with a Phase rotation of 180 ° in the four-wire branch coming from the hybrid circuit has an interference signal compensation effect.
  • a digital telecommunications system with a hybrid circuit G between a four-wire line section VL and a two-wire line section ZL, the two-wire line ZL and the multi-circuit circuit G being a two-wire Subscriber line and their subscriber-side or exchange-side termination can act.
  • the four-wire line section VL has, in its transmission branch VS arriving at the hybrid circuit G, a digital signal transmission circuit DS for transmitting transmission signal pulses s of a predetermined form or with a predetermined center of gravity of its frequency spectrum; In Fig. 2 it is indicated that the transmission circuit DS may convert its supplied binary signal pulses d into AMI signal pulses s.
  • the four-wire line section VL has a digital signal receiving circuit with a filter and, if necessary, an equalizer in its receiving branch VE which branches off the hybrid circuit G.
  • --Circuit F and a digital signal receiver E which may convert the signals emitted by the filter circuit F into corresponding binary signals, with the reception of the signal shapes indicated in FIG. 1, such a received signal converter can in principle be implemented with a rectifier circuit.
  • the transmission signal pulses s pass from the transmission branch VS of the four-wire line section VL via the hybrid circuit G to the two-wire line ZL, via which they are transmitted to the remote station of the digital telecommunications system, which is not shown in FIG. 2; in the reverse direction of transmission, signal pulses originating from the remote station and transmitted via the two-wire line ZL pass through the hybrid circuit G as received signal pulses to the receiving branch VE of the four-wire line section VL.
  • the two-wire line ZL has reflection points, as can be caused by sudden changes in line parameters, then in addition to the actual received signal pulses, echoes of the transmitted signal pulses s also reach the receiving branch VE of the four-wire line section VL, and, in addition, with limited fork blocking, portions of the transmitted signal pulses s can also be obtained directly get into the reception branch VE.
  • the reception branch VE there then occurs a received signal mixture of the actual received signal pulses and an interference signal composed of echo signals and crosstalk signals; this interference signal must be compensated.
  • Echo compensation circuit with a compensation signal memory UR which can be controlled in accordance with transmission signal pulses which occur in the incoming four-wire line branch VS is provided.
  • the compensation signal memory UR is formed by a circulation memory, preferably in the form of a so-called circulation shift register closed to a ring, the circulation time of which is equal to a multiple of a transmission signal bit period ( TB; t in FIG.
  • Each circulating memory output a can be connected via a logic circuit SI to a subsequent digital / analog converter D / A, which only has to consist of one RC element in the case of a compensation signal stored in the circulating shift register UR in ⁇ M representation.
  • the outputs of the digital / analog converter D / A lead, combined via a passive adder circuit ADD. to the compensation signal input k of the compensation element K to be implemented, for example, with a differential amplifier, which is inserted into the four-wire line branch VE going out from the hybrid circuit G.
  • Behind this compensation element K is connected to the outgoing four-wire line branch VE the input of an analog / digital converter A / D, with ⁇ M representation of the compensation signal to be stored in the circulation shift register UR, a delta modulator, which leads on the output side to the write-in input of the circulation shift register UR.
  • the compensation element K can first be followed by a permanently set amplifier which brings the signals to a level suitable for the A / D conversion and compensates for the attenuation of the passive addition network ADD.
  • the interference signal indicated in FIG. 2 is obtained via the analog / digital converter A / D (see also FIG.
  • a static memory SS is provided in parallel with the circulation shift register UR and also stores the interference signal written into the circulation memory UR; while the digitized interference signal rotates in the circulation memory UR, so that it can be read out at each of the transmit signal bit periods at one of the memory outputs a1 ... a4, it remains permanently stored in the static memory SS for later transmission processes and possibly also for control purposes.
  • the interference signal can remain stored in particular if it could be lost in the circulation shift register UR when the clock is switched off in the pauses between two connections, for example because of the power requirement of the circulation memory UR when the clock is switched off also no noteworthy Should consume feed current.
  • the parallel-connected static memory SS can possibly be omitted if the circulation shift register (circulation memory) UR used keeps the information as long as the (remote) supply voltage is present after the clock has been switched off.
  • the analog / digital converter A / D which in the example only inputs the digitized interference signal (it in FIG. 1 below and FIG. 2) into the compensation signal memory UR during the first four transmission signal bit periods, can also be used for control purposes in the following time can be used: Whenever no signal impulses arrive from the opposite side, either randomly (series of "0" bits) or controlled by a procedure, the analog / digital converter can be used as a level detector and the accuracy of the stored Check compensation signal.
  • a corresponding control device Ste can provide the circulation memory UR and the static memory SS and the transfer of the digitized interference signal contained in the static memory SS into the circulation memory UR during later transmission processes and for controlling procedures for checking and, if necessary, correcting the stored signal is indicated in Fig. 2.
  • the storage capacity required for the circulating memory UR or for the static memory SS is relatively small, since the amplitude of an echo to be compensated rapidly decreases with increasing transit time because of the double line attenuation, as can also be seen from FIG. 1 below.
  • the storage capacity is dependent on the sampling frequency of the analog / digital converter A / D; the higher the sampling frequency, the smaller the quantization distortions of the interference signal and the smaller the residual error remaining after the compensation.
  • the four memory outputs a1 ... a4 then provided in the example, each at a distance of 20 bits of the digitized interference signal, are, as already mentioned, each via a logic circuit SI with the respective subsequent digital / analog converter, in the example delta modulator, D / A connectable.
  • These logic circuits SI can with a binary line code, i. H. in the case of transmission signal pulses of one polarity, in each case be formed by a simple switching element; with a ternary line code, d. H.
  • the logic circuits SI can each be formed by a parallel connection of a simple switching element and a controlled NOT element, so that, depending on the sign of the interference signal to be compensated, the compensation signal is inverted or not is inverted. It should be noted here that, in deviation from the illustration given in FIG. 2, instead of an inversion of the compensation signal still present in the digital representation before the digital / analog conversion, a phase reversal of the compensation signal then present in the analog representation is also carried out after the digital / analog conversion can, but this is not shown in the drawing.
  • the individual outputs a1, a2, a3, a4 of the circulation register UR are unlocked in a sequence corresponding to the pattern of the transmission signal pulses (“1” bits) contained in a sequence of transmission signal bits, each for the duration of four times a transmission signal bit period in the example, so that the interference signal stored in the revolving shift register UR may be read out simultaneously at several memory outputs a1 ... a4, each with a different phase position; the adder circuit ADD then combines the individual signals by superimposition to form a combined compensation signal, as is then also required in order to compensate for the interference signal which is present in the outgoing four-wire line branch VE and has corresponding superimpositions.
  • FIGS. 3 and 4 show circuit details of the control devices Sta and Ste mentioned above.
  • the control device Sta can, as indicated in FIG. 3, have a circulation shift register in the same way as the circulation shift register UR (in FIG. 2) with four outputs in the example, in which phase with the beginning of the Circulation shift register UR (in Fig. 2) stored interference signal rotates a control bit and at the outputs of each of them via an AND gate unlocked by a (positive or negative) transmission signal pulse (s in Fig. 2) for a duration of four in the example Line signal bit time periods activatable bistable flip-flop is connected, which controls the logic element (switching element or NOT element) SI to be unlocked in each case (in FIG. 2).
  • the control device Ste can, as indicated in FIG. 4, have a bistable flip-flop that can be activated by a transmission signal pulse (d in FIG. 2) for the duration of four line signal bit periods in the example, which is connected via a subsequent flip-flop by another bistable flip-flop after a first activation of the first flip-flop locked blocking element unlocks the write input of the circulation shift register UR;
  • a control signal for parallel transfer of the interference signal written into the circulation shift register UR into the static memory SS (in FIG. 2) and from the output of the first-mentioned bistable trigger element can be input from the output of the blocking element via a series connection of a NOT element and a differentiating element Starting signal for a sample and shift clock generator (clock in Fig. 2) are taken.
  • control device Ste can send a control signal to a connection start signal v supplied to it via an AND gate that can be unlocked by a transmission signal pulse, for parallel transfer of the interference signal stored in the static memory SS into the circulation memory UR and for restarting the shift clock generator clock ( in Fig. 2).

Abstract

1. A digital telecommunications system with at least one hybrid circuit (G) which is located between a four-wire line section (VL) and a two-wire line section (ZL), in particular for terminating a two-wire subscriber connection line (ZL) at the subscriber end or at the exchange end, and with a cross-talk and/or echo compensation circuit which is arranged between the four-wire line arm (VS) incoming to the hybrid circuit (G) and the four-wire line arm (VE) outgoing from the hybrid circuit (G), having a compensation signal store (UR) which can be operated in accordance with transmitted signal pulses which occur in the four-wire line arm (VS) incoming to the hybrid circuit (G) and which feeds at its output end to the four-wire line arm (VE) outgoing from the hybrid circuit (G), where an interference signal (es ), which occurs in the outgoing four-wire line arm (VE) in response to a first transmitted signal pulse (s), which itself occurs in the incoming four-wire line arm (VS) when the two-wire line (ZL) is free of signal pulses to be transmitted in the opposite direction, is input in serial fashion into the compensation signal store (UR) and is read out therefrom compensation signal (k), at least during the following connection, in response to each further transmitted signal pulse (s), characterised in that the compensation signal store (UR) is formed by a cyclic store having a cycle time which is equal to a multiple of a bit interval and has a corresponding number of outputs (a1, a2, a3, a4) which follow one another at intervals in each case corresponding to one bit intervals and which are assembled by a following adder circuit (ADD) via which the individual outputs can be connected to the outgoing four-wire line arm (VE) for the duration of the multiple of one bit interval, in a sequence corresponding to a sequence of transmitted signal pulses (s).

Description

In Fernmeldesystemen können bei der Übertragung von Signalen auf dem Übertragungsweg lineare Signalstörungen entstehen, zu deren Beseitigung sogenannte Kompensatoren eingesetzt werden können. Solche Störungen können z. B. in Femmeldesystemen, in denen zur Überführung von Zweidrahtleitungen in vierdrähtige Abschnitte und umgekehrt Gabelschaltungen (Brückenschaltungen) vorgesehen sind, dadurch hervorgerufen werden, daß eine solche Gabelschaltung eine exakte Nachbildung der Eingangsimpedanz der Zweidrahtleitung enthalten müßte, um eine vollständige Entkopplung des von der Gabelschaltung wegführenden Empfangszweigs der Vierdrahtleitung von dem zur Gabelschaltung hinführenden Sendezweig der Vierdrahtleitung zu erzielen, wozu die Leitungsnachbildung im Einzelfall durch manuellen Abgleich an die jeweilige Zweidrahtleitung angepaßt werden muß ; mit einer in der Praxis vielfach angewendeten Kompromißnachbildung, mit der man unterschiedlichen Leitungsimpedanzen Rechnung zu tragen sucht, vermag die Gabelschaltung, die dann eine von der jeweiligen Leitungsimpedanz abhängige endliche Sperrdämpfung aufweist, die Sende- und Empfangssignale nur begrenzt voneinander zu entkoppeln. Auf der anderen Seite können auch bei optimalem Abgleich der Gabelschaltung Echos des eigenen Sendesignals, die durch auf der Zweidrahtleitung vorhandene Reflexionsstellen hervorgerufen werden, nicht ohne weiteres unterdrückt werden.In signaling systems, linear signal interference can occur during the transmission of signals, so-called compensators can be used to eliminate them. Such disorders can e.g. B. in Femmeldesysteme in which for the transfer of two-wire lines into four-wire sections and vice versa fork circuits (bridge circuits) are provided, caused by the fact that such a hybrid circuit should contain an exact replica of the input impedance of the two-wire line in order to completely decouple the leading away from the hybrid circuit To achieve the reception branch of the four-wire line from the transmitting branch of the four-wire line leading to the hybrid circuit, for which purpose the line simulation must be adapted to the respective two-wire line in individual cases by manual adjustment; With a compromise simulation that is often used in practice and with which one tries to take into account different line impedances, the hybrid circuit, which then has a finite blocking attenuation dependent on the respective line impedance, can only decouple the transmit and receive signals from one another to a limited extent. On the other hand, even if the hybrid circuit is optimally matched, echoes of the own transmission signal, which are caused by reflection points on the two-wire line, cannot be easily suppressed.

Zur Eliminierung oder zumindest Verringerung solcher Echosignale ist es (aus US-A-40 24 358) bekannt, zur Echokompensation bei einer Gabelschaltung zwischen ankommendem und abgehendem Vierdrahtleitungszweig eine Kompensationsschaltung vorzusehen, die vor Beginn einer Konversation einen Prüfimpuls in den Echopfad aussendet und die daraufhin erhaltene Impulsantwort abtastete und die Abtastwerte in einem ersten Speicher einspeichert; in einer mit Hilfe eines das im ankommenden Vierdrahtleitungszweig auftretende Sendesignal speichernden zweiten Speichers, einer Multiplikationsschaltung und einer Integrationsschaltung realisierten Faltungsoperation wird dann durch Faltung (d. h. Produktbildung und anschließende Integration) zwischen der gespeicherten Impulsantwort und dem Sendesignal ein von dem im abgehenden Vierdrahtleitungszweig auftretenden Empfangssignal zu subtrahierendes Korrektursignal erzeugt. Ein solcher Echokompensator erfordert einen relativ hohen schaltungstechnischen Aufwand, insbesondere für einen zweiten Speicher, eine Multiplikationsschaltung und eine Integrationsschaltung. Stattdessen ist es auch möglich, wie dies ebenfalls bereits (aus AGARD Conference Proceedings No. 103 (1972), 12-1...12-16) bekannt ist, das Kompensationssignal mit Hilfe eines variablen Filters zu erzeugen, das beim Aufbau jeder Verbindung so eingestellt wird, daß es auf ein Testsignal hin dieselbe Impulsantwort wie der Echopfad liefert ; dabei kann allerdings die Korrelation zwischen Sende- und Empfangssignal eine störende Rolle spielen.In order to eliminate or at least reduce such echo signals, it is known (from US Pat. No. 4,024,358) to provide a compensation circuit for echo compensation in the case of a hybrid connection between the incoming and outgoing four-wire line branch, which transmits a test pulse into the echo path before the start of a conversation and then receives it Sampled impulse response and the samples stored in a first memory; In a folding operation implemented with the aid of a second memory storing the transmission signal occurring in the incoming four-wire line branch, a multiplication circuit and an integration circuit, a reception signal occurring in the outgoing four-wire line branch is subtracted by folding (ie product formation and subsequent integration) between the stored impulse response and the transmission signal Correction signal generated. Such an echo canceller requires a relatively high level of circuit complexity, in particular for a second memory, a multiplication circuit and an integration circuit. Instead, it is also possible, as is also already known (from AGARD Conference Proceedings No. 103 (1972), 12-1 ... 12-16), to generate the compensation signal with the aid of a variable filter, which is used when establishing each connection is set to provide the same impulse response as the echo path upon a test signal; however, the correlation between the transmit and receive signals can play a disruptive role.

Ein anderer (aus DE-A-28 46 105 = GB-A-20 07 946) bekannter digitaler Übersprech- und Echokompensator weist einen Kompensationssignal-Momentanwerte codiert speichernden Kompensationssignalspeicher auf, der bei einer über eine Ansteuerschaltung bewirkten Ansteuerung nach Maßgabe der Sendesignalelemente die entsprechenden Momentanwerte in ihrer codierten Darstellung einem Digital/Analog-Wandler zuführt, welcher daraus das entsprechende, von den gestörten Empfangssignalelementen zu subtrahierende Kompensationssignal bildet. Dabei ist die Ansteuerschaltung durch einen Decodierer zur Abtastung der jeweils auftretenden Sendesignalelementfolgen gebildet, der in Abhängigkeit von der jeweiligen Sendesignalelementfolge ein dieser Sendesignalelementfolge entsprechendes Kompensationssignal aus dem Kompensationssignalspeicher auswählt.Another (from DE-A-28 46 105 = GB-A-20 07 946) known digital crosstalk and echo canceller has a compensation signal memory which stores coded compensation signal instantaneous values and which, when triggered via a control circuit, has the corresponding function in accordance with the transmission signal elements Feeds instantaneous values in their coded representation to a digital / analog converter, which forms the corresponding compensation signal to be subtracted from the disturbed received signal elements. The control circuit is formed by a decoder for sampling the transmission signal element sequences that occur in each case, which selects a compensation signal corresponding to this transmission signal element sequence from the compensation signal memory as a function of the respective transmission signal element sequence.

Bekannt ist es (aus DE-B-29 20 575) auch, einen anderen Weg zu gehen und ein Kompensationssignal zu speichern, das auf jeden Sendesignalimpuls hin aus dem Kompensationssignalspeicher ausgelesen und dem von der Gabelschaltung abgehenden Vierdrahtleitungszweig zugeführt wird.It is also known (from DE-B-29 20 575) to take a different path and to store a compensation signal which is read out of the compensation signal memory in response to each transmission signal pulse and which is fed to the four-wire line branch coming from the hybrid circuit.

In beiden Fällen können die erforderlichen Kompensationssignalelemente bei Inbetriebnahme des betreffenden Fernmeidesystems in einem extern angeschalteten Rechner errechnet und in den Kompensationssignalspeicher eingeschrieben werden. Nachteilig ist dabei das Erfordernis einer Neuberechnung der Speicherinhalte bei Änderungen der Leitungsverhältnisse, beispielsweise bei Umrangierungen im Leitungsnetz. Sieht man, wie dies ebenfalls (aus DE-A-2846105 = GB-A-2007946) bekannt ist, eine adaptive Störsignalimpensation vor, so muß dazu wiederum die Voraussetzung zumindest über einen bestimmten Zeitraum unkorrelierter bzw. statistisch voneinander unabhängiger Sende- und Empfangssignale gegeben sein ; solche Korrelationen können aber, wenn gerade nicht gesprochen wird, bei der üblichen Verwendung ein und desselben Scramblers kaum vermieden werden.In both cases, the required compensation signal elements can be calculated in an externally connected computer when the relevant remote control system is put into operation and written into the compensation signal memory. The disadvantage here is the need to recalculate the memory contents in the event of changes in the line conditions, for example in the case of rearrangements in the line network. If, as is also known (from DE-A-2846105 = GB-A-2007946), provision is made for adaptive interference signal compensation, then in turn the prerequisite must be given at least over a certain period of uncorrelated or statistically independent transmission and reception signals be ; Such correlations, if not spoken, can hardly be avoided with the usual use of the same scrambler.

Aus JP-A-55-10243, die den Oberbegriff von Patentanspruch 1 belegt, ist es auch schon bekannt, das Störsignal, das auf einen bei von in der Gegenrichtung zu übertragenden Signalimpulsen freier Zweidrahtleitung im ankommenden Vierdrahtleitungszweig auftretenden jeweils ersten Sendesignalimpuls hin im abgehenden Vierdrahtleitungszweig auftritt, seriell in den Kompensationssignalspeicher einzuschreiben und daraus auf jeden weiteren Sendesignalimpuls hin als Kompensationssignal wieder auszulesen ; dabei ist jedoch eine der Länge des Störsignals entsprechende Mehrzahl von jeweils das gleiche Störsignal speichernden Kompensationssignalspeichern erforderlich.From JP-A-55-10243, which supports the preamble of claim 1, it is also known that the interfering signal which in response to a first two-wire signal pulse occurring in the incoming four-wire line branch when the two-wire line is free of signal pulses to be transmitted in the opposite direction in the outgoing four-wire line branch occurs, to write serially into the compensation signal memory and from there to every further transmission signal pulse as Read out compensation signal again; however, a plurality of compensation signal memories each storing the same interference signal corresponding to the length of the interference signal is required.

Der Erfindung liegt nun die Aufgabe zugrunde, ein Digital-Fernmeldesystem mit einer Gabelschaltung und einer parallel dazu vorgesehenen Kompensationsschaltung anzugeben, bei dem unter Vermeidung von Nachteilen, wie sie im vorstehenden angeführt sind, die angestrebte Störsignalkompensation in vorteilhafter Weise ohne großen zusätzlichen schaltungstechnischen Aufwand ermöglicht wird.The invention is based on the object of specifying a digital telecommunication system with a hybrid circuit and a compensation circuit provided in parallel, in which the desired interference signal compensation is advantageously made possible without great additional circuitry outlay, while avoiding disadvantages as mentioned above .

Die Erfindung betrifft ein Digital-Fernmeldesystem mit mindestens einer zwischen einem Vierdrahtleitungsabschnitt und einem Zweidrahtleitungsabschnitt liegenden Gabelschaltung, insbesondere zum teilnehmerseitigen oder vermittlungsseitigen Abschluß einer Zweidraht-Teilnehmeranschlußleitung, und mit einer zwischen dem bei der Gabelschaltung ankommenden Vierdrahtleitungszweig und dem von der Gabelschaltung abgehenden Vierdrahtleitungszweig vorgesehenen Übersprech- u./o. Echo-Kompensationsschaltung mit einem nach Maßgabe von Sendesignalimpulsen, die in dem bei der Gabelschaltung ankommenden Vierdrahtleitungszweig auftreten, ansteuerbaren Kompensationssignalspeicher, des ausgangsseitig zu dem von der Gabelschaltung abgehenden Vierdrahtleitungszweig führt, wobei ein Störsignal, das auf einen bei von in der Gegenrichtung zu übertragenden Signalimpulsen freier Zweidrahtleitung im ankommenden Vierdrahtleitungszweig auftretenden jeweils ersten Sendesignalimpuls hin im abgehenden Vierdrahtleitungszweig auftritt, seriell in den Kompensationssignalspeicher eingeschrieben wird und daraus zumindest während der nachfolgenden Verbindung auf jeden weiteren Sendesignalimpuls hin als Kompensationssignal wieder ausgelesen wird ; ein solches Digital-Fernmeldesystem ist erfindungsgemäß dadurch gekennzeichnet, daß der Kompensationssignalspeicher durch einen Umlaufspeicher mit einer Umlaufzeit gleich einem Vielfachen einer Bitzeitspanne gebildet ist und eine entsprechende Vielzahl von in jeweils einer Bitzeitspanne entsprechenden Abständen aufeinanderfolgenden Ausgängen aufweist, die durch eine nachfolgende Addierschaltung zusammengefaßt sind, über die die einzelnen Ausgänge in einer einer Reihe von Sendesignalimpulsen entsprechenden Reihenfolge jeweils für die Dauer des Vielfachen einer Bitzeitspanne mit dem abgehenden Vierdrahtleitungszweig verbindbar sind.The invention relates to a digital telecommunication system with at least one hybrid circuit between a four-wire line section and a two-wire line section, in particular for subscriber-side or exchange-side termination of a two-wire subscriber line, and with a cross-talk provided between the four-wire line branch arriving at the multi-line circuit and the four-wire line branch coming from the hybrid circuit. u./o. Echo compensation circuit with a compensation signal memory which can be controlled in accordance with the transmission signal pulses which occur in the four-wire line branch arriving at the hybrid circuit and which leads on the output side to the four-wire line branch leaving the hybrid circuit, an interference signal which is free on a signal pulse to be transmitted in the opposite direction Two-wire line occurs in the incoming four-wire line branch, the first transmission signal pulse occurring in the outgoing four-wire line branch, is written serially into the compensation signal memory and is read out therefrom as a compensation signal at least during the subsequent connection on each further transmission signal pulse; Such a digital telecommunication system is characterized according to the invention in that the compensation signal memory is formed by a circulation memory with a circulation time equal to a multiple of a bit time period and has a corresponding plurality of successive outputs, each corresponding to a bit time period, which are summarized by a subsequent adding circuit the individual outputs can be connected to the outgoing four-wire line branch in a sequence corresponding to a series of transmission signal pulses, each for the duration of a multiple of a bit period.

Die Erfindung, bei der die für das Einspeichern des Störsignals bei von in der Gegenrichtung übertragenen Signalimpulsen freier Zweidrahtleitung verfügbare Zeit durch die doppelte Signallaufzeit auf der Leitung oder auch durch eine Verzögerungsprozedur in der Erzeugung eines Antwortsignals bedingt sein kann und mit der bei mehr oder weniger schnell aufeinanderfolgenden Sendesignalimpulsen und - durch lange Echolaufzeiten bedingt - länger als eine Bitzeitspanne andauerndem Kompensationssignal eine Überlagerung von durch mehrfaches Auslesen einunddesselben Kompensationssignalspeichers gewonnenen, unter sich gleichförmigen Kompensationssignalen verbunden ist, gestattet eine sehr einfache und zugleich von einer Korrelation zwischen Sende-und Empfangssignalen unbeeinträchtigte Gewinnung eines Kompensationssignals, das vorteilhafterweise nicht eigens errechnet werden muß, so daß mit einer Kompensationssignalerrechnung verbundene Zeitschwierigkeiten vermieden sind. Nachdem keine hohen Verarbeitungsgeschwindigkeiten erforderlich sind, kann das angegebene Kompensationsprinzip auch bei höheren Übertragungs-Bitragen von z. B. 128 kbit/s Anwendung finden. Mit der Möglichkeit einer Realisierung der Kompensationssignalschaltung mit einem relativ einfachen Schaltungsaufbau nicht nur begrenzter Verarbeitungsgeschwindigkeit, sondern zugleich auch begrenzten Stromverbrauchs eröffnet die Erfindung zugleich auch die Möglichkeit einer Fernspeisbarkeit der Kompensationsschaltung, wie dies besonders bei einer teilnehmerseitig vorzusehenden Kompensationsschaltung erwünscht ist. Von Vorteil ist weiterhin die Eignung der Erfindung für eine teilnehmerseitige Kompensationssignalerzeugung auch im Rahmen von über Zweidraht-Vermittlungsstellen verlaufenden Fernmeideverbindungen mit demzufolge von Verbindung zu Verbindung sich ändernden Leitungsverhältnissen, indem zu Beginn der Übertragung nacheinander beide an einer Verbindung beteiligte Fernmelde-Teil-nehmerstellen sich jeweils das Kompensationssignal in einer Prozedur erzeugen können, deren der doppelten Signallaufzeit entsprechende Dauer im Vergleich zu sonst etwa erforderlichen Adaptionsprozeduren vernachlässigbar klein ist.The invention in which the time available for storing the interference signal when the two-wire line is free from signal pulses transmitted in the opposite direction can be caused by the double signal propagation time on the line or also by a delay procedure in the generation of a response signal and with which more or less quickly successive transmission signal pulses and - due to long echo propagation times - a longer than one bit period of the compensation signal, a superimposition of compensation signals obtained by multiple readings of the same compensation signal memory, connected among themselves, allows a very simple and at the same time unaffected by a correlation between transmit and receive signals a compensation signal , which advantageously does not have to be calculated separately, so that time difficulties associated with a compensation signal calculation are avoided. Since no high processing speeds are required, the specified compensation principle can also be used with higher transmission bit rates of e.g. B. 128 kbit / s application. With the possibility of implementing the compensation signal circuit with a relatively simple circuit structure, not only limited processing speed, but also limited power consumption, the invention also opens up the possibility of the compensation circuit being able to be remotely fed, as is particularly desirable in the case of a compensation circuit to be provided on the subscriber side. Another advantage is the suitability of the invention for subscriber-side compensation signal generation also in the context of remote switching connections running over two-wire exchanges with consequent line conditions changing from connection to connection, in that at the beginning of the transmission both telecommunication subscriber stations involved in a connection are in succession each can generate the compensation signal in a procedure, the duration of which corresponds to twice the signal propagation time is negligibly small in comparison with adaptation procedures that would otherwise be required.

In weiterer Ausgestaltung der Erfindung kann bei einer Gabelschaltung, die eine Zweidraht-Teilnehmeranschlußleitung teilnehmerseitig abschließt, jeweils bei einem Anschalten der Fern-Speisespannung ein solcher erster Sendesignalimpuls erzeugt und das daraus resultierende Störsignal in den zugehörigen Kompensationssignalspeicher eingeschrieben werden, aus dem es danach wiederholt jeweils auf einen Sendesignalimpuls hin als Kompensationssignal ausgelesen wird ; hiermit kann in zweckmäßiger Weise der Möglichkeit einer Unterbrechung des Speisestromkreises und eines daraus resultierenden Verlustes des bis dahin gespeicherten Störsignals, etwa aufgrund einer Leitungsumrangierung in der Vermittlungsstelle oder Umsteckens eines Teilnehmerapparates von einer Anschlußsteckdose an eine andere, Rechnung getragen werden.In a further embodiment of the invention, in the case of a hybrid circuit which terminates a two-wire subscriber line on the subscriber side, such a first transmission signal pulse is generated each time the remote supply voltage is switched on, and the resulting interference signal is written into the associated compensation signal memory, from which it is then repeated each time a transmission signal pulse is read out as a compensation signal; this can suitably take into account the possibility of an interruption in the supply circuit and a resultant loss of the interference signal stored up to that point, for example due to a line rearrangement in the switching center or a transfer of a subscriber set from one connection socket to another.

Bei einer Gabelschaltung, die eine vermittlungsstellenseitig von einer Gabelschaltung abgeschlossene Zweidraht-Teilnehmeranschlußleitung teilnehmerseitig abschließt, kann sich die Erfindung den Umstand, daß sich die durch Echos und Fehlanpassung bedingten Störsignale allenfalls bei einer Umrangierung der Teilnehmeranschlußleitung ändern, in der Weise zu Nutze machen, daß das Kompensationssignal beim ersten vom Teilnehmer ausgehenden Verbindungsaufbau, insbesondere etwa beim ersten von der Teilnehmerstelle ausgehenden Proberuf, in den zugehörigen Kompensationssignalspeicher eingeschrieben wird und daraus während späterer über die Zweidraht-Teilnehmeranschlußleitung verlaufender Verbindungen als Kompensationssignal wieder ausgelesen wird. In der umgekehrten Übertragungsrichtung kann bei einer Gabelschaltung, die eine leilnehmerstellenseitig von einer Gabelschaltung abgeschlossene Zweidraht-Teilnehmeranschlußleitung vermittlungsstellenseitig abschließt, das Kompensationssignal beim ersten zu dem betreffenden Teilnehmer hinführenden Verbindungsaufbau, insbesondere etwa beim ersten Proberückruf zu der betreffenden Teilnehmerstelle, in den zugehörigen Kompensationssignalspeicher eingeschrieben werden und daraus während späterer über die Zweidraht-Teilnehmeranschlußleitung veaufender Verbindungen als Kompensationssignal wieder ausgelesen werden.In the case of a hybrid circuit which terminates a two-wire subscriber line terminated on the exchange side by a hybrid circuit, the invention can take into account the fact that the Change echoes and mismatch-related interference signals at most when the subscriber line is rearranged, in such a way that the compensation signal is written into the associated compensation signal memory during the first connection establishment initiated by the subscriber, in particular, for example, during the first test call originating from the subscriber station, and from there during later connections running over the two-wire subscriber line are read out again as a compensation signal. In the reverse direction of transmission, in the case of a hook-up circuit which terminates a two-wire subscriber line terminated at the subscriber station end by a hook-up circuit, the compensation signal can be written into the associated compensation signal memory when the first connection is made to the subscriber concerned, in particular, for example, when the test call is first called back to the subscriber station concerned therefrom can be read out again as compensation signal during later connections veverender on the two-wire subscriber line.

Zweckmäßigerweise wird in weiterer Ausgestaltung der Erfindung das Störsignal zunächst quantisiert und codiert und dann in Form des so erhaltenen Binärsignals in den Kompensationssignalspeicher eingeschrieben, der dann über eine nachfolgende Digital/Analog-Wandlerschaltung 'zum abgehenden Vierdrahtleitungszweig führt ; dabei wird das Störsignal vorzugsweise über einen Deltamodulator in Form des so erhaltenen AM-Signals in den dann über eine Deltademodulatorschaltung zum abgehenden Vierdrahtleitungszweig führenden Kompensationssignalspeicher eingeschrieben.In a further embodiment of the invention, the interference signal is expediently first quantized and encoded and then written into the compensation signal memory in the form of the binary signal thus obtained, which then leads via a subsequent digital / analog converter circuit to the outgoing four-wire line branch; the interference signal is preferably written via a delta modulator in the form of the AM signal thus obtained into the compensation signal memory which then leads via a delta modulator circuit to the outgoing four-wire line branch.

Ist das Störsignal digitalisiert (vorzugsweise in AM-Darstellung) im Kompensationssignalspeicher enthalten, wobei dann dem Speicherausgang bzw. jedem Speicherausgang ein Digital/Analog-Wandler nachgeschaltet ist, so kann der Kompensationssignalspeicher in weiterer Ausgestaltung der Erfindung durch ein Umlauf-Schieberegister gebildet sein.If the interference signal is digitized (preferably in an AM representation) in the compensation signal memory, with a digital / analog converter then being connected downstream of the memory output or each memory output, the compensation signal memory can be formed in a further embodiment of the invention by a circulation shift register.

Neben dem Umlaufspeicher kann in weiterer Ausgestaltung der Erfindung ein statischer Speicher vorgesehen sein, in den das Kompensationssignal ebenfalls eingeschrieben wird, um daraus jeweils zu Beginn eines neuen Übertragungsvorganges neu in den Umlaufspeicher eingelesen werden.In a further embodiment of the invention, in addition to the circulation memory, a static memory can be provided, into which the compensation signal is also written, so that it can be read into the circulation memory again at the beginning of a new transmission process.

Anhand der Zeichnungen sei die Erfindung noch näher erläutert.The invention will be explained in more detail with reference to the drawings.

Dabei zeigt

  • Figur 1 schematisch ein Zweidraht-Vierdraht-Fernmelde-system und ein Beispiel für ein darin auftretendes Störsignal ;
  • Figur 2 zeigt ein Ausführungsbeispiel eines Digital-Fernmeldesystems mit Störsignalkompensation gemäß der Erfindung.
  • Figur 3 und Figur 4 zeigen weitere schaltungstechnische Einzelheiten einer entsprechenden Kompensationsschaltung.
It shows
  • Figure 1 shows schematically a two-wire four-wire communication system and an example of an interference signal occurring therein;
  • Figure 2 shows an embodiment of a digital telecommunication system with interference signal compensation according to the invention.
  • Figure 3 and Figure 4 show further circuit details of a corresponding compensation circuit.

In der Zeichnung Fig. 1 oben ist schematisch ein Fernmeldesystem mit einer zwischen zwei Vierdrahtleitungsabschnitten VLT, VLv liegenden, beiderseits mit einer Gabelschaltung GT bzw. Gv abgeschlossenen Zweidrahtleitung ZL dargestellt, wobei angedeutet ist, daß diese Zweidrahtleitung ZL beispielsweise durch Durchmesseränderungen der Leitungsadern bedingte Stoßstellen R aufweist. An solchen Stoßstellen und ebenso an einer nicht angepaßten Gabelschaltung treten bei einer Signalübertragung Signalreflexionen auf, die zur Folge haben, daß beispielsweise auf einen in dem bei der Gabelschaltung GT ankommenden Vierdrahtleitungszweig VS auftretenden, über Gabelschaltung GT und Zweidrahtleitung ZL zur Gegenstelle Gv-VLv übertragenen Signalimpuls hin in dem von der Gabelschaltung GT abgehenden Vierdrahtleitungszweig VE ein Störsignal es auftritt, wie es etwa in Fig. 1 unten dargestellt ist ; dabei kann in dem vorderen Teil eines solchen Störsignals auch ein Signalanteil enthalten sein, der direkt auf ein durch eine ungenügende Gabelsperrdämpfung bedingtes Übersprechen vom Vierdrahtleitungszweig VS auf den Vierdrahtleitungszweig VE zurückgeht.In the drawing Fig. 1 above, a telecommunications system is shown schematically with a two-wire line ZL lying between two four-wire line sections VL T , VL v , closed on both sides with a hook-up circuit G T or G v , whereby it is indicated that this two-wire line ZL, for example, by changes in diameter of the Has conduction joints R conditional. At such joints and also at a non-adapted hybrid circuit, signal reflections occur during signal transmission, which has the consequence that, for example, a four-wire line branch VS arriving at the hybrid circuit G T , via hybrid circuit G T and two-wire line ZL to the remote station G v - VL v transmitted signal pulse in the four-wire line branch VE going from the hybrid circuit G T, an interference signal occurs, as is shown, for example, in FIG. 1 below; In this case, the front part of such an interference signal can also contain a signal component which is directly attributable to crosstalk from the four-wire line branch VS to the four-wire line branch VE, which is caused by insufficient fork blocking.

Eben ein solches auf einen ersten Sendesignalimpuls hin in einer für eine Signalübertragung in der Gegenrichtung nicht verfügbaren Zeitspanne auftretendes Störsignal wird nun erfindungsgemäß seriell in einen Kompensationssignalspeicher eingeschrieben und daraus zumindest während der nachfolgenden Signalübertragung auf jeden weiteren Sendesignalimpuls hin als Kompensationssignal wieder ausgelesen, das dann mit einer Phasendrehung von 180° in dem von der Gabelschaltung abgehenden Vierdrahtleitungszweig störsignalkompensierend wirksam wird.Such an interference signal occurring in response to a first transmission signal pulse in a time period that is not available for signal transmission in the opposite direction is now serially written into a compensation signal memory and is read out therefrom as a compensation signal at least during the subsequent signal transmission upon each further transmission signal pulse, which is then read out with a Phase rotation of 180 ° in the four-wire branch coming from the hybrid circuit has an interference signal compensation effect.

In der Zeichnung Fig. 2 ist schematisch in einem zum Verständnis der Erfindung erforderlichen Umfange ein Digital-Fernmeldesystem mit einer zwischen einem Vierdrahtleitungsabschnitt VL und einem Zweidrahtleitungsabschnitt ZL liegenden Gabelschaltung G dargestellt, wobei es sich bei der Zweidrahtleitung ZL und der Gabelschaltung G um eine Zweidraht-Teilnehmeranschlußleitung und deren teilnehmerseitigen oder vermittlungsstellenseitigen Abschluß handeln kann.In the drawing Fig. 2 is shown schematically in a scope necessary for understanding the invention, a digital telecommunications system with a hybrid circuit G between a four-wire line section VL and a two-wire line section ZL, the two-wire line ZL and the multi-circuit circuit G being a two-wire Subscriber line and their subscriber-side or exchange-side termination can act.

Der Vierdrahtleitungsabschnitt VL weist in seinem bei der Gabelschaltung G ankommenden Sendezweig VS eine Digitalsignal-Sendeschaltung DS zum Aussenden von Sendesignalimpulsen s vorgegebener Form bzw. mit einem vorgegebenen Schwerpunkt ihres Frequenzspektrums auf ; in Fig. 2 ist dazu angedeutet, daß die Sendeschaltung DS ihr zugeführte Binärsignalimpulse d in AMI-Signalimpulse s umsetzen möge.The four-wire line section VL has, in its transmission branch VS arriving at the hybrid circuit G, a digital signal transmission circuit DS for transmitting transmission signal pulses s of a predetermined form or with a predetermined center of gravity of its frequency spectrum; In Fig. 2 it is indicated that the transmission circuit DS may convert its supplied binary signal pulses d into AMI signal pulses s.

In seinem von der Gabelschaltung G abgehenden Empfangszweig VE weist der Vierdrahtleitungsabschnitt VL eine Digitalsignalempfangsschaltung mit einer Filter- und ggf. auch Entzerrer---Schaltung F und einem Digitalsignalempfänger E auf, der die von der Filterschaltung F abgegebenen Signale in entsprechende Binärsignale umsetzen möge, wobei bei Zugrundelegung der in Fig. 1 angedeuteten Signalformen ein solcher Empfangssignalwandler im Prinzip mit einer Gleichrichterschaltung realisiert sein kann.The four-wire line section VL has a digital signal receiving circuit with a filter and, if necessary, an equalizer in its receiving branch VE which branches off the hybrid circuit G. --Circuit F and a digital signal receiver E, which may convert the signals emitted by the filter circuit F into corresponding binary signals, with the reception of the signal shapes indicated in FIG. 1, such a received signal converter can in principle be implemented with a rectifier circuit.

Die Sendesignalimpulse s gelangen vom Sendezweig VS des Vierdrahtleitungsabschnittes VL über die Gabelschaltung G zur Zweidrahtleitung ZL, über die sie zu der in Fig. 2 nicht näher dargestellten Gegenstelle des Digital-Fernmeldesystems übertragen werden ; in umgekehrter Übertragungsrichtung gelangen von der Gegenstelle herrührende, über die Zweidrahtleitung ZL übertragene Signalimpulse über die Gabelschaltung G als Empfangssignalimpulse zum Empfangszweig VE des Vierdrahtleitungsabschnittes VL. Weist die Zweidrahtleitung ZL Reflexionsstellen auf, wie sie durch Stellen sprunghafter Änderungen von Leitungsparametern gegeben sein können, so gelangen außer den eigentlichen Empfangssignalimpulsen aber auch Echos der Sendesignalimpulse s zum Empfangszweig VE des Vierdrahtleitungsabschnitts VL, und außerdem können bei begrenzter Gabelsperrdämpfung auch direkt Anteile der Sendesignalimpulse s in den Empfangszweig VE gelangen. Im Empfangszweig VE tritt dann jeweils ein Empfangssignalgemisch aus den eigentlichen Empfangssignalimpulsen und einem aus Echosignalen und Übersprechsignalen zusammengesetzten Störsignal auf ; dieses Störsignal ist zu kompensieren.The transmission signal pulses s pass from the transmission branch VS of the four-wire line section VL via the hybrid circuit G to the two-wire line ZL, via which they are transmitted to the remote station of the digital telecommunications system, which is not shown in FIG. 2; in the reverse direction of transmission, signal pulses originating from the remote station and transmitted via the two-wire line ZL pass through the hybrid circuit G as received signal pulses to the receiving branch VE of the four-wire line section VL. If the two-wire line ZL has reflection points, as can be caused by sudden changes in line parameters, then in addition to the actual received signal pulses, echoes of the transmitted signal pulses s also reach the receiving branch VE of the four-wire line section VL, and, in addition, with limited fork blocking, portions of the transmitted signal pulses s can also be obtained directly get into the reception branch VE. In the reception branch VE there then occurs a received signal mixture of the actual received signal pulses and an interference signal composed of echo signals and crosstalk signals; this interference signal must be compensated.

Zur Kompensation eines solchen Störsignals ist zwischen dem ankommenden Vierdrahtleitungszweig VS und dem abgehenden Vierdrahtleitungszweig VE eine Übersprech- u./o. Echo-Kompensationsschaltung mit einem nach Maßgabe von Sendesignalimpulsen, die im ankommenden Vierdrahtleitungszweig VS auftreten, ansteuerbaren Kompensationssignalspeicher UR vorgesehen. Der Kompensationssignalspeicher UR ist dabei durch einen Umlaufspeicher vorzugsweise in Form eines zu einem Ring geschlossenen sog. Umlauf-Schieberegisters gebildet, dessen Umlaufzeit gleich einem Vielfachen einer Sendesignal-Bitzeitspanne (TB;t in Fig. 1) ist und der eine entsprechende Vielzahl von in jeweils einer solchen Bitzeitspanne entsprechenden Abständen aufeinanderfolgenden Ausgängen aufweist ; in Fig. 2 ist dabei angedeutet, daß die Umlaufzeit gleich dem Vierfachen einer Bitzeitspanne ist und daß das Umlauf-Schieberegister UR dementsprechend vier in entsprechenden Abständen aufeinanderfolgende Ausgänge a1, a2, a3, a4 aufweist. Jeder Umlaufspeicherausgang a ist über eine Verknüpfungsschaltung SI mit einem nachfolgenden Digital-/Analog-Wandler D/A verbindbar, der bei im Umlauf-Schieberegister UR in ΔM-Darstellung gespeichertem Kompensationssignal nur aus einem RC-Glied zu bestehen braucht. Die Ausgänge der Digital/Analog-Wandler D/A führen, über eine passive Addierschaltung ADD zusammengefaßt,. zu dem Kompensationssignaleingang k des beispielsweise mit einem Differenzverstärker zu realisierenden Kompensationsgliedes K, das in den von der Gabelschaltung G abgehenden Vierdrahtleitungszweig VE eingefügt ist.To compensate for such an interference signal, a crosstalk and / or is between the incoming four-wire line branch VS and the outgoing four-wire line branch VE. Echo compensation circuit with a compensation signal memory UR which can be controlled in accordance with transmission signal pulses which occur in the incoming four-wire line branch VS is provided. The compensation signal memory UR is formed by a circulation memory, preferably in the form of a so-called circulation shift register closed to a ring, the circulation time of which is equal to a multiple of a transmission signal bit period ( TB; t in FIG. 1) and which is a corresponding multiplicity of in each case has intervals of successive outputs corresponding to such a bit time period; 2 indicates that the round trip time is equal to four times a bit time period and that the round trip shift register UR accordingly has four outputs a1, a2, a3, a4 which follow one another at corresponding intervals. Each circulating memory output a can be connected via a logic circuit SI to a subsequent digital / analog converter D / A, which only has to consist of one RC element in the case of a compensation signal stored in the circulating shift register UR in ΔM representation. The outputs of the digital / analog converter D / A lead, combined via a passive adder circuit ADD. to the compensation signal input k of the compensation element K to be implemented, for example, with a differential amplifier, which is inserted into the four-wire line branch VE going out from the hybrid circuit G.

Hinter diesem Kompensationsglied K ist an den abgehenden Vierdrahtleitungszweig VE der Eingang eines Analog/Digital-Wandlers A/D, bei ΔM-Darstellung des im Umlauf-Schieberegister UR zu speichernden Kompensationssignals ein Deltamodulator, angeschlossen, der ausgangsseitig zu dem Einschreibeingang des Umlaufschieberegisters UR führt. Dabei kann, wie dies auch in Fig. 2 angedeutet ist, dem Kompensationsglied K zunächst ein fest eingestellter Verstärker nachgeschaltet sein, der die Signale auf einen für die A/D-Wandlung geeigneten Pegel bringt und die Dämpfung des passiven Additionsnetzwerks ADD ausgleicht. Über den Analog/Digital-Wandler A/D wird das in Fig. 2 angedeutet Störsignal es (siehe auch Fig. 1 unten), das auf einen - bei von in der Gegenrichtung zu übertragenden Signalimpulsen freier Zweidrahtleitung ZL - im ankommenden Vierdrahtleitungszweig VS auftretenden ersten Sendesignalimpuls s hin im abgehenden Vierdrahtleitungszweig VE auftritt, quantisiert und codiert ; in Form des so erhaltenen Binärsignals, im Beispiel OM-Signals, wird das Störsignal dann in das Umlauf-Schieberegiste UR seriell eingeschrieben.Behind this compensation element K is connected to the outgoing four-wire line branch VE the input of an analog / digital converter A / D, with ΔM representation of the compensation signal to be stored in the circulation shift register UR, a delta modulator, which leads on the output side to the write-in input of the circulation shift register UR. In this case, as is also indicated in FIG. 2, the compensation element K can first be followed by a permanently set amplifier which brings the signals to a level suitable for the A / D conversion and compensates for the attenuation of the passive addition network ADD. The interference signal indicated in FIG. 2 is obtained via the analog / digital converter A / D (see also FIG. 1 below), which occurs when the two-wire line ZL is free in the incoming four-wire line branch VS when the signal pulses are transmitted in the opposite direction Transmitted signal pulse s occurs in the outgoing four-wire line branch VE, quantized and encoded; in the form of the binary signal thus obtained, in the example OM signal, the interference signal is then written serially into the circulation shift register UR.

Wie oben schon erwähnt wurde, kann dies bei einem teiInehmerseitig die Zweidraht-Teilnehmeranschlußleitung ZL abschließenden Vierdrahtleitungsabschnitt VL jeweils bei einem (Wieder-) Anschalten der Speisespannung an den Teilnehmerapparat geschehen (und etwa mit Hilfe eines von der Speisespannung beaufschlagten Differenziergliedes initiert werden) oder auch beim ersten von der Teilnehmerstelle ausgehenden Proberuf ; bei einem vermittlungsstellenseitig die Zweidraht-Teilnehmeranschlußleitung ZL abschließenden Vierdrahtleitungsabschnitt VL kann das Einschreiben eines Störsignals etwa beim ersten Proberückruf zum Teilnehmer geschehen.As already mentioned above, this can take place in the case of a four-wire line section VL terminating the two-wire subscriber connection line ZL on the subscriber side, each time the supply voltage is (re) switched on to the subscriber apparatus (and initiated, for example, with the aid of a differentiating element acted upon by the supply voltage), or also in first trial call originating from the subscriber station; in the case of a four-wire line section VL terminating the two-wire subscriber line ZL on the exchange, an interference signal can be written in, for example, on the first trial call back to the subscriber.

In dem in Fig. 2 skizzierten Ausführungsbeispiel eines Digital-Fernmeldesystems gemäß der Erfindung ist parallel zum Umiauf-Schieberegister UR ein statischer Speicher SS vorgesehen, der das in den Umlaufspeicher UR eingeschriebene Störsignal ebenfalls aufnimmt ; während das digitalisierte Störsignal im Umlaufspeicher UR rotiert, so daß es in jeder Sendesignal-Bitzeitspanne an einemder Speicherausgänge a1 ... a4 ausgelesen werden kann, bleibt es im statischen Speicher SS für spätere Übertragungsvorgänge und ggf. auch für Kontrollzwecke fest gespeichert.In the exemplary embodiment of a digital telecommunication system according to the invention outlined in FIG. 2, a static memory SS is provided in parallel with the circulation shift register UR and also stores the interference signal written into the circulation memory UR; while the digitized interference signal rotates in the circulation memory UR, so that it can be read out at each of the transmit signal bit periods at one of the memory outputs a1 ... a4, it remains permanently stored in the static memory SS for later transmission processes and possibly also for control purposes.

In einem solchen statischen Speicher SS kann das Störsignal insbesondere dann gespeichert bleiben, wenn es im-Umlauf-Schieberegister UR bei einem Abschalten des Taktes in den Pausen zwischen jeweils zwei Verbindungen verloren gehen könnte, etwa weil aus Gründen des Leistungsbedarfs der Umlaufspeicher UR bei abgeschaltetem Takt auch keinen nennenswerten Speisestrom verbrauchen soll. Der parallelgeschaltete statische Speicher SS kann dagegen ggf. entfallen, wenn das verwendete Umlauf-Schieberegister (Umlaufspeicher) UR nach Abschalten des Takts die Information solange hält, wie die (Fern-) Speisespannung anliegt.In such a static memory SS, the interference signal can remain stored in particular if it could be lost in the circulation shift register UR when the clock is switched off in the pauses between two connections, for example because of the power requirement of the circulation memory UR when the clock is switched off also no noteworthy Should consume feed current. The parallel-connected static memory SS, on the other hand, can possibly be omitted if the circulation shift register (circulation memory) UR used keeps the information as long as the (remote) supply voltage is present after the clock has been switched off.

Der Analog/Digital-Wandler A/D, der im Beispiel nur während der ersten vier Sendesignal-Bitperioden das digitalisierte Störsignal (es in Fig. 1 unten und Fig. 2) in den Kompensationssignalspeicher UR eingibt, kann in der nachfolgenden Zeit ebenfalls für Kontrollzwecke genutzt werden : Immer dann, wenn von der Gegenseite her, entweder zufällig (Serie von « 0 »-Bits) oder durch eine Prozedur gesteuert, keine Signalimpulse ankommen, kann der Analog/Digital-Wandler als Pegeldetektor genutzt werden, und die Genauigkeit des abgespeicherten Kompensationssignals zu prüfen.The analog / digital converter A / D, which in the example only inputs the digitized interference signal (it in FIG. 1 below and FIG. 2) into the compensation signal memory UR during the first four transmission signal bit periods, can also be used for control purposes in the following time can be used: Whenever no signal impulses arrive from the opposite side, either randomly (series of "0" bits) or controlled by a procedure, the analog / digital converter can be used as a level detector and the accuracy of the stored Check compensation signal.

Zur Steuerung des Einschreibens des auf einen - im skizzierten Digital-Fernmeldesystem beispielsweise bei einem vom Vierdrahtleitungsabschnitt VL über die Zweidrahtleitung ZL ausgesandten ersten Proberuf erzeugten - ersten Sendesignalimpuls s hin im abgehenden Vierdrahtleitungsabschnitt VE auftretenden Störsignals es (in Fig 1 unten und Fig. 2) in den Umlaufspeicher UR und den statischen Speicher SS und der Übernahme des im statischen Speicher SS enthaltenen digitalisierten Störsignals in den Umlaufspeicher UR bei späteren Übertragungsvorgängen sowie zur Steuerung von Prozeduren zur Kontrolle und ggf. Korrektur des abgespeicherten Signals kann eine entsprechende Steuereinrichtung Ste vorgesehen, wie dies auch in Fig. 2 angedeutet ist.To control the writing of the first transmission signal pulse s, which occurs in the outlined four-wire line section VE, in the outlined four-wire line section VE, in the outlined four-wire line section VE, for example in a first test call emitted by the four-wire line section VL via the two-wire line ZL A corresponding control device Ste can provide the circulation memory UR and the static memory SS and the transfer of the digitized interference signal contained in the static memory SS into the circulation memory UR during later transmission processes and for controlling procedures for checking and, if necessary, correcting the stored signal is indicated in Fig. 2.

Die für den Umlaufspeicher UR bzw. für den statischen Speicher SS erforderliche Speicherkapazität ist relativ gering, da die Amplitude eines zu kompensierenden Echos mit zunehmender Laufzeit wegen der doppelten Leitungsdämpfung schnell abnimmt, wie dies auch aus Fig. 1 unten ersichtlich wird. Die Speicherkapazität ist dabei von der Abtastfrequenz des Analog/Digital-Wandlers A/D abhängig ; je höher die Abtastfrequenz ist, desto kleiner sind die Quantisierungsverzerrungen des Störsignals und desto kleiner ist der nach der Kompensation verbleibende Restfehler. Nimmt man im Beispiel eine Kompensation über vier Sendesignal- oder, allgemeiner gesagt, Leitungssignal-Bitperioden hinweg vor, so ergibt sich beispielsweise bei einem 64- kbit/s-Leitungssignal und - bei AM-Darstellung des Kompensationssignals - einer Abtastfrequenz - und zugleich Schiebetaktfrequenz - von 1,28 MHz (entsprechend 20 Abtastwerten je Leitungssignalbit) eine erforderliche Speicherkapazität von 80 Bit.The storage capacity required for the circulating memory UR or for the static memory SS is relatively small, since the amplitude of an echo to be compensated rapidly decreases with increasing transit time because of the double line attenuation, as can also be seen from FIG. 1 below. The storage capacity is dependent on the sampling frequency of the analog / digital converter A / D; the higher the sampling frequency, the smaller the quantization distortions of the interference signal and the smaller the residual error remaining after the compensation. If, in the example, compensation is carried out over four transmission signal or, more generally, line signal bit periods, this results, for example, in the case of a 64 kbit / s line signal and - in the AM representation of the compensation signal - a sampling frequency - and at the same time shift clock frequency - of 1.28 MHz (corresponding to 20 samples per line signal bit), a required memory capacity of 80 bits.

Die im Beispiel dann in einem Abstand von jeweils 20 Bit des digitalisierten Störsignals vorgesehenen vier Speicherausgänge a1 ... a4 sind, wie schon erwähnt, jeweils über eine Verknüpfungsschaltung SI mit dem jeweils nachfolgenden Digital/Analog-Wandler, im Beispiel Deltademodulator, D/A verbindbar. Diese Verknüpfungsschaltungen SI können bei einem binären Leitungscode, d. h. bei Sendesignalimpulsen einer Polarität, jeweils durch ein einfaches Schaltglied gebildet sein ; bei einem ternären Leitungscode, d. h. bei Sendesignalimpulsen abwechselnd positiver und negativer Polarität, und in AM-Darsteiiung gespeichertem Störsignal können die Verknüpfungsschaltungen SI jeweils durch eine Parallelschaltung eines einfachen Schaltgliedes und eines gesteuerten NICHT-Gliedes gebildet sein, so daß je nach dem Vorzeichen des zu kompensierenden Störsignals das Kompensationssignal invertiert oder nicht invertiert wird. Es sei hier bemerkt, daß in Abweichung von der Fig. 2 gegebenen Darstellung statt einer vor der Digital/Analog-Wandlung vorgenommenen Invertierung des noch in Digitaldarstellung vorliegenden Kompensationssignals auch nach der Digital/Analog-Wandlung eine Phasenumkehr des dann in Analogdarstellung vorliegenden Kompensationssignals vorgenommen werden kann, ohne daß dies jedoch in der Zeichnung näher dargestellt ist.The four memory outputs a1 ... a4 then provided in the example, each at a distance of 20 bits of the digitized interference signal, are, as already mentioned, each via a logic circuit SI with the respective subsequent digital / analog converter, in the example delta modulator, D / A connectable. These logic circuits SI can with a binary line code, i. H. in the case of transmission signal pulses of one polarity, in each case be formed by a simple switching element; with a ternary line code, d. H. with transmission signal pulses alternating positive and negative polarity, and in the AM signal stored interference signal, the logic circuits SI can each be formed by a parallel connection of a simple switching element and a controlled NOT element, so that, depending on the sign of the interference signal to be compensated, the compensation signal is inverted or not is inverted. It should be noted here that, in deviation from the illustration given in FIG. 2, instead of an inversion of the compensation signal still present in the digital representation before the digital / analog conversion, a phase reversal of the compensation signal then present in the analog representation is also carried out after the digital / analog conversion can, but this is not shown in the drawing.

Jeweils auf einen im ankommenden Vierdrahtleitungszweig VS auftretenden Sendesignalimpuls hin wird dann zur Kompensation des dadurch im abgehenden Vierdrahtleitungszweid VE hervorgerufenen Störsignals durch entsprechende Entriegelung eines der Schalt- bzw. NICHT-Glieder für die Dauer des im Beispiel Vierfachen einer Leitungssignal-Bitzeitspanne das im Umlaufspeicher UR als Kompensationssignal digitalisiert gespeicherte Störsignal ausgelesen und über Digital/Analog-Wandler D/A und Addierschaltung ADD dem Kompensationsglied K zugeführt. Die Auswahl des jeweils in Frage kommenden Ausgangs a des Umlaufregisters UR, in dem das als Kompensationssignal dienende gespeicherte Störsignal umläuft, kann dabei durch eine entsprechende Steuereinrichtung Sta vorgenommen werden, wie dies auch in Fig. 2 angedeutet ist. Dabei werden die einzelnen Ausgänge a1, a2, a3, a4 des Umlaufregisters UR in einer dem Muster der in einer Folge von Sendesignalbits enthaltenen Sendesignalimpulse (« 1 »-Bits) entsprechenden Reihenfolgen jeweils für die Dauer des im Beispiel Vierfachen einer Sendesignal-Bitzeitspanne entriegelt, so daß das im Umlauf-Schieberegister UR gespeicherte Störsignal ggf. an mehreren Speicherausgängen a1 ... a4 gleichzeitig mit jeweils unterschiedlicher Phasenlage ausgelesen wird ; durch die Addierschaltung ADD werden die einzelnen Signale dann durch Überlagerung zu einem kombinierten Kompensationssignal zusammengefaßt, wie es dann gerade auch erforderlich ist, um das gerade im abgehenden Vierdrahtleitungszweig VE auftretende, entsprechende Überlagerungen aufweisende Störsignal zu kompensieren.In each case in response to a transmission signal pulse occurring in the incoming four-wire line branch VS, in order to compensate for the interference signal thereby caused in the outgoing four-wire line branch VE, corresponding unlocking of one of the switching or NOT elements for the duration of four times a line signal bit time period in the example, that in the circulation memory UR Compensation signal digitized stored interference signal read out and supplied to the compensation element K via digital / analog converter D / A and adding circuit ADD. The selection of the output a of the circulation register UR in question, in which the stored interference signal serving as the compensation signal circulates, can be carried out by a corresponding control device Sta, as is also indicated in FIG. 2. The individual outputs a1, a2, a3, a4 of the circulation register UR are unlocked in a sequence corresponding to the pattern of the transmission signal pulses (“1” bits) contained in a sequence of transmission signal bits, each for the duration of four times a transmission signal bit period in the example, so that the interference signal stored in the revolving shift register UR may be read out simultaneously at several memory outputs a1 ... a4, each with a different phase position; the adder circuit ADD then combines the individual signals by superimposition to form a combined compensation signal, as is then also required in order to compensate for the interference signal which is present in the outgoing four-wire line branch VE and has corresponding superimpositions.

An dieser Stelle sei noch besonders bemerkt, daß es in weiterer Ausgestaltung der Erfindung auch möglich ist, nacheinander mehrere jeweils durch einen eigenen Sendesignalimpuls erzeugte Störsignale jeweils in einem eigenen Umlaufspeicher (entsprechend dem Umlaufspeicher UR in Fig. 2) und ggf. auch eingenem statischen Speicher (entsprechend dem statischen Speicher SS in Fig. 2) einzuschreiben und daraus zumindest während der nachfolgenden Verbindung auf jeden weiteren Sendesignalimpuls hin unter Mittelwertbildung zur Bildung eines Kompensationssignals wieder auszulesen ; dies ermöglicht es, während eines einzelnen Störsignales etwa vorhandene Fremdstörungen zu eliminieren.At this point, it should be particularly noted that in a further embodiment of the invention it is also possible to consecutively produce a plurality of interference signals each generated by a separate transmission signal pulse in a separate circulation memory (corresponding to the circulation memory UR in FIG. 2) and possibly also a static memory (corresponding to the static memory SS in FIG. 2) and read out therefrom at least during the subsequent connection upon each further transmission signal pulse with averaging to form a compensation signal; this makes it possible to eliminate any external interference that may be present during a single interference signal.

Abschließend sei noch ein Blick auf die Zeichnungen Fig. 3 und Fig. 4 geworfen, die schaltungstechnische Einzelheiten der oben erwähnten Steuereinrichtungen Sta und Ste erkennen lassen.Finally, a look at the drawings in FIGS. 3 and 4 is shown, which show circuit details of the control devices Sta and Ste mentioned above.

Die Steuereinrichtung Sta kann, wie dies in Fig. 3 angedeutet ist, ein in gleicher Weise wie das Umlauf-Schieberegister UR (in Fig. 2) ausgebildetes Umlauf-Schieberegister mit im Beispiel wiederum vier Ausgängen aufweisen, in welchem phasengleich mit dem Anfang des im Umlauf-Schieberegister UR (in Fig. 2) gespeicherten Störsignals ein Steuerbit umläuft und an dessen Ausgänge jeweils über ein durch einen (positiven bzw. negativen) Sendesignalimpuls (s in Fig. 2) entriegeltes UND-Glied ein für die Dauer von im Beispiel vier Leitungssignal-Bitzeitspannen aktivierbares bistabiles Kippglied angeschlossen ist, welches das jeweils zu entriegelnde Verknüpfungsglied (Schaltglied bzw. NICHT-Glied) SI (in Fig. 2) steuert.The control device Sta can, as indicated in FIG. 3, have a circulation shift register in the same way as the circulation shift register UR (in FIG. 2) with four outputs in the example, in which phase with the beginning of the Circulation shift register UR (in Fig. 2) stored interference signal rotates a control bit and at the outputs of each of them via an AND gate unlocked by a (positive or negative) transmission signal pulse (s in Fig. 2) for a duration of four in the example Line signal bit time periods activatable bistable flip-flop is connected, which controls the logic element (switching element or NOT element) SI to be unlocked in each case (in FIG. 2).

Die Steuereinrichtung Ste kann, wie dies in Fig. 4 angedeutet ist, ein durch einen Sendesignalimpuls (d in Fig. 2) für die Dauer von im Beispiel vier Leitungssignal-Bitzeitspannen aktivierbares bistabiles Kippglied aufweisen, das über ein nachfolgendes, von einem weiteren bistabilen Kippglied her nach einer ersten Aktivierung des ersteren Kippgliedes gesperrtes Sperrglied den Einschreibeingang des Umlauf-Schieberegisters UR entriegelt; dabei kann von dem Ausgang des Sperrgliedes über eine Serienschaltung eines NICHT-Gliedes und eines Differenziergliedes ein Steuersignal zur Parallelübernahme des in das Umlauf-Schieberegister UR eingeschriebenen Störsignals in den statischen Speicher SS (in Fig. 2) und von dem Ausgang des erstgenannten bistabilen Kippgliedes ein Anlaßsignal für einen Abtast- und Schiebetaktgenerator (Takt in Fig. 2) abgenommen werden. Zu Beginn späterer Verbindungen bzw. Übertragungsvorgänge kann die Steuereinrichtung Ste jeweils auf ein ihr zugeführtes Verbindungsanfangszeichen v hin über ein durch einen Sendesignalimpuls entriegelbares UND-Glied ein Steuersignal zur Parallelübernahme des im statischen Speicher SS gespeicherten Störsignals in den Umlaufspeicher UR und zum Wiederanlassen des Schiebetaktgenerators Takt (in Fig. 2) abgeben.The control device Ste can, as indicated in FIG. 4, have a bistable flip-flop that can be activated by a transmission signal pulse (d in FIG. 2) for the duration of four line signal bit periods in the example, which is connected via a subsequent flip-flop by another bistable flip-flop after a first activation of the first flip-flop locked blocking element unlocks the write input of the circulation shift register UR; In this case, a control signal for parallel transfer of the interference signal written into the circulation shift register UR into the static memory SS (in FIG. 2) and from the output of the first-mentioned bistable trigger element can be input from the output of the blocking element via a series connection of a NOT element and a differentiating element Starting signal for a sample and shift clock generator (clock in Fig. 2) are taken. At the beginning of later connections or transmission processes, the control device Ste can send a control signal to a connection start signal v supplied to it via an AND gate that can be unlocked by a transmission signal pulse, for parallel transfer of the interference signal stored in the static memory SS into the circulation memory UR and for restarting the shift clock generator clock ( in Fig. 2).

Claims (9)

1. A digital telecommunications system with at least one hybrid circuit (G) which is located between a four-wire line section (VL) and a two-wire line section (ZL), in particular for terminating a two-wire subscriber connection line (ZL) at the subscriber end or at the exchange end, and with a cross-talk and/or echo compensation circuit which is arranged between the four-wire line arm (VS) incoming to the hybrid circuit (G) and the four-wire line arm (VE) outgoing from the hybrid circuit (G), having a compensation signal store (UR) which can be operated in accordance with transmitted signal pulses which occur in the four-wire line arm (VS) incoming to the hybrid circuit (G) and which feeds at its output end to the four-wire line arm (VE) outgoing from the hybrid circuit (G), where an interference signal (es), which occurs in the outgoing four-wire line arm (VE) in response to a first transmitted signal pulse (s), which itself occurs in the incoming four-wire line arm (VS) when the two-wire line (ZL) is free of signal pulses to be transmitted in the opposite direction, is input in serial fashion into the compensation signal store (UR) and is read out therefrom compensation signal (k), at least during the following connection, in response to each further transmitted signal pulse (s), characterised in that the compensation signal store (UR) is formed by a cyclic store having a cycle time which is equal to a multiple of a bit interval and has a corresponding number of outputs (a1, a2, a3, a4) which follow one another at intervals in each case corresponding to one bit intervals and which are assembled by a following adder circuit (ADD) via which the individual outputs can be connected to the outgoing four-wire line arm (VE) for the duration of the multiple of one bit interval, in a sequence corresponding to a sequence of transmitted signal pulses (s).
2. A digital telecommunications system as claimed in claim 1, characterised in that the interference signal (es) is quantized and coded and is then input, in the form of the binary signal obtained in this manner, into the compensation signal store (UR) whose store outputs are each followed by a digital/analogue converter (D/A).
3. A digital telecommunications system as claimed in claim 2, characterised in that the interference signal (es) is input via a delta-modulator (A/D), in the form of the ΔM-signal (A) obtained in this way, into the compensation signal store (UR) which leads via a delta-modulator circuit (D/A) to the outgoing four-wire line arm (VE).
4. A digital telecommunications system as claimed in claim 2 or 3, characterised in that the compensation signal store (UR) is formed by a cyclic shift register.
5. A digital telecommunications system as claimed in one of claims 1 to 4, characterised in that in addition to the cyclic store (U/R) a static store (SS) is provided into which the compensation signal is likewise input from which, at the beginning of a new transmission process, it is reinput into the cyclic store (UR).
6. A digital telecommunications system as claimed in one of the claims 1 to 5, characterised in that in a hybrid circuit (G) which terminates a two-wire subscriber connection line (ZL) at the subscriber end, whenever the feed voltage is connected a first transmitted signal pulse (s) of this kind is produced, and the resultant interference signal (es) is input into the associated compensation signal store (UR) from which it is then repeatedly read out, as a compensation signal (k), in response to a transmitted signal pulse (s).
7. A digital telecommunications system as claimed in one of the claims 1 to 6, characterised in that in a hybrid circuit (G) which terminates at the subscriber end a two-wire subscriber connection line (ZL) which is terminated at the exchange end by a hybrid circuit, on the occasion of the first connection establishment initiated by the subscriber the interference signal (es) is input into the associated compensation signal store (UR) from which it is read out again, as compensation signal, during later connections which extend via the two-wire subscriber connection line (ZL).
8. A digital telecommunications system as claimed in one of the claims 1 to 7, characterised in that in a hybrid circuit (G) which terminates at the exchange end a two-wire subscriber connection line (ZL) which is terminated at the subscriber end by a hybrid circuit, on the occasion of the first connection establishment leading to the subscriber in question, the interference signal is input into the associated compensation signal store (UR) from which it is read out again, as compensation signal, during later connections which take place via the two-wire subscriber connection line (ZL).
9. A digital telecommunications system as claimed in one of the claims 1 to 8, characterised in that a plurality of such interference signals (es), which are each produced by a transmitted signal pulse, are input consecutively into a separate store (UR) from which they are read out again, at least during the following connection, in response to each further transmitted signal pulse (s), whilst forming mean values for the formation of the compensation signal.
EP81109138A 1981-04-28 1981-10-28 Digital telecommunication system Expired EP0063638B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81109138T ATE18482T1 (en) 1981-04-28 1981-10-28 DIGITAL TELECOMMUNICATION SYSTEM.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3116863 1981-04-28
DE3116863A DE3116863C2 (en) 1981-04-28 1981-04-28 Circuit arrangement for digital signal echo cancellation

Publications (3)

Publication Number Publication Date
EP0063638A2 EP0063638A2 (en) 1982-11-03
EP0063638A3 EP0063638A3 (en) 1983-10-12
EP0063638B1 true EP0063638B1 (en) 1986-03-05

Family

ID=6130999

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81109138A Expired EP0063638B1 (en) 1981-04-28 1981-10-28 Digital telecommunication system

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EP (1) EP0063638B1 (en)
JP (1) JPS57183137A (en)
AT (1) ATE18482T1 (en)
DE (1) DE3116863C2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3121545C2 (en) * 1981-05-29 1986-12-04 Siemens AG, 1000 Berlin und 8000 München Crosstalk and / or Echo cancellation circuit
GB2144950A (en) * 1983-08-10 1985-03-13 Philips Electronic Associated Data transmission system
CA1238381A (en) * 1985-03-14 1988-06-21 Ephraim Arnon Multi-stage echo canceller
JPH0666710B2 (en) * 1986-04-07 1994-08-24 日本電気株式会社 Eco-Cancell method
FR2612029B1 (en) * 1987-03-03 1989-05-12 Connan Jean Louis DEVICE FOR REALIZING THE "HANDSFREE" FUNCTION IN A TELEPHONE SET, COMBINING THE GAIN SWITCHING AND ECHO CANCELLATION FUNCTIONS

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128413A (en) * 1974-09-03 1976-03-10 Nippon Electric Co TEKIOGATAHANKYOSHOKYOSOCHI
US4024358A (en) * 1975-10-31 1977-05-17 Communications Satellite Corporation (Comsat) Adaptive echo canceller using differential pulse code modulation encoding
JPS5283112A (en) * 1975-12-30 1977-07-11 Fujitsu Ltd Two-ways amplifier
NO140648C (en) * 1977-10-24 1983-03-29 Elektrisk Bureau As DIRECTIVE CONNECTOR.
JPS5829023B2 (en) * 1978-07-10 1983-06-20 富士通株式会社 data communication equipment
JPS55123243A (en) * 1979-03-16 1980-09-22 Fujitsu Ltd Echo canceler
DE2920575C2 (en) * 1979-05-21 1981-09-17 Siemens AG, 1000 Berlin und 8000 München Digital telecommunications system with at least one four-wire line section
DE3116817A1 (en) * 1981-04-28 1982-11-11 Siemens AG, 1000 Berlin und 8000 München Digital telecommunications system

Also Published As

Publication number Publication date
DE3116863C2 (en) 1985-08-08
ATE18482T1 (en) 1986-03-15
JPS57183137A (en) 1982-11-11
EP0063638A3 (en) 1983-10-12
EP0063638A2 (en) 1982-11-03
DE3116863A1 (en) 1982-11-11

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