CH647366A5 - CODING DEVICE FOR BINARY DATA SIGNALS AND DECODING DEVICE FOR THESE DATA SIGNALS. - Google Patents

Description

The invention relates to a coding device for binary data signals and a decoding device for these data signals with an optimized data signal density, the binary data signals consisting of successive data elements (bits) of the same duration.

The invention has for its object to provide a device with which the data signal density of binary data e.g. can be optimized in the form of a pulse change code. The encoding and decoding should be possible with a minimal bandwidth, the encoded signal containing a synchronization signal which ensures the synchronization of the coding circuit with the decoding circuit.

This object is achieved according to the invention by a coding device with the characterizing features of claim 1 and by a decoding device with the characterizing features of claim 2.

Further embodiments of the invention are the subject of dependent claims.

The coded signal according to the invention has no ambiguity and contains positive synchronization information. The encoded signal is also a pulse signal,

where, however, the maximum distance between two signal jumps corresponds to the duration of two data elements. The location of the signal jumps in the coded signal depends in part on where the preceding signal jump is located with regard to the duration of a data element. A limited amount of defined information can be extracted from the coded signal, such as:

a) if the distance between two signal jumps is equal to the length of a data element,

that the second signal jump identifies a binary 1 of the original data or the original pulse change code;

b) if the distance between two signal jumps corresponds to the duration of two data elements, it follows that once in the original data sequence or the pulse change code, a series of identical binary states, e.g. binary 0 is present and that both signal jumps take place between data elements. In contrast, it is known in the prior art that the data jumps occur in the middle of the duration of data elements.

The advantages and features of the invention also result from the following description of an exemplary embodiment in conjunction with the claims and the drawing. Show it:

I shows a coding circuit in a simplified block diagram;

FIG. 2 shows the coding circuit according to FIG. 1 in a schematic circuit diagram;

3 shows a number of waveforms A to M, which characterize the signal sequences at different points of the circuits according to FIGS. 1 and 2;

Fig. 4 is a simplified block diagram of a decoding circuit;

FIG. 5 shows a schematic circuit diagram of the decoding circuit according to FIG. 4;

6 shows a number of waveforms A to J as they occur at different points in the decoding circuit according to FIGS. 4 and 5;

7 shows a number of waveforms A to I as they occur at different points in the decoding circuit according to FIGS. 4 and 5 and are used to explain the mode of operation of the zero detector;

8 shows a number of waveforms A to H to explain the mode of operation of the clock and phase generator according to FIGS. 4 and 5;

9 shows a number of waveforms A to J which are used to explain the mode of operation of the signal generator according to FIGS. 4 and 5.

3C shows a pulse code modulated waveform, the individual code characters directly adjoining one another. According to FIG. 3A, the waveform consists of individual data elements which are identified by the numbers 1 to 10. In the following, reference will be made to these data elements in the treatment of the different forms of vibration, the data elements in the decoding being shifted by the length of a data element compared to the data elements in the coding. The content of the individual data elements is indicated in FIGS. 3B and 6B with the binary numbers 1 and 0.

It is also possible to use a complementary nomenclature and accordingly to change the circuits described in such a way that the opposite signal levels are encoded or decoded in each case compared to those in the example described here. It is known to the person skilled in the art that the replacement of the signal level 0 by the signal level 1 does not constitute a significant circuit

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modification. For example, the control of the coding circuit via an inverting stage on the output side to the complement of the signal levels described for the example.

A binary 1 is described by a high signal level 15 and a binary 0 by a low signal level 16. It is characteristic of a pulse change code of a known type that the signal level is maintained if successively identical data levels are coded in succession. Accordingly, there is no change in the signal level for the two successively coded binary 1 and the three successively coded binary 0 in the waveforms shown in FIGS. 3C and 6C.

In the coding and decoding technology described below, certain circuits respond to the instantaneously changing polarity direction of the waveform. This direction of changing polarity is conventionally designated by a negative edge 17 according to FIGS. 3C and 6C, which is indicated by a corresponding downward-pointing arrow. The change in polarity in the opposite direction is identified by an arrow 18 pointing upward and denotes a positive edge. The negative edge is also referred to as the trailing edge and the positive edge.

The change from a high signal level 15 to a low signal level 16 is also referred to as a signal jump, it being possible in this case to speak of a negative signal jump and in the case of a transition from the low signal level 16 to the high signal level 15 the positive signal jump.

Such a signal jump occurs when e.g. in the area of the trailing edge 17 or the leading edge 18 adjoin two data elements with which different data signals are encoded. In the case of data signals coded in the same way, there is no such signal jump as can be seen from FIGS. 3C and 6C for data elements 5 and 6 and 7, 8 and 9. The time during which such a signal jump takes place is also referred to as the transition time.

The individual waveforms shown are synchronized with one another with respect to the temporal assignment of the transition times via clock signals, as are characterized by FIGS. 3D and 7D. All waveforms drawn to the clock signals begin with a positive signal jump for data element 1. The clock signal according to FIG. 7D has twice the clock frequency of the clock signal according to FIG. 3D. In FIG. 3D, a clock cycle corresponds to the length of a data element, whereas the clock cycle according to FIG. 7D is run through twice for a data element.

FIG. 3M shows the so-called Jordan-coded waveform of the pulse change code according to FIG. 3C. This Jordan-encoded waveform has no ambiguity and has the same spectral power density distribution as the aforementioned Miller code for a random data pattern.

Because of the operating methods for the coding circuit according to FIGS. 1 and 2, the Jordan code shown in FIG. 3M has several unique characteristics. The transition times for the positive and negative signal jump occur at an average time of the time period assigned to a data element, such as at the time marked 19 and 20 according to FIG. 3M. The mean time period assigned to a data element is very broad and is defined as that time which is different from the time assigned to the start or end of a data element. In the described embodiment, this time corresponds to the point in time in the middle of a data element. Furthermore, positive and negative signal jumps can also occur at the time assigned to the end of a data element, as indicated by reference numerals 21 and 22. Finally, the distance between two successive signal jumps can correspond to the length of time for the length of a data element corresponding to reference symbol 23 or the duration of VA data elements identified by reference symbol 24 and the time duration of 2 data elements identified by reference symbol 25.

The start and end of a data element in the pulse change code shown in FIGS. 3C and 6C occurs at the point in time which is also identified as the transition time between two data elements. Accordingly, the transition time at the end of one data element coincides with the transition time at the beginning of the next data element.

As indicated in FIG. 3A for data element 1, each data element can be divided into four equal parts.

For the explanation of the signal processing by the circuits according to the invention, it is important to describe the signal condition for different times of the individual data elements. In order to avoid confusion, the following two characteristic markings are used for the signal for all forms of vibration. The first label is the time at which the signal occurs and the second label is the direction of the signal jump. There is a negative signal jump, which is identified by the reference symbol 17 in FIG. 3C, and a positive signal jump, which is identified by the reference symbol 18 in FIG. 3C. The time period at which the signal occurs can be the mean time, identified by reference numerals 19 and 20, the start time or end time, identified by reference numerals 21 and 22, and the time after the first quarter, identified in FIG. 3F by reference numeral 26, and the time after the third quarter, identified by reference numeral 27 in FIG. 3F, may be the time period associated with a data element.

The distance between the signal jumps and the time of the transition time between the signal levels interact for the unique coding of the data of a pulse change code. A clear distinguishing feature of the Jordan code according to FIG. 3M relates to the distance between two transition times for the length of two data elements, as identified by reference number 25. Whenever this distance occurs in a Jordan code, both signal jumps are identified by the coding circuit as occurring at the time of the transition time. This feature is used to synchronize the encoding circuit with the incoming data stream.

1 shows a simplified block diagram for the coding circuit according to the invention. For the explanation of the mode of operation of the coding circuit, of which FIG. 2 is a schematic circuit diagram, reference is made to the waveforms according to FIG. 3, on the basis of which the signal processing is explained. 3C is applied to a NAND gate 30 via the input line 31. This NAND gate 30 is acted upon at its second input via a line 32 by a clock signal which comes from a clock generator 32a and corresponds to the waveform according to FIG. 3D. The clock 32a can be constructed in a conventional manner.

3C has a high signal level 15 for the data element corresponding to a binary 1 and a low signal level 16 for the data element corresponding to a binary 0. The clock signal according to

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3D begins with a first high voltage level 33, which is followed by a second low voltage level 34. The length of a full data element is identified by the length identified by reference numeral 35. It can be seen from this that a full period of the pulse-shaped clock signal is assigned to the time duration of a data element. The signal jump between the two voltage levels 33 and 34 takes place at the mean time of the time period assigned to the data element and is identified by the reference symbol 36.

The circuit according to FIGS. 1 and 2 further comprises a level detector 37, which is acted upon by the output signals of the NAND gate 30 via the line 38. A detector 39 for the positive signal jump responds to the clock signal applied via a line 40. Both the output signal of the level detector 37 and the output signal of the detector 39 for the positive signal jump are applied to an AND gate 41 via lines 42 and 44, respectively. The output signal of the AND gate 41 acts on a divider 46 via a line 48, the output signal of which is available at the output terminal 50.

The level detector 37 delivers an output signal whenever the pulse change code applied via line 31 according to FIG. 3C assumes the high signal level 15 or the low signal level 16. In the described embodiment, the level detector 37 identifies the low signal level of the pulse change code applied on the input side, which is assigned a binary 0.

For the preferred embodiment, the level detector generates an output pulse for each data level applied to a binary 1 corresponding to the input. This output pulse of the level detector is characterized in that it begins with a negative signal jump at the mean time of the time period corresponding to a data element. The pulse duration of the pulses generated by the level detector 37 depends on the input characteristic of the divider 46. In particular, the pulse duration of this output-side pulse only needs to be sufficient to control the divider 46. A sequence of such output pulses from the level detector 37 is shown in FIG. 3G for the alternating code, for example.

The detector 39 for the positive signal jump generates an output pulse for each positive signal jump 50 of the clock signal according to FIG. 3D. Thus, it applies to the coding circuit that the level detector 37 delivers output pulses, each of which represents the presence of a binary 1 in the pulse change code, whereas the detector 39 delivers an output pulse for each positive signal jump of the clock signal.

The AND gate 41 connects these two pulse sequences applied via the lines 42 and 44 and supplies a pulse on the output side which contains all the necessary information for the reconstruction of the encoded pulse change code. The pulse available at the output of the AND gate 41 is shown in FIG. 3K and is suitable for recording and for transmission. This pulse contains redundant information and offers the possibility of dividing the frequency e.g. to decrease by a factor of 4.

The more detailed circuit diagram of the coding circuit is shown in FIG. 2. The pulse change code is applied via the input line 31 to the NAND gate 30, on which the clock signal from the clock generator 32a is also connected via the line 32. The output signal supplied by the NAND gate 30 is applied to a sequence of inverting stages 62, 64, 66, which form part of the level detector 37. This level detector also includes a NAND gate 68 which is connected to the output of NAND gate 30 via line 32

on the one hand directly and on the other hand via the reversal stages.

The two input signals for NAND gate 68 are shown in Figures 3E and 3F. Accordingly, the output signal of the NAND gate 30 corresponds to a pulse, the negative signal jump of which corresponds to the positive signal jump 50 of the clock pulse and which has a pulse duration of half the duration of a data element for each pulse, with the negative signal jump 36 of the clock pulse assigned in each case ends. 3F that the input signal for NAND gate 68 via line 70 has an opposite polarity and is delayed compared to the pulse sequence according to FIG. 3E. The delay corresponds to the distance between the dashed lines 74 and 76 and is caused by the reversing stages 62, 64 and 66. Schottky circuits are used for these inversion stages, so that three stages are necessary since each individual stage has a delay of approximately 5 ns. If TTL circuits were used, only one reversal stage would be necessary, since delays of 15 to 20 ns are possible with such TTL circuits. The function of the inverting stages is merely to reverse the output signal of the NAND gate 30 and to delay it sufficiently long that it is suitable for driving the divider 46. The normal function of a NAND gate is to deliver a negative pulse when two pulses applied to its inputs have a positive signal level. This is only the case during the period during which the input signal is delayed by the inverting stages 62, 64 and 66, as can be seen from FIG. 3G in connection with 3E and F. The negative pulse according to FIG. 3 G has a pulse duration which corresponds to the delay time due to the reversing stages, the leading edge coinciding with the negative signal jump 36 of the clock pulse. This pulse shown in FIG. 3G has the characteristic, already mentioned features of the present pulse code modulation, according to which each individual pulse begins at the mean time of the time period assigned to a data element with a binary 1 of the pulse change code.

The detector 39 for the positive signal jump likewise comprises a multiplicity of reversing stages 80, 82 and 84, which are connected in series and control the one input of a NAND gate 86 via the line 88. The second input of this NAND gate is acted upon directly via line 90 by the clock signal, which is available via line 40. The clock signal transmitted via the reversing stages 80, 82 and 84 is delayed and vice versa, so that it corresponds to the signal sequence shown in FIG. 3H. The output signal of NAND gate 86 is a negative pulse whenever two positive, i.e. a binary 1 assigned signal levels. The resulting output signal under these circumstances is shown in Fig. 31. 31 begins with a positive signal jump of the clock signal according to FIG. 3D.

The AND gate 41 is formed from a NAND gate 96 and an inverter 98. At the inputs of NAND gate 96, the output signal of NAND gate 68 is applied on the one hand via line 42 and, on the other hand, the output signal of NAND gate 86 is applied via line 44. With the help of the NAND gate 96, a negative output signal is generated whenever the NAND gate 96 has two positive, i.e. binary 1 assigned signal levels is applied simultaneously. If one of the input signals corresponds to the status of a binary 0, a signal corresponding to the status of a binary 1 is generated on the output side. The pulse train of the output signal from

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NAND gate 96 is shown in Figure 3J. This signal is transmitted via the inverter 98, so that it is available at the output of the AND gate 41 in the signal sequence shown in FIG. 3K.

The divider 46 consists of two series-connected JK flip-flops 100 and 102. The flip-flop 100 is triggered by a negative input pulse of sufficient pulse duration and switched to one of its stable states. As already mentioned, the reversing stages 80 to 84 and 62 to 66 serve the purpose of creating such a trigger pulse with a sufficient pulse length for the flip-flop 100.

Each of these flip-flops has two stable states, which can be seen in the corresponding output signals. One output signal has a high signal level 104 and the other output signal has a low signal level 106 according to FIG. 3L. The two signals are available at the non-inverting output Q and at the inverting output Q.

The output signal of flip-flop 100 is transmitted via line 108 from output Q to the input of second flip-flop 102. The output Q of the second flip-flop supplies the output signal shown in FIG. 3M. This output signal is available at terminal 50 for further processing. 4 shows the simplified block diagram of the decoding circuit according to the invention. A zero decoder 200 is acted upon by a phase-locked clock generator 201 via line 202 with a first input signal. This clock generator can be of conventional construction. The clock signal from the clock generator 201 has twice the frequency of the clock signal shown in FIG. 3D and corresponds to the signal according to FIG. 7D. This clock signal on the input side is synchronized with the received data signals in a conventional manner, it being possible to use a synchronization circuit with a phase-locked bit loop.

A detector 204 for determining the positive and negative signal jump is acted upon by the input terminal 205 for the data signals via the line 206. On the output side, this detector 204 supplies a pulse for each signal jump of the received data signals, which pulse is supplied to an inverter 208, among other things. This signal, which is output on the output side by the reversing stage 208, serves to reset the zero detector 200 and is supplied to it via the line 210. With the aid of the zero detector 200, two successive data elements in the input signal are to be determined which identify a binary 0. Such a sequence of two binary 0s is shown in FIG. 6D with the route identified by reference numeral 25. The mode of operation of the zero detector 200 is explained in more detail below in connection with FIG. 5.

The output of detector 204 is also applied to an AND gate 214 via line 216 and to an AND gate 218 via line 220. Finally, the output signal of the detector 204 is also applied to a univibrator circuit 222 via the line 224.

The output signal of the zero detector 200 is transmitted via line 228 to a clock and phase generator 226, which is acted upon directly at a second input via line 230 by the output signal of the phase-locked clock generator 202. This clock and phase generator 226 provides several output signals. The first output signal is fed via line 232 to the second input of AND gate 214. The second output signal is transmitted to the first flip-flop 234 via line 236. The third output signal of this clock and phase generator 226 acts via a line 240 on a second flip-flop 238. Finally, the synchronous clock signal is also available at terminal 242 via line 244 as an output signal. The flip-flops are JK flip-flops.

As already mentioned, the code format of the signal coded by the coding circuit according to the invention has, as a characteristic feature, a signal jump in the new code format which occurs at the middle time of the period of data elements which are assigned to certain selected binary 1 of the original pulse change code. A second characteristic feature of the new code format is formed by signal jumps occurring in pairs, which identify further binary 1 of the original pulse change code. The distance between a pair of pulses is equal to the length of time for a data element.

Since these are the characteristics of a recorded signal, circuit devices are required in the decoding circuit with which these characteristic features can be detected and ascertained. The AND gate 214 serves the purpose of selecting out all signal transitions which occur at the middle time of the duration of data elements. This is achieved by the corresponding logical processing of the signals applied on the input side via lines 216 and 232. The signal supplied via line 216 represents a sequence of pulses which are assigned to both the positive signal step 19 and the negative signal step 22 in the recorded waveform. As can be seen in FIG. 6F, the pulses can occur at the mean time of the duration of a data element, as indicated by reference numeral 246, or at the beginning or at the end of such a duration, as indicated by pulses 248 and 250. These jumps in signal are identified by AND gate 214 if they occur at the mean time of the time period assigned to a data element.

The second characteristic feature of the recorded signal occurs, as mentioned, when the distance between two signal jumps is equal to the duration of a data element, in which case one or both signal jumps represent a binary 1. It is the job of the univibrator circuit 222 to perform this function together with the AND gate 218. The output of univibrator circuit 222 is applied to the second input of AND gate 218 via line 252. The output signal of the detector 204 is connected to the first input via the line 220.

If a pair of pulses is provided by the detector 204, which has a pulse interval equal to the duration of a data element, the first pulse acts as a trigger pulse for the second. The univibrator circuit 222 increases the first pulse and provides a trigger pulse to the AND gate 218 for the second pulse.

FIG. 5 shows a schematic circuit diagram of the decoder circuit according to FIG. 4, the waveforms occurring in the circuit at individual switching points being shown in FIG. 6, which in line A represents the time period assigned to the individual data elements. Line B shows the binary content of the data elements whose binary waveform is shown in line C as a pulse change code.

This pulse change code shown in Fig. 6C describes the code format of the information to be recorded. FIG. 6D shows the code format in the form of the so-called Jordan code, in which the pulse change code is available for recording or transmission after coding in the coding circuit according to FIGS. 1 and 2. This recorded or transmitted signal is applied in the Jordan code to the input terminal 205 of the decoding circuit according to FIGS. 4 and 5 and acts on the detector 204 via the line 206. This detector 204 comprises a plurality of reversing stages 300, 302, 304

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and 306, which are connected in series. With the aid of these reversal stages, a sufficiently long delay of the received code format is to be effected so that both the positive and the negative signal jumps can be determined. The code signal shown in FIG. 6D acts on the one hand via line 308 on the reversing stage 300 and on the other hand via line 312 directly on an exclusive OR gate 310. After passing through the reversing stages, the output of the last reversing stage 306 is on line 311 6E available.

The exclusive OR gate 310 supplies a signal on the output side which corresponds to the waveform according to FIG. 6F. Due to the conventional mode of operation of an exclusive OR gate, a positive pulse is available on the output side whenever the two input signals have an opposite signal level. If, on the other hand, the two input signals are at the same signal level, a negative pulse is generated on the output side.

The output signal of the exclusive OR gate 310 is applied via line 216 to the AND gate 214, to which the clock signal from the clock and phase generator 226 is applied at its second input via line 232.

This clock and phase generator 226 consists of a first flip-flop 314 and a second flip-flop 316. The phase-locked clock signal is applied via line 230 to input C of first flip-flop 314 and at the same time to input C of second flip-flop 316 via an inverter 320. The flip-flop 314 detects the trailing edge of a pulse signal and changes its stable state whenever a negative pulse edge at input C is active. The flip-flop 316 also acts in a corresponding manner, but due to the inversion of the applied signals, it now responds to the leading edge of the applied clock pulses. The mode of operation of this generator is explained in more detail below with reference to FIG. 8.

The clock signal shown in FIG. 6G is available at the output Q of the flip-flop 314, which acts on the AND gate 214 via the line 232. The waveform shown in FIG. 6G is identical to the waveform shown in FIG. 8D. The signal according to FIG. 6H is available at the output of the AND gate 214, which has positive pulses whenever two binary 1s are active on the input side of the AND gate 214.

The signal of FIG. 6G makes the AND gate 214 effective during the second and third part of the period of a data element. As a result, AND gate 214 transmits those pulses from detector 204 that occur during that time. Accordingly, a pulse is available at the output signal of the AND gate 214, which is used as a reset pulse for the flip-flop 234.

The output side pulses from the exclusive OR gate 310 are also applied to the univibrator circuit 222 and via line 220 to the one input of an AND gate 218. The univibrator circuit 222 serves the purpose of stretching the applied pulses with respect to the pulse duration and generating an output signal which is effective on the one hand longer than the time duration of a data element and on the other hand shorter than the time duration of 1 Vi data elements. The waveform of this output signal of the univibrator circuit is shown in Fig. 61, whereas the waveform of the output signal of the AND gate 218 is shown in Fig. 6J. Accordingly, a positive output signal is produced at the output of the AND gate 218 whenever a signal with a high signal level is active from the univibrator circuit 222 and from the detector 204.

6F and 61 show the input signal for the univibrator circuit 222 on the one hand and the output signal on the other hand. The output signal only changes to the second state or the state that triggers an effect after the input signal is no longer effective. This delay prevents the univibrator circuit 222 from turning the AND gate 218 on for each pulse from detector 204. The output signal of the univibrator circuit remains at the trigger level for a time that is longer than the duration of a data element. The univibrator circuit 222 can thus transmit the pulses shown in FIG. 6F via the AND gate 218, which follow a preceding pulse at a distance from the duration of a data element.

Each individual binary 1 in the original pulse change code is encoded in one of two ways. In one possibility, a signal jump is generated in the middle of the time period assigned to a data element, whereas in the other case two signal jumps are generated which are separated from one another by the time duration of a data element. Correspondingly, during the decoding, those signal jumps which occur in the middle of the time period of a data element are identified by the AND gate 214 and those signal jumps which are separated from one another by the time duration of a data element in the decoded pulse train are determined by the AND gate 218. After this information has been abstracted from the incoming signal coded in the Jordan code, the remaining circuit parts serve to convert the pulses into the format of the pulse change code.

FIG. 7 shows a number of waveforms as they are generated by the zero detector 200, a synchronization pulse always occurring when:

when a series of three binary 0s occurs in the original pulse change code. Although it is also possible

Generating a corresponding synchronization pulse if two binary 0s occur in succession in the original pulse change code will not be dealt with in any further detail since this is a condition which generates a synchronization pulse depending on the state of a plurality of data elements which precede two binary pulses. Since this is a variable, the Jordan code depends on three binary 0s in a sequence to generate its synchronization pulse. If three binary 0s occur in a sequence, it is known that a synchronization pulse with a positive signal jump is generated which is exactly at the beginning of the period of a data element. This positive signal jump is used to trigger flip-flops 314 and 316 in clock and phase generator 226. In the event that these flip-flops drift out of synchronization with respect to the incoming pulse change code,

the synchronization is immediately restored by the synchronization pulse. JK flip-flops are used as flip-flops.

The original pulse change code is shown in Fig. 7B, while its coding in the Jordan code is shown in Fig. 7C. The binary equivalents are given in Fig. 7A. 5 is shown in FIG. 7D, whereas FIG. 7E shows the output signal at the inverting stage 208. This signal is 180 ° out of phase with the signal according to FIG. 6F.

The zero detector 200 comprises a multiplicity of flip-flops 320, 322 and 324, which each work as a divider by a factor of 2 and respond to negative signal jumps in the input signal applied to the connection C or to a pulse applied to the reset input R. The output signal at output Q of flip-flop 320 is shown in Fig. 7F. A negative signal jump applied to input C causes the flip-flop to be switched over.

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The flip-flop is reset by a negative signal jump applied to the reset input R, so that a signal with a low signal level is available at the output Q.

The Q output of the individual flip-flops is the non-inverting output, whereas the Q output is the inverting output.

As already mentioned, the flip-flops act as a divider by a factor of 2, so that a signal appears at the output Q of the flip-flop 320 whenever the input C has been subjected to an input signal twice. In addition, flip-flop 320 is reset when a pulse is effective at reset input R. This pulse according to FIG. 7E switches the individual flip-flops into the stable state in which a low signal level is effective at the output Q. This is described in detail in connection with the explanation of the waveform according to FIG. 7F. The negative signal jumps of the waveform according to FIG. 7D and FIG. 7E interact in such a way that the waveform according to FIG. 7F arises.

The negative signal jump of the pulse, which occurs at the output of the inverter 208 during the mean time of the time period assigned to a data element, switches the flip-flop 320 into a state in which a low signal level is effective at the output Q. The negative signal jump of the signal, which occurs after% of the duration of the first data element in the signal according to FIG. 7D, switches the output Q of the flip-flop 320 to the high signal level. The negative signal jump, which occurs after the first quarter of the period in the second data element according to FIG. 7D, switches the flip-flop back down to the lower signal level on the output side. The negative signal jump, which occurs after Va of the duration of the second data element according to FIG. 7D, switches the output Q of the flip-flop 320 to the high signal level. The negative signal jump of the reset pulse of the reversing stage 208, which occurs at the beginning of the period of the third data element according to FIG. 7E, switches the output Q of the flip-flop 320 to the low signal level. The negative signal jump after the first quarter of the duration of the third data element according to FIG. 7D switches the output Q of the flip-flop 320 to the high signal level. The negative signal jump, which occurs after% of the duration of the third data element according to FIG. 7D, switches the output Q of the flip-flop 320 to the lower signal level. The negative signal jump at the beginning of the period of the fourth data element according to FIG. 7E does not change the output signal of the flip-flop 320, since its output Q is already at a low signal level and a negative reset signal always shifts the flip-flop in the state in which the output Q a low signal level is effective. The remaining waveform according to FIG. 7F is generated in a corresponding manner. In summary, it can be said that the negative signal jumps according to FIG. 7D switch the flip-flop 320 from one to the other stable state, while the negative signal jumps of the pulses applied from the reversing stage 208 set the flip-flop 320 such that a low signal level at the output Q is effective.

The waveform resulting at output Q of flip-flop 322 is shown in Fig. 7G. The output signal at the output Q of this flip-flop 322 arises in the same way as was explained in connection with the flip-flop 320.

The input signal is applied to flip-flop 322 via input C. This input signal corresponds to the output signal according to FIG. 6F at the output Q of the flip-flop 320. As a second input signal, the flip-flop 322 is supplied with a reset pulse at the reset input R, which comes from the inverting stage 208 and has the waveform according to FIG. 7E. The flip-flop 322 responds to the negative signal jump of this reset pulse and resets the flip-flop 322 to the stable state in which a low signal level is available at the Q output. The flip-flop 322 is also switched over via input C likewise only in the event of negative signal jumps. Accordingly, the flip-flop 322 is switched over by the signals applied to its input in accordance with FIGS. 7E and 7F. The negative signal jumps coming from the reversing stage 208, which occur in the middle of the period of the first data element, switch the flip-flop 322 to the low output level, whereas the negative signal jumps, which occur after the first quarter of the period of the second data element according to FIG. 7F, cause flip-flop 322 to switch over such that a high signal level is present at output Q.

Both the negative signal jumps of the pulses from the inverting stage 208 and the signals from the output Q of the flip-flop 320, which occur at the beginning of the period of the third data element, cause the flip-flop 322 to switch to the low signal level at the output Q. The negative from the output Q of the flip-flop 320 from the applied signal jump after% of the duration of the third data element switches the flip-flop 320 at the Q output to the high signal level. The negative signal jump of the pulse applied from the inverting stage 208 at the time of the beginning of the period of the fourth data element resets the output Q of the flip-flop 322 to the low signal level. The remaining parts of the waveform according to FIG. 7G are also generated in a corresponding manner.

The negative signal jumps of the reset pulses according to FIG. 7E set the flip-flop 324 to the signal state in which a low signal level is present at the output Q. 7G can change the stable state of the flip-flop 324. It can be seen from FIGS. 7E and G that with each negative signal jump of the waveform according to FIG. 7G, which wants to switch over the flip-flop 324, occurs simultaneously with a negative signal jump of the reset signal from the reversing stage 208, which turns the flip-flop 324 into a state switches in which a low signal level is present at output Q. The only exception to this arises in the event of a negative signal jump at the output Q of the flip-flop 322 after the third quarter of the period of the ninth data element, which namely switches the flip-flop 324 into a state in which a high signal level is effective at the output Q. This change is followed by a negative signal jump from the inverting stage 208 at the beginning of the period of the tenth data element, which in turn resets the flip-flop 324, so that a low signal level is available at the output Q. The waveform shown in Fig. 7H shows a pulse at which the negative signal jump occurs at the beginning of the period of the tenth data element. This point in time is identical to the point in time at which the three consecutive binary 0s according to FIGS. 7A and B have ended.

It is the task of the zero detector 200 to generate a synchronization pulse at the Q output of the flip-flop 324 whenever three binary 0 occur in the original pulse change code. 7H is shown in FIG. 71. This complementary waveform is used to drive the flip-flop 314 because it responds to the positive signal jump. 71 occurs exactly at the time at the end of one data element and at the start of the other data element and causes the synchronization

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tion of the internal clock and phase generator 226 with the received data signal, if necessary, which represents the pulse change code encoded in the coding circuit.

FIG. 8 shows one of the waveforms on the basis of which the mode of operation of the clock and phase generator 226 5 is explained. This clock and phase generator consists of two flip-flops 314 and 316, which on the trailing edge, i.e. address the negative signal jump of the pulse applied to the respective input D. The flip-flop 314 is acted upon directly by the clock frequency and the flip-flop 316 via an inverse stage 320. Therefore, the output signal at output Q of flip-flop 316 is 90 ° out of phase with the signal at output Q of flip-flop 314. The inverted output signals are available at outputs Q. 15

FIG. 8A shows the pulse change code which is used as the basis for the coding according to the invention. 8B shows the pulse change code in the Jordan code. 8C shows the clock pulse that has twice the frequency of the applied data. The waveforms in Fig. 8D and. E denote the change in the output signals of the flip-flop 316, which result from the negative signal jumps of the data clock on the input side. 8F and G show the state changes of the flip-flop 316 which occur simultaneously with the applied 25 positive signal jump of the data clock. Since the data clock is applied to the flip-flop 316 via the reversing stage 320, there is a shift by 90 °.

The waveform according to FIG. 8H is identical to the waveform shown in FIG. 71. It follows from this that the synchronizing reset pulse occurs at the beginning of the time period of the tenth data element. In the event that the waveform occurring on the flip-flops 314 and 316 is no longer synchronized with the incoming pulse change code, the reset pulse would synchronize the generation of the output signals according to FIGS. 8D, E, F and G again with the incoming pulse change code. The waveform according to FIG. 8F is available at the output Q of the flip-flop 316 and is applied via the line 244 to the terminal 242 as a synchronization clock.

FIG. 9 shows a number of waveforms which occur when a format in the Jordan code is converted into the pulse change code. Figure 9A shows the binary values of the original pulse change code shown in Figure 9B. In contrast, Fig. 9C shows the original pulse change code reproduced by coding in the Jordan code, as used for recording the digital data. FIG. 9D repeats the waveform as it is available at the output Q of the flip-flop 314 and is already shown in FIG. 8E. 9E shows the output signal at AND gate 214, which corresponds to the output signal according to FIG. 6H.

The signal at the output Q of the flip-flop 234 is shown in FIG. 9F and arises as a function of two input signals 55 on this flip-flop, which correspond to the waveforms according to FIGS. 9D and E.

The flip-flop 234 operates as follows. A negative signal jump applied to input C only changes the operating state of the flip-flop if there is a change at output Q from a low signal state to a high signal state. A positive signal jump applied to input C of flip-flop 234 does not switch the flip-flop. If there is a high signal state at output Q of flip-flop 234, a negative signal jump acting at input C has no influence on the flip-flop. The positive edge of the reset pulse applied to input R resets the flip-flop so that at its out 35

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a low output signal is available.

FIG. 9G shows the signal at the output Q of the flip-flop 316, which corresponds to the waveform according to FIG. 8G. The waveform at the output of the AND gate 218 shown in FIG. 9H corresponds to the waveform as shown in FIG. 6J '.

The signal at output Q of flip-flop 238 is shown in FIG. 91 and is the result of the signals processed for decoding in flip-flop 238. The flip-flop 238 decodes the signals applied to its input in accordance with FIG. 9F in cooperation with the clock signal in accordance with FIG. 9G and the reset signal in accordance with FIG. 9H. In this way, the flip-flop 238 effects a second step in the decoding in order to derive a binary 1 from the signal obtained from the output Q of the flip-flop 234 whenever the original pulse change code has contained a binary 1, as is indicated by a pair of pulses which the individual pulses are separated from each other by the duration of a data element in the encoded pulse train.

For the detailed description below, it is assumed that the signal available at output Q of flip-flop 314 is applied to input C of flip-flop 234 according to FIG. 9D. Depending on the leading edge of the pulse applied by AND gate 214, flip-flop 234 is switched to its first stable state, with a low signal level being present at output Q. At the time of the first quarter during the period of the second data element, the negative signal jump from the output Q of the flip-flop 314 acts on the input C of the flip-flop 234 and switches this flip-flop so that a high signal level is output at its output Q. The flip-flop 234 is now in a stable state, in which further negative signal jumps from the output Q of the flip-flop 314, which occur at the time of the first quarter during the period of the third data element,

do not trigger a switchover. The flip-flop 234 also does not change its switching state as a function of further negative signal jumps which occur from the output Q of the flip-flop 314 at the time of the first quarter of the time period of both the fourth and fifth data elements.

The positive signal jump according to FIG. 9E occurs at the middle time of the time period assigned to the fifth data element, switches the flip-flop 234 into the other stable state, so that a low signal level is now available at the output Q. The negative signal jump, which occurs at the time of the first quarter during the period of the sixth data element, resets the flip-flop, so that a high signal level according to FIG. 9F is again present at the output. The positive signal jump of the reset pulse, which occurs at the middle time of the time period assigned to the sixth data element, switches the flip-flop 234 again, so that the low signal level shown in FIG. 9F is present at its output.

The next negative signal jump at the output Q of the flip-flop 314 occurs at the first quarter of the duration of the seventh data element, with the result that the flip-flop 234 is again switched to a high signal level on the output side. All subsequent negative signal jumps at the output Q of the flip-flop 314 have no influence on the decoding flip-flop 234.

The signal according to FIG. 9F is the result of the first decoding step, the signal applied to the flip-flop 234 initially being processed by vCurde according to FIG. 9E. The pulses contained in this signal correspond to those pulses which, in the original coding, characterize the mean time of the duration of a data element which represents a binary 1 in the pulse change code

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sent. Accordingly, the vibration form according to Fgi. 9F shows a partially encoded signal, the information content of which represents the two 1's, which were encoded by the use of a pulse at the mean time of the duration of the corresponding data element.

The second decoding step is carried out with the aid of the flip-flop 238, which is subjected to several waveforms. The signal from the output Q of the flip-flop 234 according to FIG. 9F is applied to the input J of this flip-flop. The signal from the output Q of the flip-flop 316 is applied to the input C, as shown in FIG. 9G, and finally the input R is driven with a signal as shown in FIG. 9H from the AND gate 218.

The mode of operation of the flip-flop 238 used for the second decoding step is slightly different from the mode of operation of the flip-flop 234 used for the first decoding step. The signal according to FIG. 9F is shifted into the second flip-flop 238 in accordance with the control by the pulses contained in the signals according to FIGS. 9G and H. The negative pulse jumps of the waveform according to FIG. 9G control the flip-flop 238, the reset pulses according to FIG. 9H reset the flip-flop to the switching state in which a low signal level is available at the output Q. The negative signal jump of the clock pulse according to FIG. 9G at the beginning of the period of the second data element has the effect that the low signal level acting at the input J at the same time brings the flip-flop 238 into the switching state in which a low signal level according to FIG. 91 is present. With the next negative signal jump of the clock signal according to FIG. 9G, which occurs at the beginning of the period of the third data element, the high signal level effective at input J according to FIG. 9F is fed into flip-flop 238 and this at output Q to the high signal level according to FIG 91 raised. The positive signal jump of the reset pulse from the AND gate 218, which occurs at the beginning of the period of the fourth data element, switches the flip-flop 238 back, so that a low signal level is effective at its output Q. The negative signal jump at the output Q of the flip-flop 316 causes the high signal level according to FIG. 9F to be fed into the flip-flop 238 via the input J, so that its output Q is raised to a high signal level.

The negative signal jump of the clock signal from flip-flop 316 at the beginning of the period of the sixth data element has the effect that the low signal level according to FIG. 9F at output Q of flip-flop 234 via input J into flip10

flop 238 is shifted so that it assumes a low signal level at output Q. The positive signal jump of the reset pulse, which occurs at the middle time of the time period assigned to the sixth data element according to FIG. 9H 5, has no influence on the flip-flop 238, since its output Q is already at a low signal level and the reset pulse only switches over to the output side low signal level could cause. The simultaneous occurrence of a pulse for the waveform 10 according to FIGS. 9E and H represents redundancy. However, this redundancy does not cause any ambiguity when decoding the Jordan code. For this reason, it is not necessary to suppress one of the two pulses by an additional circuit.

The negative signal jump of the clock pulse according to FIG. 9G at the beginning of the period of the seventh data element causes the transmission of the low signal level from the output Q of the flip-flop 234 via the input J to the flip-flop 238, so that a 20 low signal level is also present at the output Q of this flip-flop is present. The negative signal jump of the clock pulse according to FIG. 9G at the beginning of the period of the eighth data element transfers the high signal level effective at input I of flip-flop 238 according to FIG. 9F to output Q of flip-flop 238, which assumes this signal level 25. The negative signal jump, the clock pulses at the beginning of the period of the ninth and tenth data elements does not change the signal level at the output Q of the flip-flop 238. In both cases, this maintains the high signal level, which corresponds to the waveforms according to FIGS. 9F and I 30. The positive signal jump of the reset pulse, as occurs at the beginning of the period of the eleventh data element, resets the flip-flop 238, so that its output Q again assumes the low signal level.

The inverted output signal occurs at the output Q of the flip-flop 238, the waveform of which is shown in FIG. 9J and corresponds to the original waveform of the pulse change code according to FIG. 9B. Compared to the original waveform of the pulse change code, the same waveform obtained after decoding is delayed by the duration of a data element. It follows from the description that the waveform received in the Jordan code can be decoded with the aid of the circuit according to FIGS. 4 and 5, and that the waveform of the original 45 pulse change code is obtained again as a decoded signal. This coded signal is available at terminal 370 assigned to output Q.

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Claims (11)

647 366 PATENT CLAIMS 1. Device for coding binary data signals for transmission and / or recording with an optimized data signal density, the binary data signals consisting of successive data elements of the same duration, characterized by the following switching elements: a clock generator (32a) which supplies a clock signal (FIG. 3D) in which a signal period (35) corresponds to the duration of a data element and furthermore the positive signal jump occurs synchronously with the time of the transition from one data element to another, - A first coding stage (30,37), which by linking the clock signal (Fig. 3D) with the binary data signals (Fig. 3C) provides a first pulse train (Fig. 3G), in each of which a pulse to all data elements of a particular one the same signal levels are assigned between their leading and trailing edges, a second coding stage (39) which derives a second pulse sequence (FIG. 3J) from the clock signal (FIG. 3D), in which a pulse is assigned to each positive signal jump of the clock signal, - A logic stage (41), which links the first and second pulse train (Fig. 3G and 3J) and transmits to a divider stage (46), as well - A divider stage, which delivers the coded data signal (FIG. 3M) after division, in which signal jumps occur at the time of the transition as well as between the times of the transition of successive data elements, which have a maximum distance of the duration of two data elements. 2. Device for decoding the data signals coded with a device according to claim 1, in which signal jumps occur at the time of the transition as well as between the times of the transition of successive data elements, which have a maximum distance between the duration of two data elements, characterized by the following switching elements: a clock and phase generator (226) which supplies a large number of clock signals (FIGS. 8C-H), a detector (204) which supplies a first pulse train signal (FIG. 6F) for each signal jump of the coded signal (FIG. 3M), - A first decoding stage (214) which responds to one of the clock signals (Fig. 6G) of the clock and phase generator (226) and to the output signal (Fig. 6F) of the detector (204) and a second pulse train signal (Fig. 6H) provides which determines the signal jumps in the coded signal (FIG. 6D) which are assigned to the area between the leading and trailing edges of the data elements with coordinated identical signal levels of the binary data signal (FIG. 6C), - A second decoding stage (218, 222) which responds to the output signal (Fig. 6F) of the detector (204) and provides a third pulse train signal (Fig. 6J) which determines the signal jumps in the coded signal (Fig. 6D) which are each assigned to the point in time of the transition of a data element which is distant from the point in time of the transition of the preceding data element by the duration of a data element, and - A signal generator (238, 234) which links the second pulse train signal (Fig. 6H) of the first decoding stage (214) and the third pulse train signal (Fig. 6J) of the second decoding stage C218, 222) and as a function of clock signals from the clock and phase generator (226) provides the original binary data signal (Fig. 6D). 3. Device according to claim 1, characterized in that the first coding stage (30,37) comprises: a first NAND gate (30), which responds to the binary signals (FIG. 2C) and to the clock signal (FIG. 3 D), and supplies a sequence of pulses (FIG. 3E), the negative signal jumps of which are each assigned to a binary 1 of the binary data, - Inversion stages (62, 64, 66) which respond to the pulses from the first NAND gate (30) and deliver an output signal (FIG. 3F) which is offset in time from the output signal of the first NAND gate (30), a second NAND gate (68) which responds both to the output signal (FIG. 3E) of the first NAND gate and to the output signal of the reversing stages (62, 64, 66) and supplies negative pulses (FIG. 3G), which occur at the mean time of the period of a data element characterizing a binary 1. 4. Device according to claim 1, characterized in that the second coding stage (39) comprises: Inverter stages (80, 82, 84) which respond to the clock signal (FIG. 3D) and on the output side supply a clock signal delayed with respect to the clock signal (FIG. 3H), - A NAND gate 86 which is responsive to the clock signal (Fig. 3D) and the delayed and inverted clock signal (Fig. 3H) and negative pulses. (Fig. 31) provides which occur at the start of each data element when the clock signal is positive. 5. Device according to claim 1, characterized in that the linkage stage (41, 46) comprises: - An AND gate (96, 98), which delivers negative pulses (Fig. 3K) on the one hand at the mean time duration of each data element corresponding to a binary 1 and on the other hand at the start of each data element at the time of the positive signal jump of the clock signal (Fig. 3G + 1); - A divider (46) which responds to the output signal (Fig. 3K) of the AND gate (96.98) and divides this in a ratio of 1: 4. 6. Device according to claim 2, characterized in that the clock and phase generator (226) comprises: first devices for generating a first clock signal (FIG. 8C) with a double period per data element, with a positive signal jump occurring at the beginning of each data element, - Second devices for generating a clock signal (FIG. 8E) with one period per data element, with no signal jump occurring at the beginning of a data element, but rather at a point in time during the period of the data element; - Third devices for generating a clock signal (Fig. 8G) with one period per data element, the negative signal jump occurring at an average time of the time period assigned to each individual data element. 7. Device according to claim 2, characterized in that the detector (204) comprises delay devices (300 to 306) which delay the received coded signal to the one input of an exclusive OR gate (310), which at the other input of the received coded signal is applied directly, and that the exclusive OR gate delivers positive pulses on the output side (FIG. 6F) if signal jumps occur in the received coded signal. 8. Device according to claim 2, characterized in that the second decoding stage (218, 222) comprises a univibrator (222) which is acted upon by the output signal (Fig. 6F) of the detector (204) and a trigger signal to the one input of an AND Applies gate (218), which is supplied with the output signal (Fig. 6F) of the detector (204) at its other input and emits a pulse signal (Fig. 61) on the output side, in which every second pulse of a pulse pair separated by the duration of a data element a positive pulse is associated with the pulse train provided by the detector (204). 2nd 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 3rd 647 366 9. Device according to claim 2, characterized in that the first decoding stage (214) consists of an AND gate, which is connected with its one input to the detector (204) and from the output signal (Fig.j 6F) of the detector ( 204), it is applied that a second clock signal (FIG. 8D) is present at the second input of the AND gate, and that the second positive pulse sequence signal (FIG. 6H) is available at the output of the AND gate, the individual positive ones Pulses are assigned an average time during the period of a data element, which is identified by a binary 1. 10. The device according to claim 2, characterized in that the signal generator (234, 238) comprises a first JK flip-flop (234) and a second JK flip-flop (238), that the first JK flip-flop (234) at input C with the second Clock signal (Fig. 8D) and at the reset input R with the second pulse sequence signal (Fig. 6H) from the first decoding stage (214) that the second JK flip-flop (238) at its input C with a third clock signal (Fig. 8G ) and at its reset input R with the pulse sequence signal (Fig. 61) from the second decoding stage (218,222), and that the output Q of the first JK flip-flop with the input J of the second JK flip-flop and the output Q of the first JK flip-flop is connected to the input K of the second JK flip-flop. 11. Device according to one of claims 2 or 6 to 10 with a synchronization device to keep the clock of the decoding device in synchronism with the clock of the coding device, characterized in that the synchronization device (Fig. 4, Fig. 5) has a phase-locked clock generator ( 201), which provides a clock signal (FIG. 7D) with a double period per data element, that a 0 detector (200) is present, which on the one hand contains the clock signal (FIG. 7D) from the phase-locked clock generator (201) and on the other hand from inverted output signal (Fig. 6F) of the detector (204) is applied to provide a synchronization pulse (Figs. 7H and 71) which corresponds to the second signal jump of two signal jumps that are separated by the duration of two data elements, and that devices are present, which apply the synchronization signal for synchronizing the clock and phase generator (226) to the clock and phase generator.