CH641626GA3 - - Google Patents

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Publication number
CH641626GA3
CH641626GA3 CH40980A CH40980A CH641626GA3 CH 641626G A3 CH641626G A3 CH 641626GA3 CH 40980 A CH40980 A CH 40980A CH 40980 A CH40980 A CH 40980A CH 641626G A3 CH641626G A3 CH 641626GA3
Authority
CH
Switzerland
Prior art keywords
printed circuit
circuit board
flexible printed
chip
leads
Prior art date
Application number
CH40980A
Other languages
German (de)
Other versions
CH641626B (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Publication of CH641626B publication Critical patent/CH641626B/en
Priority claimed from JP339679U external-priority patent/JPS55105991U/ja
Priority claimed from JP4182079A external-priority patent/JPS55134386A/en
Priority claimed from JP4607479A external-priority patent/JPS55138847A/en
Priority claimed from JP4806579A external-priority patent/JPS55141742A/en
Priority claimed from JP12258279A external-priority patent/JPS5646540A/en
Application filed filed Critical
Publication of CH641626GA3 publication Critical patent/CH641626GA3/de

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G17/00—Structural details; Housings
    • G04G17/02—Component assemblies
    • G04G17/04—Mounting of electronic components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

A method of fabricating an electronic watch module in which a flexible printed circuit board (12) having a printed circuit pattern and a plurality of leads (42) extending therefrom is prepared and an IC chip (14) is wireless bonded to the leads (42) of said flexible printed circuit board (12), which is then inserted into a cavity of a molding die unit (50) and at least a part of one of said flexible printed circuit board (12) and said IC chip (14) is fixedly retained within the cavity of said die unit (50). A thermoplastic resin is supplied into the cavity of said molding die unit (50) for thereby encapsulating said flexible printed circuit board (12) and said IC chip (14), without distortion of the leads (42). <IMAGE>
CH40980A 1979-01-18 1980-01-18 METHOD OF MANUFACTURING ELECTRONIC CLOCK MODULES. CH641626B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP339679U JPS55105991U (en) 1979-01-18 1979-01-18
JP4182079A JPS55134386A (en) 1979-04-06 1979-04-06 Circuit substrate for electronic watch
JP4607479A JPS55138847A (en) 1979-04-17 1979-04-17 Method of fabricating circuit substrate for watch
JP4806579A JPS55141742A (en) 1979-04-20 1979-04-20 Circuit board for watch
JP12258279A JPS5646540A (en) 1979-09-26 1979-09-26 Manufacture of circuit board for watch

Publications (2)

Publication Number Publication Date
CH641626B CH641626B (en)
CH641626GA3 true CH641626GA3 (en) 1984-03-15

Family

ID=27518355

Family Applications (1)

Application Number Title Priority Date Filing Date
CH40980A CH641626B (en) 1979-01-18 1980-01-18 METHOD OF MANUFACTURING ELECTRONIC CLOCK MODULES.

Country Status (2)

Country Link
CH (1) CH641626B (en)
GB (1) GB2042774B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2545653B1 (en) * 1983-05-04 1986-06-06 Pichot Michel METHOD AND DEVICE FOR ENCAPSULATING INTEGRATED CIRCUITS
DE68918995T2 (en) * 1988-06-23 1995-05-11 Teikoku Tsushin Kogyo Kk Assembly of electronic components.
DE19841498C2 (en) * 1998-09-10 2002-02-21 Beru Ag Method for producing an electronic component, in particular a Hall sensor

Also Published As

Publication number Publication date
GB2042774A (en) 1980-09-24
GB2042774B (en) 1983-04-13
CH641626B (en)

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