CH609200B - Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique. - Google Patents
Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique.Info
- Publication number
- CH609200B CH609200B CH1036375A CH1036375A CH609200B CH 609200 B CH609200 B CH 609200B CH 1036375 A CH1036375 A CH 1036375A CH 1036375 A CH1036375 A CH 1036375A CH 609200 B CH609200 B CH 609200B
- Authority
- CH
- Switzerland
- Prior art keywords
- igfet
- phi
- junction
- capacitor
- gate
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G99/00—Subject matter not provided for in other groups of this subclass
- G04G99/003—Pulse shaping; Amplification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Manipulation Of Pulses (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Protection Of Static Devices (AREA)
- Elimination Of Static Electricity (AREA)
- Amplifiers (AREA)
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
- Read Only Memory (AREA)
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH1036375A CH609200B (fr) | 1975-08-08 | 1975-08-08 | Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique. |
| FR7623717A FR2320598A1 (fr) | 1975-08-08 | 1976-08-03 | Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique |
| DE19762635456 DE2635456A1 (de) | 1975-08-08 | 1976-08-04 | Vorrichtung zum aufrechterhalten des elektrischen potentials eines punktes eines elektronischen schaltkreises in einem bestimmten zustand |
| NL7608695A NL7608695A (nl) | 1975-08-08 | 1976-08-05 | Inrichting voor het houden in een vastgestelde toestand van de elektrische potentiaal van een punt van een elektronische keten. |
| JP51093252A JPS5237777A (en) | 1975-08-08 | 1976-08-06 | Device for maintaining electric potential at one point of electronic circuit in determined state |
| GB32781/76A GB1546682A (en) | 1975-08-08 | 1976-08-06 | Circuit arrangement for the storage of a signal voltage ofpredetermined level |
| US05/815,016 US4110637A (en) | 1975-08-08 | 1977-07-12 | Electronic system for capacitively storing a signal voltage of predetermined level |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH1036375A CH609200B (fr) | 1975-08-08 | 1975-08-08 | Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique. |
| US71187976A | 1976-08-05 | 1976-08-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CH609200B true CH609200B (fr) | |
| CH609200GA3 CH609200GA3 (enExample) | 1979-02-28 |
Family
ID=25706518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1036375A CH609200B (fr) | 1975-08-08 | 1975-08-08 | Dispositif pour maintenir dans un etat determine le potentiel electrique d'un point d'un circuit electronique. |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4110637A (enExample) |
| JP (1) | JPS5237777A (enExample) |
| CH (1) | CH609200B (enExample) |
| DE (1) | DE2635456A1 (enExample) |
| FR (1) | FR2320598A1 (enExample) |
| GB (1) | GB1546682A (enExample) |
| NL (1) | NL7608695A (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4656367A (en) * | 1985-10-18 | 1987-04-07 | International Business Machines Corporation | Speed up of up-going transition of TTL or DTL circuits under high _capacitive load |
| US5216290A (en) * | 1988-10-19 | 1993-06-01 | Texas Instruments, Incorporated | Process of conserving charge and a boosting circuit in a high efficiency output buffer with NMOS output devices |
| IT1227561B (it) * | 1988-11-07 | 1991-04-16 | Sgs Thomson Microelectronics | Dispositivo circuitale, a ridotto numero di componenti, per l'accensione simultanea di una pluralita' di transistori di potenza |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3576571A (en) * | 1969-01-07 | 1971-04-27 | North American Rockwell | Memory circuit using storage capacitance and field effect devices |
| US3702926A (en) * | 1970-09-30 | 1972-11-14 | Ibm | Fet decode circuit |
| US3699544A (en) * | 1971-05-26 | 1972-10-17 | Gen Electric | Three transistor memory cell |
| US3744037A (en) * | 1971-10-04 | 1973-07-03 | North American Rockwell | Two-clock memory cell |
| US3855581A (en) * | 1971-12-30 | 1974-12-17 | Mos Technology Inc | Semiconductor device and circuits |
| US3798616A (en) * | 1972-04-14 | 1974-03-19 | North American Rockwell | Strobe driver including a memory circuit |
| US3903431A (en) * | 1973-12-28 | 1975-09-02 | Teletype Corp | Clocked dynamic inverter |
| SU488258A1 (ru) * | 1974-02-07 | 1975-10-15 | Предприятие П/Я Х-5885 | Динамическа чейка пам ти |
| US3924247A (en) * | 1974-08-21 | 1975-12-02 | Rockwell International Corp | Driver cell with memory and shift capability |
| US3943496A (en) * | 1974-09-09 | 1976-03-09 | Rockwell International Corporation | Memory clocking system |
| US3922650A (en) * | 1974-11-11 | 1975-11-25 | Ncr Co | Switched capacitor non-volatile mnos random access memory cell |
| US3988617A (en) * | 1974-12-23 | 1976-10-26 | International Business Machines Corporation | Field effect transistor bias circuit |
-
1975
- 1975-08-08 CH CH1036375A patent/CH609200B/fr not_active IP Right Cessation
-
1976
- 1976-08-03 FR FR7623717A patent/FR2320598A1/fr active Granted
- 1976-08-04 DE DE19762635456 patent/DE2635456A1/de not_active Withdrawn
- 1976-08-05 NL NL7608695A patent/NL7608695A/xx not_active Application Discontinuation
- 1976-08-06 GB GB32781/76A patent/GB1546682A/en not_active Expired
- 1976-08-06 JP JP51093252A patent/JPS5237777A/ja active Pending
-
1977
- 1977-07-12 US US05/815,016 patent/US4110637A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2320598B1 (enExample) | 1980-05-30 |
| FR2320598A1 (fr) | 1977-03-04 |
| JPS5237777A (en) | 1977-03-23 |
| GB1546682A (en) | 1979-05-31 |
| DE2635456A1 (de) | 1977-02-17 |
| CH609200GA3 (enExample) | 1979-02-28 |
| US4110637A (en) | 1978-08-29 |
| NL7608695A (nl) | 1977-02-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |