CH609198GA3 - Circuit arrangement for the drive-level display of signal amplifiers for clock control units - Google Patents

Circuit arrangement for the drive-level display of signal amplifiers for clock control units Download PDF

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Publication number
CH609198GA3
CH609198GA3 CH496776A CH496776A CH609198GA3 CH 609198G A3 CH609198G A3 CH 609198GA3 CH 496776 A CH496776 A CH 496776A CH 496776 A CH496776 A CH 496776A CH 609198G A3 CH609198G A3 CH 609198GA3
Authority
CH
Switzerland
Prior art keywords
clock
drive
clock control
control units
circuit arrangement
Prior art date
Application number
CH496776A
Other versions
CH609198B (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Publication of CH609198B publication Critical patent/CH609198B/en
Application filed filed Critical
Publication of CH609198GA3 publication Critical patent/CH609198GA3/en

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Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
    • G04D7/00—Measuring, counting, calibrating, testing or regulating apparatus
    • G04D7/12—Timing devices for clocks or watches for comparing the rate of the oscillating member with a standard
    • G04D7/1207—Timing devices for clocks or watches for comparing the rate of the oscillating member with a standard only for measuring
    • G04D7/1214—Timing devices for clocks or watches for comparing the rate of the oscillating member with a standard only for measuring for complete clockworks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of El Displays (AREA)
  • Electric Clocks (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Circuits Of Receivers In General (AREA)
  • Indicating Measured Values (AREA)

Abstract

The clock frequency fed to a clock control unit (28) is simultaneously transmitted to a display unit (26, 36). The latter displays a plurality of sequential clock pulses by means of a plurality of display elements (1 to 16) which are arranged in a spatially distributed fashion and driven successively. As a result, the input level of the control unit is to be displayed even in the case of high clock frequencies in an accurate and well-arranged fashion. It can thereby subsequently be determined whether a clock is arranged in the correct order on the sensor (21). <IMAGE>
CH496776A 1976-02-18 1976-04-21 Circuit arrangement for the drive-level display of signal amplifiers for clock control units CH609198GA3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19762606478 DE2606478A1 (en) 1976-02-18 1976-02-18 CIRCUIT AND ARRANGEMENT FOR THE DISPLAY OF THE DISPLAY OF SIGNAL AMPLIFIERS FOR WATCH CONTROL DEVICES

Publications (2)

Publication Number Publication Date
CH609198B CH609198B (en)
CH609198GA3 true CH609198GA3 (en) 1979-02-28

Family

ID=5970203

Family Applications (1)

Application Number Title Priority Date Filing Date
CH496776A CH609198GA3 (en) 1976-02-18 1976-04-21 Circuit arrangement for the drive-level display of signal amplifiers for clock control units

Country Status (2)

Country Link
CH (1) CH609198GA3 (en)
DE (1) DE2606478A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2470986A1 (en) * 1979-12-07 1981-06-12 Etic Sa Function checking device for electronic timepiece module - uses high input amplifier and frequency converter to provide audible signal indicating measured ultrasonic test signal amplitude

Also Published As

Publication number Publication date
CH609198B (en)
DE2606478A1 (en) 1977-08-25

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