CH607139A5 - - Google Patents

Info

Publication number
CH607139A5
CH607139A5 CH1448875A CH1448875A CH607139A5 CH 607139 A5 CH607139 A5 CH 607139A5 CH 1448875 A CH1448875 A CH 1448875A CH 1448875 A CH1448875 A CH 1448875A CH 607139 A5 CH607139 A5 CH 607139A5
Authority
CH
Switzerland
Application number
CH1448875A
Inventor
Vernon Kenneth Andersen
Michael Wayne Goddard
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of CH607139A5 publication Critical patent/CH607139A5/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
CH1448875A 1974-11-11 1975-11-10 CH607139A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/522,553 US3967247A (en) 1974-11-11 1974-11-11 Storage interface unit

Publications (1)

Publication Number Publication Date
CH607139A5 true CH607139A5 (de) 1978-11-30

Family

ID=24081323

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1448875A CH607139A5 (de) 1974-11-11 1975-11-10

Country Status (8)

Country Link
US (1) US3967247A (de)
JP (1) JPS6118222B2 (de)
CH (1) CH607139A5 (de)
DE (2) DE2560206C2 (de)
FR (1) FR2290710A1 (de)
GB (1) GB1532798A (de)
IT (1) IT1049044B (de)
SE (1) SE411404B (de)

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US4382278A (en) * 1980-06-05 1983-05-03 Texas Instruments Incorporated Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache
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US4355306A (en) * 1981-01-30 1982-10-19 International Business Machines Corporation Dynamic stack data compression and decompression system
US4414644A (en) * 1981-04-03 1983-11-08 International Business Machines Corporation Method and apparatus for discarding data from a buffer after reading such data
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CA1187198A (en) * 1981-06-15 1985-05-14 Takashi Chiba System for controlling access to channel buffers
US4439837A (en) * 1981-06-16 1984-03-27 Ncr Corporation Non-volatile memory system for intelligent terminals
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US4675812A (en) * 1983-02-14 1987-06-23 International Business Machines Corp. Priority circuit for channel subsystem having components with diverse and changing requirement for system resources
US4607331A (en) * 1983-05-13 1986-08-19 Motorola, Inc. Method and apparatus for implementing an algorithm associated with stored information
US4695951A (en) * 1983-07-07 1987-09-22 Honeywell Bull Inc. Computer hierarchy control
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
US4625273A (en) * 1983-08-30 1986-11-25 Amdahl Corporation Apparatus for fast data storage with deferred error reporting
US4710966A (en) * 1984-01-04 1987-12-01 Itek Corporation Digital frame processor pipe line circuit
US4736293A (en) * 1984-04-11 1988-04-05 American Telephone And Telegraph Company, At&T Bell Laboratories Interleaved set-associative memory
USRE34052E (en) * 1984-05-31 1992-09-01 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
US4630195A (en) * 1984-05-31 1986-12-16 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
EP0173884B1 (de) * 1984-08-10 1989-11-23 Siemens Aktiengesellschaft Schaltungsanordnung zur prioritätsbezogenen Einordnung und Registrierung einzelner Speicherabschnitte bzw. Bänke unter Anwendung des LRU-Algorithmus
DE3429571A1 (de) * 1984-08-10 1986-02-20 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur prioritaetsbezogenen einordnung und registrierung von speicherabschnitten bzw. speicherbaenken, unter anwendung des lru-algorithmus
JPH0670773B2 (ja) * 1984-11-01 1994-09-07 富士通株式会社 先行制御方式
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US4939641A (en) * 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
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US5202972A (en) * 1988-12-29 1993-04-13 International Business Machines Corporation Store buffer apparatus in a multiprocessor system
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US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5434990A (en) * 1990-08-06 1995-07-18 Ncr Corporation Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
US5218246A (en) * 1990-09-14 1993-06-08 Acer, Incorporated MOS analog XOR amplifier
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
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US5673415A (en) * 1993-12-03 1997-09-30 Unisys Corporation High speed two-port interface unit where read commands suspend partially executed write commands
JP3266470B2 (ja) * 1994-10-03 2002-03-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 強制順序で行う要求毎ライト・スルー・キャッシュを有するデータ処理システム
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US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
WO2000018041A2 (en) * 1998-09-18 2000-03-30 Harris Corporation Distributed trunking mechanism for vhf networking
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
US9274964B2 (en) 2012-02-02 2016-03-01 Qualcomm Incorporated Multi-bank cache memory

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BE622921A (de) * 1961-10-06
BE629069A (de) * 1962-03-05
US3275991A (en) * 1962-12-03 1966-09-27 Bunker Ramo Memory system
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
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US3737871A (en) * 1971-07-28 1973-06-05 Hewlett Packard Co Stack register renamer
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
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US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories

Also Published As

Publication number Publication date
FR2290710A1 (fr) 1976-06-04
SE7512524L (sv) 1976-05-12
GB1532798A (en) 1978-11-22
IT1049044B (it) 1981-01-20
SE411404B (sv) 1979-12-17
DE2550339C2 (de) 1982-10-14
DE2550339A1 (de) 1976-06-16
JPS6118222B2 (de) 1986-05-12
JPS5176936A (de) 1976-07-03
DE2560206C2 (de) 1983-01-20
US3967247A (en) 1976-06-29
FR2290710B1 (de) 1980-04-18

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Legal Events

Date Code Title Description
PFA Name/firm changed
PL Patent ceased