CH554051A - Kapazitive speichereinrichtung fuer binaer codierte daten. - Google Patents

Kapazitive speichereinrichtung fuer binaer codierte daten.

Info

Publication number
CH554051A
CH554051A CH1383573A CH1383573A CH554051A CH 554051 A CH554051 A CH 554051A CH 1383573 A CH1383573 A CH 1383573A CH 1383573 A CH1383573 A CH 1383573A CH 554051 A CH554051 A CH 554051A
Authority
CH
Switzerland
Prior art keywords
storage device
coded data
binary coded
capacitive storage
capacitive
Prior art date
Application number
CH1383573A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH554051A publication Critical patent/CH554051A/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
CH1383573A 1972-10-19 1973-09-27 Kapazitive speichereinrichtung fuer binaer codierte daten. CH554051A (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US00298918A US3811117A (en) 1972-10-19 1972-10-19 Time ordered memory system and operation
US00298917A US3810129A (en) 1972-10-19 1972-10-19 Memory system restoration

Publications (1)

Publication Number Publication Date
CH554051A true CH554051A (de) 1974-09-13

Family

ID=26970945

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1383573A CH554051A (de) 1972-10-19 1973-09-27 Kapazitive speichereinrichtung fuer binaer codierte daten.

Country Status (5)

Country Link
US (2) US3810129A (de)
CH (1) CH554051A (de)
FR (1) FR2204012B1 (de)
GB (1) GB1397007A (de)
NL (1) NL7312608A (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526506A (en) * 1970-12-28 1996-06-11 Hyatt; Gilbert P. Computer system having an improved memory architecture
US4028675A (en) * 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
IT1002272B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di ricarica in memoria a semiconduttori
JPS50156325A (de) * 1974-06-05 1975-12-17
US4142233A (en) * 1975-10-30 1979-02-27 Tokyo Shibaura Electric Co., Ltd. Refreshing system for dynamic memory
JPS5255337A (en) * 1975-10-31 1977-05-06 Hitachi Ltd Refresh control system
NL7600648A (nl) * 1976-01-22 1977-07-26 Philips Nv Geheugen met dynamische informatieopslag.
US4172282A (en) * 1976-10-29 1979-10-23 International Business Machines Corporation Processor controlled memory refresh
US4218753A (en) * 1977-02-28 1980-08-19 Data General Corporation Microcode-controlled memory refresh apparatus for a data processing system
US4227798A (en) * 1978-08-14 1980-10-14 Xerox Corporation Protection system for electrostatographic machines
US4292676A (en) * 1978-11-15 1981-09-29 Lockheed Electronics Co., Inc. Refresh cycle minimizer in a dynamic semiconductor memory
US4238842A (en) * 1978-12-26 1980-12-09 Ibm Corporation LARAM Memory with reordered selection sequence for refresh
US4241425A (en) * 1979-02-09 1980-12-23 Bell Telephone Laboratories, Incorporated Organization for dynamic random access memory
US4317169A (en) * 1979-02-14 1982-02-23 Honeywell Information Systems Inc. Data processing system having centralized memory refresh
US4387423A (en) * 1979-02-16 1983-06-07 Honeywell Information Systems Inc. Microprogrammed system having single microstep apparatus
JPS55132593A (en) * 1979-04-02 1980-10-15 Fujitsu Ltd Refresh control method for memory unit
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit
JPS6046461B2 (ja) * 1979-11-26 1985-10-16 株式会社日立製作所 アクセス要求選択回路
FR2474227A1 (fr) * 1980-01-17 1981-07-24 Cii Honeywell Bull Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant
US4357686A (en) * 1980-09-24 1982-11-02 Sperry Corporation Hidden memory refresh
JPS59119591A (ja) * 1982-12-27 1984-07-10 Toshiba Corp 半導体メモリ装置
JPS6079593A (ja) * 1983-10-07 1985-05-07 Hitachi Ltd 半導体集積回路システム
US4625296A (en) * 1984-01-17 1986-11-25 The Perkin-Elmer Corporation Memory refresh circuit with varying system transparency
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
JPH0612613B2 (ja) * 1986-03-18 1994-02-16 富士通株式会社 半導体記憶装置
US5214607A (en) * 1990-11-26 1993-05-25 Ncr Corporation Look-ahead FIFO byte count apparatus
WO1998019337A1 (en) 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
DE10329370B3 (de) * 2003-06-30 2005-01-27 Infineon Technologies Ag Schaltung und Verfahren zum Auffrischen von Speicherzellen eines dynamischen Speichers
DE10329369B4 (de) * 2003-06-30 2010-01-28 Qimonda Ag Schaltung und Verfahren zum Auffrischen von Speicherzellen eines dynamischen Speichers

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory

Also Published As

Publication number Publication date
DE2351523B2 (de) 1976-03-18
FR2204012A1 (de) 1974-05-17
US3810129A (en) 1974-05-07
NL7312608A (de) 1974-04-23
US3811117A (en) 1974-05-14
GB1397007A (en) 1975-06-11
FR2204012B1 (de) 1976-07-23
DE2351523A1 (de) 1974-05-16

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Legal Events

Date Code Title Description
PL Patent ceased