CH544160A - Verfahren zum Herstellen eines Musters in einem metallischen Film - Google Patents

Verfahren zum Herstellen eines Musters in einem metallischen Film

Info

Publication number
CH544160A
CH544160A CH971671A CH971671A CH544160A CH 544160 A CH544160 A CH 544160A CH 971671 A CH971671 A CH 971671A CH 971671 A CH971671 A CH 971671A CH 544160 A CH544160 A CH 544160A
Authority
CH
Switzerland
Prior art keywords
pattern
producing
metallic film
metallic
film
Prior art date
Application number
CH971671A
Other languages
English (en)
Inventor
Murray Richard
Kenneth Jr Stewart John
W Ditmer Robert
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Publication of CH544160A publication Critical patent/CH544160A/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/08Apparatus, e.g. for photomechanical printing surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CH971671A 1970-07-02 1971-07-01 Verfahren zum Herstellen eines Musters in einem metallischen Film CH544160A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5180870A 1970-07-02 1970-07-02

Publications (1)

Publication Number Publication Date
CH544160A true CH544160A (de) 1973-11-15

Family

ID=21973487

Family Applications (1)

Application Number Title Priority Date Filing Date
CH971671A CH544160A (de) 1970-07-02 1971-07-01 Verfahren zum Herstellen eines Musters in einem metallischen Film

Country Status (8)

Country Link
US (1) US3674579A (de)
BE (1) BE769403A (de)
BR (1) BR7103942D0 (de)
CH (1) CH544160A (de)
DE (1) DE2132109A1 (de)
FR (1) FR2100151A5 (de)
GB (1) GB1286219A (de)
ZA (1) ZA713875B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915394B2 (ja) * 1978-08-31 1984-04-09 富士通株式会社 厚膜微細パタ−ン生成方法
NL8204307A (nl) * 1982-11-08 1984-06-01 Philips Nv Werkwijze voor het etsen van holten en openingen in substraten en inrichting voor het uitvoeren van deze werkwijze.
US5185056A (en) * 1991-09-13 1993-02-09 International Business Machines Corporation Method and apparatus for etching semiconductor wafers and developing resists

Also Published As

Publication number Publication date
BE769403A (fr) 1971-11-16
ZA713875B (en) 1972-01-26
BR7103942D0 (pt) 1973-04-12
DE2132109A1 (de) 1972-02-10
FR2100151A5 (de) 1972-03-17
US3674579A (en) 1972-07-04
GB1286219A (en) 1972-08-23

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Legal Events

Date Code Title Description
PL Patent ceased