CH536028A - Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren - Google Patents

Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren

Info

Publication number
CH536028A
CH536028A CH105572A CH105572A CH536028A CH 536028 A CH536028 A CH 536028A CH 105572 A CH105572 A CH 105572A CH 105572 A CH105572 A CH 105572A CH 536028 A CH536028 A CH 536028A
Authority
CH
Switzerland
Prior art keywords
making
monolithic device
isolated transistors
transistors
isolated
Prior art date
Application number
CH105572A
Other languages
German (de)
English (en)
Inventor
Jones Ivor
J Rideout Arthur
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH105572A priority Critical patent/CH536028A/de
Priority to IT32876/72A priority patent/IT971839B/it
Priority to JP47128274A priority patent/JPS4886490A/ja
Priority to CA160,404A priority patent/CA992218A/en
Priority to DE2300412A priority patent/DE2300412A1/de
Priority to FR7301492A priority patent/FR2169069A1/fr
Publication of CH536028A publication Critical patent/CH536028A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
CH105572A 1972-01-25 1972-01-25 Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren CH536028A (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CH105572A CH536028A (de) 1972-01-25 1972-01-25 Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren
IT32876/72A IT971839B (it) 1972-01-25 1972-12-14 Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati
JP47128274A JPS4886490A (en(2012)) 1972-01-25 1972-12-22
CA160,404A CA992218A (en) 1972-01-25 1973-01-02 Process for making monolithic devices with isolated transistors
DE2300412A DE2300412A1 (de) 1972-01-25 1973-01-05 Verfahren zur herstellung integrierter transistoren
FR7301492A FR2169069A1 (en(2012)) 1972-01-25 1973-01-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH105572A CH536028A (de) 1972-01-25 1972-01-25 Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren

Publications (1)

Publication Number Publication Date
CH536028A true CH536028A (de) 1973-04-15

Family

ID=4201392

Family Applications (1)

Application Number Title Priority Date Filing Date
CH105572A CH536028A (de) 1972-01-25 1972-01-25 Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren

Country Status (6)

Country Link
JP (1) JPS4886490A (en(2012))
CA (1) CA992218A (en(2012))
CH (1) CH536028A (en(2012))
DE (1) DE2300412A1 (en(2012))
FR (1) FR2169069A1 (en(2012))
IT (1) IT971839B (en(2012))

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2532694B2 (ja) * 1989-11-22 1996-09-11 三菱電機株式会社 半導体装置の製造方法
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate

Also Published As

Publication number Publication date
DE2300412A1 (de) 1973-08-02
FR2169069A1 (en(2012)) 1973-09-07
JPS4886490A (en(2012)) 1973-11-15
CA992218A (en) 1976-06-29
IT971839B (it) 1974-05-10

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Legal Events

Date Code Title Description
PL Patent ceased