CH491546A - Schaltungsanordnung mit mindestens einem Taktgeber - Google Patents

Schaltungsanordnung mit mindestens einem Taktgeber

Info

Publication number
CH491546A
CH491546A CH202367A CH202367A CH491546A CH 491546 A CH491546 A CH 491546A CH 202367 A CH202367 A CH 202367A CH 202367 A CH202367 A CH 202367A CH 491546 A CH491546 A CH 491546A
Authority
CH
Switzerland
Prior art keywords
circuit arrangement
clock generator
clock
generator
arrangement
Prior art date
Application number
CH202367A
Other languages
English (en)
Inventor
Henry Rees Frederick
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Publication of CH491546A publication Critical patent/CH491546A/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/12—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)
CH202367A 1966-02-11 1967-02-10 Schaltungsanordnung mit mindestens einem Taktgeber CH491546A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB6091/66A GB1110093A (en) 1966-02-11 1966-02-11 Electrical circuit units and oscillation generators including triggered pulse generators

Publications (1)

Publication Number Publication Date
CH491546A true CH491546A (de) 1970-05-31

Family

ID=9808212

Family Applications (1)

Application Number Title Priority Date Filing Date
CH202367A CH491546A (de) 1966-02-11 1967-02-10 Schaltungsanordnung mit mindestens einem Taktgeber

Country Status (5)

Country Link
US (1) US3411107A (de)
CH (1) CH491546A (de)
DE (1) DE1512246A1 (de)
FR (1) FR1510538A (de)
GB (1) GB1110093A (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3522455A (en) * 1967-07-27 1970-08-04 Bendix Corp Method and means of synchronizing timing pulses of a three channel triplicated system
US3543184A (en) * 1968-11-27 1970-11-24 Bell Telephone Labor Inc Controllable logic gate oscillator
US3619661A (en) * 1970-02-05 1971-11-09 Lorain Prod Corp Multichannel control circuit
US3775696A (en) * 1971-11-18 1973-11-27 Texas Instruments Inc Synchronous digital system having a multispeed logic clock oscillator
US4255668A (en) * 1978-03-30 1981-03-10 Emi Limited Pulsed power supplies
US4423338A (en) * 1982-03-01 1983-12-27 International Business Machines Corporation Single shot multivibrator having reduced recovery time
US4710653A (en) * 1986-07-03 1987-12-01 Grumman Aerospace Corporation Edge detector circuit and oscillator using same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1050126A (de) * 1963-12-19

Also Published As

Publication number Publication date
FR1510538A (fr) 1968-01-19
DE1512246A1 (de) 1969-07-03
GB1110093A (en) 1968-04-18
US3411107A (en) 1968-11-12

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Legal Events

Date Code Title Description
PL Patent ceased