CH479120A - Datenverarbeitungsanlage mit einem Hauptspeicher und einem Aktivspeicher und variabler Adressierung des letzteren - Google Patents

Datenverarbeitungsanlage mit einem Hauptspeicher und einem Aktivspeicher und variabler Adressierung des letzteren

Info

Publication number
CH479120A
CH479120A CH1435568A CH1435568A CH479120A CH 479120 A CH479120 A CH 479120A CH 1435568 A CH1435568 A CH 1435568A CH 1435568 A CH1435568 A CH 1435568A CH 479120 A CH479120 A CH 479120A
Authority
CH
Switzerland
Prior art keywords
memory
data processing
processing system
main memory
variable addressing
Prior art date
Application number
CH1435568A
Other languages
English (en)
Inventor
Kay Womack Karl
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH479120A publication Critical patent/CH479120A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
CH1435568A 1967-09-27 1968-09-25 Datenverarbeitungsanlage mit einem Hauptspeicher und einem Aktivspeicher und variabler Adressierung des letzteren CH479120A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67091867A 1967-09-27 1967-09-27

Publications (1)

Publication Number Publication Date
CH479120A true CH479120A (de) 1969-09-30

Family

ID=24692423

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1435568A CH479120A (de) 1967-09-27 1968-09-25 Datenverarbeitungsanlage mit einem Hauptspeicher und einem Aktivspeicher und variabler Adressierung des letzteren

Country Status (10)

Country Link
US (1) US3500337A (de)
AT (1) AT281471B (de)
BE (1) BE719724A (de)
CH (1) CH479120A (de)
DE (1) DE1774864C2 (de)
ES (1) ES358451A1 (de)
FR (1) FR1580607A (de)
GB (1) GB1235927A (de)
NL (1) NL6813831A (de)
SE (1) SE329284B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE758811A (fr) * 1969-11-28 1971-04-16 Burroughs Corp Systeme de traitement d'information ayant un emmagasinage sans structure pour traitements emboites
US3626374A (en) * 1970-02-10 1971-12-07 Bell Telephone Labor Inc High-speed data-directed information processing system characterized by a plural-module byte-organized memory unit
US3946366A (en) * 1973-01-26 1976-03-23 Sanders Associates, Inc. Addressing technique employing both direct and indirect register addressing
US11808111B2 (en) 2022-02-11 2023-11-07 Weatherford Technology Holdings, Llc Rotating control device with integrated cooling for sealed bearings

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB976499A (en) * 1960-03-16 1964-11-25 Nat Res Dev Improvements in or relating to electronic digital computing machines
FR1355606A (fr) * 1962-01-22 1964-03-20 Ibm Système de mémoires destiné à un emmagasinage à lecture rapide
US3311887A (en) * 1963-04-12 1967-03-28 Ibm File memory system with key to address transformation apparatus
US3290656A (en) * 1963-06-28 1966-12-06 Ibm Associative memory for subroutines
US3337851A (en) * 1963-12-09 1967-08-22 Burroughs Corp Memory organization for reducing access time of program repetitions
USRE26429E (en) * 1964-12-08 1968-08-06 Information retrieval system and method

Also Published As

Publication number Publication date
US3500337A (en) 1970-03-10
GB1235927A (en) 1971-06-16
BE719724A (de) 1969-02-03
DE1774864B1 (de) 1972-08-31
DE1774864C2 (de) 1975-04-03
FR1580607A (de) 1969-09-05
AT281471B (de) 1970-05-25
NL6813831A (de) 1969-03-31
SE329284B (de) 1970-10-05
ES358451A1 (es) 1970-03-16

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Legal Events

Date Code Title Description
PL Patent ceased