CH477094A - Dispositif semi-conducteur et procédé pour sa fabrication - Google Patents

Dispositif semi-conducteur et procédé pour sa fabrication

Info

Publication number
CH477094A
CH477094A CH65168A CH65168A CH477094A CH 477094 A CH477094 A CH 477094A CH 65168 A CH65168 A CH 65168A CH 65168 A CH65168 A CH 65168A CH 477094 A CH477094 A CH 477094A
Authority
CH
Switzerland
Prior art keywords
manufacture
semiconductor device
semiconductor
Prior art date
Application number
CH65168A
Other languages
English (en)
Inventor
Marion Wanlass Frank
Mecchi Aldo
Harry Muller Warren
Original Assignee
Gen Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Instrument Corp filed Critical Gen Instrument Corp
Publication of CH477094A publication Critical patent/CH477094A/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CH65168A 1967-02-08 1968-01-15 Dispositif semi-conducteur et procédé pour sa fabrication CH477094A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61471567A 1967-02-08 1967-02-08

Publications (1)

Publication Number Publication Date
CH477094A true CH477094A (fr) 1969-08-15

Family

ID=24462425

Family Applications (1)

Application Number Title Priority Date Filing Date
CH65168A CH477094A (fr) 1967-02-08 1968-01-15 Dispositif semi-conducteur et procédé pour sa fabrication

Country Status (8)

Country Link
US (1) US3503124A (fr)
JP (1) JPS4811671B1 (fr)
CH (1) CH477094A (fr)
DE (1) DE1639241A1 (fr)
FR (1) FR1551444A (fr)
GB (1) GB1207370A (fr)
NL (1) NL141030B (fr)
SE (1) SE350367B (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575052B1 (fr) * 1971-06-16 1982-01-28
JPS567305B2 (fr) * 1973-01-19 1981-02-17
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4003126A (en) * 1974-09-12 1977-01-18 Canadian Patents And Development Limited Method of making metal oxide semiconductor devices
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
US5140387A (en) * 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
DE19743342C2 (de) * 1997-09-30 2002-02-28 Infineon Technologies Ag Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung
EP2041786A2 (fr) * 2006-07-10 2009-04-01 Nxp B.V. Circuit intégré, transpondeur, procédé de production d'un circuit intégré et procédé de production d'un transpondeur

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL251064A (fr) * 1955-11-04
US2981877A (en) * 1959-07-30 1961-04-25 Fairchild Semiconductor Semiconductor device-and-lead structure
US3247428A (en) * 1961-09-29 1966-04-19 Ibm Coated objects and methods of providing the protective coverings therefor
US3309585A (en) * 1963-11-29 1967-03-14 Westinghouse Electric Corp Junction transistor structure with interdigitated configuration having features to minimize localized heating
US3280391A (en) * 1964-01-31 1966-10-18 Fairchild Camera Instr Co High frequency transistors
US3298863A (en) * 1964-05-08 1967-01-17 Joseph H Mccusker Method for fabricating thin film transistors
US3372063A (en) * 1964-12-22 1968-03-05 Hitachi Ltd Method for manufacturing at least one electrically isolated region of a semiconductive material
US3341743A (en) * 1965-10-21 1967-09-12 Texas Instruments Inc Integrated circuitry having discrete regions of semiconductor material isolated by an insulating material

Also Published As

Publication number Publication date
NL141030B (nl) 1974-01-15
NL6801748A (fr) 1968-08-09
JPS4811671B1 (fr) 1973-04-14
GB1207370A (en) 1970-09-30
FR1551444A (fr) 1968-12-27
US3503124A (en) 1970-03-31
SE350367B (fr) 1972-10-23
DE1639241A1 (de) 1970-01-22

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Legal Events

Date Code Title Description
PL Patent ceased