CH450769A - Circuit arrangement for the parallel addition of binary operands - Google Patents

Circuit arrangement for the parallel addition of binary operands

Info

Publication number
CH450769A
CH450769A CH469966A CH469966A CH450769A CH 450769 A CH450769 A CH 450769A CH 469966 A CH469966 A CH 469966A CH 469966 A CH469966 A CH 469966A CH 450769 A CH450769 A CH 450769A
Authority
CH
Switzerland
Prior art keywords
circuit arrangement
parallel addition
binary operands
operands
binary
Prior art date
Application number
CH469966A
Other languages
German (de)
Inventor
Richard Geller Alan
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH450769A publication Critical patent/CH450769A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
CH469966A 1965-04-05 1966-03-31 Circuit arrangement for the parallel addition of binary operands CH450769A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44532165A 1965-04-05 1965-04-05
US44532065A 1965-04-05 1965-04-05

Publications (1)

Publication Number Publication Date
CH450769A true CH450769A (en) 1968-01-31

Family

ID=27034268

Family Applications (1)

Application Number Title Priority Date Filing Date
CH469966A CH450769A (en) 1965-04-05 1966-03-31 Circuit arrangement for the parallel addition of binary operands

Country Status (3)

Country Link
CH (1) CH450769A (en)
DE (1) DE1524141A1 (en)
NL (1) NL6604323A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2621480B2 (en) * 1989-06-06 1997-06-18 日本電気株式会社 Addition circuit inspection device

Also Published As

Publication number Publication date
DE1524141A1 (en) 1970-07-09
NL6604323A (en) 1966-10-06

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