CH450769A - Schaltungsanordnung zur Parallel-Addition binärer Operanden - Google Patents
Schaltungsanordnung zur Parallel-Addition binärer OperandenInfo
- Publication number
- CH450769A CH450769A CH469966A CH469966A CH450769A CH 450769 A CH450769 A CH 450769A CH 469966 A CH469966 A CH 469966A CH 469966 A CH469966 A CH 469966A CH 450769 A CH450769 A CH 450769A
- Authority
- CH
- Switzerland
- Prior art keywords
- circuit arrangement
- parallel addition
- binary operands
- operands
- binary
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44532065A | 1965-04-05 | 1965-04-05 | |
| US44532165A | 1965-04-05 | 1965-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH450769A true CH450769A (de) | 1968-01-31 |
Family
ID=27034268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH469966A CH450769A (de) | 1965-04-05 | 1966-03-31 | Schaltungsanordnung zur Parallel-Addition binärer Operanden |
Country Status (3)
| Country | Link |
|---|---|
| CH (1) | CH450769A (de) |
| DE (1) | DE1524141A1 (de) |
| NL (1) | NL6604323A (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2621480B2 (ja) * | 1989-06-06 | 1997-06-18 | 日本電気株式会社 | 加算回路検査装置 |
-
1966
- 1966-03-19 DE DE19661524141 patent/DE1524141A1/de active Pending
- 1966-03-31 CH CH469966A patent/CH450769A/de unknown
- 1966-04-01 NL NL6604323A patent/NL6604323A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NL6604323A (de) | 1966-10-06 |
| DE1524141A1 (de) | 1970-07-09 |
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