CH502724A - Circuit arrangement for the execution of logical functions - Google Patents

Circuit arrangement for the execution of logical functions

Info

Publication number
CH502724A
CH502724A CH1751369A CH1751369A CH502724A CH 502724 A CH502724 A CH 502724A CH 1751369 A CH1751369 A CH 1751369A CH 1751369 A CH1751369 A CH 1751369A CH 502724 A CH502724 A CH 502724A
Authority
CH
Switzerland
Prior art keywords
execution
circuit arrangement
logical functions
logical
functions
Prior art date
Application number
CH1751369A
Other languages
German (de)
Inventor
Manfred Dipl Ing Mihm
Original Assignee
Bbc Brown Boveri & Cie
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bbc Brown Boveri & Cie filed Critical Bbc Brown Boveri & Cie
Publication of CH502724A publication Critical patent/CH502724A/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/098Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using thyristors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/12Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/35Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
    • H03K3/352Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region the devices being thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
CH1751369A 1968-12-13 1969-11-25 Circuit arrangement for the execution of logical functions CH502724A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19681814486 DE1814486A1 (en) 1968-12-13 1968-12-13 Circuit arrangement for the execution of logical functions

Publications (1)

Publication Number Publication Date
CH502724A true CH502724A (en) 1971-01-31

Family

ID=5716134

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1751369A CH502724A (en) 1968-12-13 1969-11-25 Circuit arrangement for the execution of logical functions

Country Status (2)

Country Link
CH (1) CH502724A (en)
DE (1) DE1814486A1 (en)

Also Published As

Publication number Publication date
DE1814486A1 (en) 1970-06-25

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Legal Events

Date Code Title Description
PL Patent ceased