CH420264A - Logische Schaltung - Google Patents
Logische SchaltungInfo
- Publication number
- CH420264A CH420264A CH616460A CH616460A CH420264A CH 420264 A CH420264 A CH 420264A CH 616460 A CH616460 A CH 616460A CH 616460 A CH616460 A CH 616460A CH 420264 A CH420264 A CH 420264A
- Authority
- CH
- Switzerland
- Prior art keywords
- logical circuit
- logical
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
- G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Power Engineering (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Nonlinear Science (AREA)
- Dc Digital Transmission (AREA)
- Interface Circuits In Exchanges (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1633259 | 1959-05-25 | ||
JP740660 | 1960-03-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
CH420264A true CH420264A (de) | 1966-09-15 |
Family
ID=26341692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH616460A CH420264A (de) | 1959-05-25 | 1960-05-25 | Logische Schaltung |
Country Status (4)
Country | Link |
---|---|
CH (1) | CH420264A (en)) |
DE (1) | DE1424728A1 (en)) |
GB (1) | GB958565A (en)) |
NL (1) | NL251984A (en)) |
-
0
- NL NL251984D patent/NL251984A/xx unknown
-
1960
- 1960-05-24 GB GB1834260A patent/GB958565A/en not_active Expired
- 1960-05-24 DE DE19601424728 patent/DE1424728A1/de active Pending
- 1960-05-25 CH CH616460A patent/CH420264A/de unknown
Also Published As
Publication number | Publication date |
---|---|
DE1424728A1 (de) | 1968-10-31 |
NL251984A (en)) | |
GB958565A (en) | 1964-05-21 |
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