CH434362A - Logische Schaltung - Google Patents
Logische SchaltungInfo
- Publication number
- CH434362A CH434362A CH8244459A CH8244459A CH434362A CH 434362 A CH434362 A CH 434362A CH 8244459 A CH8244459 A CH 8244459A CH 8244459 A CH8244459 A CH 8244459A CH 434362 A CH434362 A CH 434362A
- Authority
- CH
- Switzerland
- Prior art keywords
- logical circuit
- logical
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
- G06F5/017—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Digital Magnetic Recording (AREA)
- Coils Or Transformers For Communication (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3835558 | 1958-12-30 | ||
JP599659 | 1959-02-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
CH434362A true CH434362A (de) | 1967-04-30 |
Family
ID=26340050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH8244459A CH434362A (de) | 1958-12-30 | 1959-12-29 | Logische Schaltung |
Country Status (6)
Country | Link |
---|---|
US (1) | US3292002A (de) |
CH (1) | CH434362A (de) |
DE (1) | DE1173704B (de) |
FR (1) | FR1244141A (de) |
GB (1) | GB949038A (de) |
NL (2) | NL140118B (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3541522A (en) * | 1967-08-02 | 1970-11-17 | Bell Telephone Labor Inc | Magnetic logic arrangement |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB721669A (en) * | 1950-05-19 | 1955-01-12 | Emi Ltd | Improvements in or relating to magnetisable core circuits such as utilised in computing apparatus |
NL197480A (de) * | 1954-05-25 | |||
US2919354A (en) * | 1955-11-23 | 1959-12-29 | Ibm | Magnetic core logical circuit |
US2958076A (en) * | 1956-08-17 | 1960-10-25 | Lab For Electronics Inc | Data synchronizer |
NL227342A (de) * | 1957-04-30 | |||
US3098157A (en) * | 1957-12-23 | 1963-07-16 | Kodusai Denshin Denwa Kabushik | Logical element |
US3030519A (en) * | 1958-01-20 | 1962-04-17 | Burroughs Corp | "and" function circuit |
US3030520A (en) * | 1958-01-20 | 1962-04-17 | Burroughs Corp | Logical "or" circuit |
-
0
- NL NL246937D patent/NL246937A/xx unknown
-
1959
- 1959-12-21 GB GB43356/59A patent/GB949038A/en not_active Expired
- 1959-12-29 DE DEK39550A patent/DE1173704B/de active Pending
- 1959-12-29 CH CH8244459A patent/CH434362A/de unknown
- 1959-12-30 NL NL59246937A patent/NL140118B/xx unknown
- 1959-12-30 FR FR814549A patent/FR1244141A/fr not_active Expired
-
1965
- 1965-07-13 US US475308A patent/US3292002A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR1244141A (fr) | 1960-10-21 |
NL246937A (de) | |
US3292002A (en) | 1966-12-13 |
GB949038A (en) | 1964-02-12 |
NL140118B (nl) | 1973-10-15 |
DE1173704B (de) | 1964-07-09 |
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