CH395592A - Circuit de multiplication binaire - Google Patents

Circuit de multiplication binaire

Info

Publication number
CH395592A
CH395592A CH1512361A CH1512361A CH395592A CH 395592 A CH395592 A CH 395592A CH 1512361 A CH1512361 A CH 1512361A CH 1512361 A CH1512361 A CH 1512361A CH 395592 A CH395592 A CH 395592A
Authority
CH
Switzerland
Prior art keywords
multiplication circuit
binary multiplication
binary
circuit
multiplication
Prior art date
Application number
CH1512361A
Other languages
English (en)
Inventor
Jean Foursin Pierre
Original Assignee
Standard Telephone & Radio Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone & Radio Sa filed Critical Standard Telephone & Radio Sa
Publication of CH395592A publication Critical patent/CH395592A/fr

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.
    • G06F7/4915Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CH1512361A 1960-12-29 1961-12-29 Circuit de multiplication binaire CH395592A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR848276A FR1283965A (fr) 1960-12-29 1960-12-29 Circuit de multiplication binaire

Publications (1)

Publication Number Publication Date
CH395592A true CH395592A (fr) 1965-07-15

Family

ID=8745697

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1512361A CH395592A (fr) 1960-12-29 1961-12-29 Circuit de multiplication binaire

Country Status (4)

Country Link
CH (1) CH395592A (fr)
DE (1) DE1151398B (fr)
FR (1) FR1283965A (fr)
GB (1) GB945527A (fr)

Also Published As

Publication number Publication date
DE1151398B (de) 1963-07-11
GB945527A (en) 1964-01-02
FR1283965A (fr) 1962-02-09

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