CA2544250A1 - Apparatus and method for interfacing between modem and memory in mobile station - Google Patents
Apparatus and method for interfacing between modem and memory in mobile station Download PDFInfo
- Publication number
- CA2544250A1 CA2544250A1 CA002544250A CA2544250A CA2544250A1 CA 2544250 A1 CA2544250 A1 CA 2544250A1 CA 002544250 A CA002544250 A CA 002544250A CA 2544250 A CA2544250 A CA 2544250A CA 2544250 A1 CA2544250 A1 CA 2544250A1
- Authority
- CA
- Canada
- Prior art keywords
- error correction
- correction code
- nand flash
- flash memory
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract 17
- 230000003936 working memory Effects 0.000 claims 4
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
An internal data processing apparatus and method in a mobile station. A NOR
flash memory is replaced with a NAND flash memory as a memory for storing internal data, and a modem is interfaced with the NAND flash memory.
flash memory is replaced with a NAND flash memory as a memory for storing internal data, and a modem is interfaced with the NAND flash memory.
Claims (6)
1. A circuit incorporating NAND flash memory having a plurality of input and output pins and having first addresses, for storing information required for the operation of an object, receiving a read command and an address, and outputting information stored at the address, the circuit comprising:
a working memory having a capacity smaller than the capacity of the NAND
flash memory, for copying part of the information stored in the NAND flash memory therein and having second addresses different from the first addresses of the NAND
flash memory;
a programmable memory for having basic codes required to copy the part of the information stored in the NAND flash memory to the working memory; and a controller connected to the programmable memory, for controlling random reading of the information stored in the working memory using the second addresses.
a working memory having a capacity smaller than the capacity of the NAND
flash memory, for copying part of the information stored in the NAND flash memory therein and having second addresses different from the first addresses of the NAND
flash memory;
a programmable memory for having basic codes required to copy the part of the information stored in the NAND flash memory to the working memory; and a controller connected to the programmable memory, for controlling random reading of the information stored in the working memory using the second addresses.
2. The circuit of claim 1, wherein the controller reads the basic codes from the programmable memory and copies the part of the information stored in the NAND flash memory in the working memory at an initial operation.
3. The circuit of claim 1, further comprising an error correction code generator for generating an error correction code for data to be written or read and outputting the error correction code to the controller.
4. The circuit of claim 3, wherein the controller controls the error correction code generator to generate an error correction code and controls the NAND
flash memory to store the error correction code at an address different from an address for data when the data is written to the NAND flash memory.
flash memory to store the error correction code at an address different from an address for data when the data is written to the NAND flash memory.
5. The circuit of claim 3, wherein when data is read, the controller controls the error correction code generator to generate an error correction code, reads an error correction code stored at a different address from the data in the NAND
flash memory, compares the generated error correction code with the read error correction code, and determines whether the read data has errors according to the comparison.
flash memory, compares the generated error correction code with the read error correction code, and determines whether the read data has errors according to the comparison.
6. The circuit of claim 1, wherein the basic code consists of a vector table, boot code and load code.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2001/50012 | 2001-08-20 | ||
| KR20010050012 | 2001-08-20 | ||
| KR2002/33697 | 2002-06-17 | ||
| KR1020020033697A KR100860682B1 (en) | 2001-08-20 | 2002-06-17 | Apparatus and method for interfacing between modem and memory in mobile station |
| CA2426183A CA2426183C (en) | 2001-08-20 | 2002-08-20 | Apparatus and method for interfacing between modem and memory in mobile station |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2426183A Division CA2426183C (en) | 2001-08-20 | 2002-08-20 | Apparatus and method for interfacing between modem and memory in mobile station |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2544250A1 true CA2544250A1 (en) | 2003-02-27 |
| CA2544250C CA2544250C (en) | 2012-01-03 |
Family
ID=36693981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2544250A Expired - Fee Related CA2544250C (en) | 2001-08-20 | 2002-08-20 | Apparatus and method for interfacing between modem and memory in mobile station |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2544250C (en) |
-
2002
- 2002-08-20 CA CA2544250A patent/CA2544250C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2544250C (en) | 2012-01-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20170821 |