KR100860682B1 - Apparatus and method for interfacing between modem and memory in mobile station - Google Patents

Abstract

The present invention relates to an internal data processing apparatus and method of a mobile terminal, and implements an exclusive logical OR flash memory using an exclusive logical OR flash memory as a memory for storing internal internal data and between a modem and the exclusive logical OR flash memory. An apparatus and method for interfacing data are provided.

Modem, Exclusive AND Flash Memory, Interface

Description

Interface device and method between modem and memory in mobile terminal {APPARATUS AND METHOD FOR INTERFACING BETWEEN MODEM AND MEMORY IN MOBILE STATION}             

1 is a view showing an interface device between a modem and a memory in a conventional mobile terminal,

2 is a view showing an interface device between a modem and a memory in a mobile terminal according to an embodiment of the present invention;

3 is a diagram illustrating a detailed configuration of a memory controller shown in FIG. 2;

4 is a diagram illustrating a control flow for recording data from a modem of a mobile terminal to a memory according to an embodiment of the present invention;

5 is a diagram illustrating a control flow for a modem of a mobile terminal to read data from a memory according to an embodiment of the present invention;

6 is a diagram illustrating a configuration of some of the combination logic illustrated in FIG. 3;

7 is a timing diagram of each signal when the combination logic according to the present invention is configured as shown in FIG. 6;

8 is a detailed circuit diagram of a combination logic according to another embodiment of the present invention;

9 is a timing diagram of a signal input to an error correction code generator when having combination logic according to a second embodiment of the present invention;

The present invention relates to an apparatus and method for processing internal data of a mobile terminal, and more particularly, to an apparatus and method for interfacing data between a modem and a memory.

Mobile terminals initially serviced only voice calls, but various services including data services are being supported due to consumer demands and the development of the communication industry. Representative examples thereof include a text service, a graphic service, an electronic mail service, a voice mail service, a navigation service, a moving picture service, and the like.

On the other hand, the mobile terminal is provided with a modem for processing various data received through the wireless network and various data transmitted to the wireless network. The modem is typically implemented in the form of a chip, which will be referred to as a core chip for driving a mobile terminal. In addition, the mobile terminal includes a memory for storing data for a service as described above and a variety of information for the operation of the mobile terminal. Accordingly, the mobile terminal requires an apparatus for interfacing data between the modem and the memory in order to perform the service as described above.

In the related art, a mobile terminal uses an exclusive OR gate flash memory as the memory for storing data such as various application programs and operating codes.

The configuration of interfacing data between the modem and the memory in the mobile terminal using the NOR flash memory is shown in FIG. 1.

As shown in FIG. 1, in order to interface data between the modem 110 and the NOR flash memory 112, a chip select signal (hereinafter referred to as “ROM_CSB”) and a read enable signal (Read Enable) are described below. Referred to as "RDB", write enable signal (hereinafter referred to as "WRB"), address signal (hereinafter referred to as "A '") and data signal (hereinafter referred to as "D") ). Meanwhile, in order to interface data between the modem 110 and the working memory 114, "RAM_CSB" is used as the chip select signal together with the above-described signals.

Referring to FIG. 1, the modem 110 processes data received through a wireless network or data to be transmitted to the wireless network. On the other hand, the modem 110 stores the data to be stored in the NOR flash memory 112 when a new data to be generated due to the transmission / reception of data through the wireless network. Meanwhile, the modem 110 reads data required for transmission to the wireless network from the NOR flash memory 112. In addition, when the power of the mobile terminal is turned on, the modem 110 accesses a basic code (eg, a boot code, a vector table, a load code, etc.) necessary for initial setting through the NOR flash memory 112. The NOR flash memory 112 stores data such as various application programs and operation codes required by the mobile terminal. The working memory 114 is a memory in which the modem 110 temporarily stores an application program or the like required to process predetermined data or provide a specific service, and is accessible when necessary. The working memory 114 may use SRAM. For example, after the initial setting of the mobile terminal, the modem 110 reads an operating code (OS code) and call processing software (Call S / W) from the NOR flash memory 112 to the working memory 114. Copy Thereafter, the modem 110 accesses and operates the working memory 114. The reason why the modem 110 copies the data from the NOR flash memory 112 to the working memory 114 is that the access time of the SRAM used as the working memory 114 is short, so that the required data can be quickly generated. Because it can be accessed. In addition, the modem 110 may read or write various application data directly from the NOR flash memory 112. However, it may be copied and accessed into the working memory 114 as needed.

The modem 110 enables the NOR flash memory 112 by ROM_CSB to write data to the NOR flash memory 112, and designates a predetermined address by the address signal A during the period in which the WRB is enabled. At the same time, predetermined data to be written to the data signal D is provided to the NOR flash memory 112. The NOR flash memory 112 is enabled by the ROM_CSB from the modem 110 and is designated by the address signal A when it receives an address signal A and a data signal D during a period in which the WRB is enabled. Data corresponding to the data signal D is stored in a memory area.

On the other hand, the modem 110 enables the NOR flash memory 112 by the ROM_CSB to read data from the NOR flash memory 112, and by the address signal A during the period in which the RDB is enabled. The data signal D is provided from the NOR flash memory 112. The NOR flash memory 112 is enabled by the ROM_CSB from the modem 110 and data from the memory area specified by the address signal A provided from the modem 110 during the period in which the RDB is enabled. Is read and transmitted to the modem 110 as the data signal D.

The modem 110 enables the working memory 114 by RAM_CSB to write data to the working memory 114, and designates a predetermined address by the address signal A during the period in which the WRB is enabled. At the same time, predetermined data to be written to the data signal D is provided to the working memory 114. The working memory 114 is enabled by the RAM_CSB from the modem 110, and a memory area designated by the address signal A when receiving the address signal A and the data signal D during the period in which the WRB is enabled. The data according to the data signal D is stored in.

On the other hand, the modem 110 enables the working memory 114 by the RAM_CSB to read data from the working memory 114, and the working by the address signal A during the period in which the RDB is enabled. The data signal D is provided from the memory 114. The working memory 114 is enabled by the RAM_CSB from the modem 110 and receives data from the memory area specified by the address signal A provided from the modem 110 during the period in which the RDB is enabled. The data signal is read and transmitted to the modem 110 as the data signal D.

The size of the memory for various services currently provided by the mobile terminal is also available in 16M / 32Mbit. However, as mentioned earlier, the future communication market (eg, "IMT-2000"), in which the size of the data file increases due to the growth of the communication market and the diversification, high functionality, and high capacity of mobile terminal services. Service ") requires 64M / 128MBit of memory as well as more memory.

However, in the NOR flash memory used in the conventional mobile terminal, it is impossible to supply 64 Mbit or more products at a low level due to the structure. In addition, due to the explosive demand for NOR flash memory, it is difficult to secure parts for NOR flash memory production. In order to solve this problem, the use of exclusive AND gate flash memory (NAND Flash Memory), which can be realized at a low price, will become a trend of memory configuration in a mobile terminal in the future.

On the other hand, NOR flash memory per megabyte is $ 3.56 and NAND flash memory is $ 0.83 when compared to NOR flash memory and NAND flash memory at the same capacity. In 2002, NOR flash memory is expected to be $ 3.06 and NAND flash memory is $ 0.60.

In addition, in comparison with the current density (Density), the density of the NAND flash memory corresponding to 64 Mbit of the NOR flash memory is 512 Mbit. In 2002, the density of NAND flash memory corresponding to 128 Mbit of NOR flash memory is expected to be 1024 Mbit.

In other words, it can be seen that NOR flash memory is inferior in cost or density compared to NAND flash memory. In view of these realities and expectations, the use of NOR flash memory in mobile communication equipment has reached its limit.

Accordingly, an aspect of the present invention is to provide a mobile terminal using an exclusive AND gate flash memory as a memory.

The present invention provides an interface device and method for interfacing data between a modem and an AND gate flash memory of a mobile terminal.

In a first aspect for achieving the above object, the present invention provides an interface between an exclusive logical AND flash memory for storing predetermined data and a modem for processing predetermined data for writing to the exclusive logical OR flash memory. An apparatus, comprising: a portion having a smaller capacity than the exclusive AND flash memory, copying some of the information stored in the exclusive AND flash memory, and copying a second address different from the first address of the exclusive AND flash memory. A programmable memory having a working memory to store, basic data required for copying partial information of the information stored in the exclusive AND flash memory into the working memory, and connected to the programmable memory and stored in the working memory; The above partial information It characterized in that it comprises a controller for controlling to read out at random with a group different from the first address.

In a second aspect for achieving the above object, the present invention provides a method for interfacing data between an exclusive-OR flash memory for storing predetermined data and a modem for processing predetermined data for writing to the exclusive-OR flash memory. An apparatus, comprising: a memory controller for controlling an error correction code written to the exclusive AND flash memory and data received from the modem when a chip select signal and a write command are enabled, and activated by the modem; A mask ROM outputting a basic code required for initialization upon receipt of a read command from the modem when initial power is supplied to the terminal, and an error corresponding to predetermined data from the modem, activated by control from the memory controller. Generate a correction code to It is characterized in that it comprises a generator providing an error correction code to the modem.

In a third aspect to achieve the above object, the present invention provides a mobile terminal comprising an exclusive logical product flash memory for storing predetermined data and a modem for processing predetermined data recorded in the exclusive logical product flash memory. A method of interfacing data between the exclusive logical AND flash memory and the modem, the method comprising: a second chip selection signal for activating the exclusive logical AND flash memory when the first chip select signal and the write command are enabled by the modem; And enabling the command latch enable signal to transmit a write command to the exclusive AND flash memory, disabling the command latch enable signal, and enabling the address latch enable signal to transmit a write address. To the modem in the exclusive AND flash memory. The process of recording the predetermined data and the emitter, the second chip select signal, characterized in that it comprises the step of disabling.
In a fourth aspect for achieving the above object, the present invention provides an exclusive AND memory flash memory for storing predetermined data, a modem for processing predetermined data recorded from the exclusive AND memory flash memory, and the exclusive AND memory flash memory. A method for interfacing data between the exclusive logical product flash memory and the modem in a mobile terminal including an error correction code generator for generating an error correction code corresponding to the predetermined data recorded by the first chip, the first chip being selected by the modem. When the signal and the read command are enabled, enabling a second chip select signal and an instruction latch enable signal for activating the exclusive AND flash memory, and transmitting a read command to the exclusive AND flash memory; Disable the Command Latch Enable Signal And enabling an address latch enable signal to transmit a read address to the exclusive logical product flash memory, and to read data with an error correction code and a read address of the corresponding data, and the address latch enable signal. Disabling a third chip selection signal to generate an error correction code corresponding to the data from the error correction code generator; and comparing the generated error correction code with a read error correction code to generate an error of the read data. And determining whether or not an error has occurred and performing error correction on the read data.

In a fifth aspect for achieving the above object, the present invention provides an exclusive AND memory flash memory for storing predetermined data, a programmable memory having basic data for initializing from the exclusive AND product, and the exclusive data. A method of interfacing data between an exclusive logical AND flash memory and a modem in a mobile terminal having a working memory having a different address from the logical AND flash memory and a modem for processing predetermined data read from the exclusive logical AND flash memory. And initializing a modem based on basic data from the programmable memory, reading data from the exclusive logical product flash memory based on the basic data, and writing the read data to the working memory. A it characterized in that it comprises.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, in order to replace and use the NOR flash memory with the NAND flash memory in the embodiment of the present invention, several configurations must be added.

First, when the initial power of the mobile terminal is supplied, the modem should be able to randomly access the basic code (vector table, boot code, load code) for initial setting. In the conventional NOR flash memory, random access is possible, and the basic code may be stored in the NOR flash memory. However, since the NAND flash memory according to the embodiment of the present invention cannot be randomly accessed, a separate configuration capable of random access of the basic code is required.

Secondly, a separate configuration is required to control the NAND flash memory according to a command from the modem so that a modem can access the NAND flash memory and inform the modem of the control state of the NAND flash memory. do.

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2 is a diagram illustrating an interface device between a modem and a memory in a mobile terminal according to an exemplary embodiment of the present invention. First, as shown in FIG. 2, a configuration according to an exemplary embodiment of the present invention is largely used to interface data between the modem 210, the memory unit 230, and the modem 210 and the memory unit 230. The interface unit 220 is divided.

Referring to FIG. 2, the interface unit 220 may include a memory controller (NAND Flash Control Block, hereinafter referred to as an “NFC unit”) 222, a mask ROM 224, and an error correcting code generator. Error Correction Code Block, hereinafter referred to as " ECC unit " The mask ROM 224 may be randomly accessed by the modem 210. Thus, the mask ROM 224 stores basic data (vector table, boot code, load code) required for initial operation, and allows the basic data to be randomly accessed by the modem 210. The vector data, the boot code, the load code, and the like, which are basic data required for the initial operation, are program data for copying necessary data from the NAND flash memory 232 to a working memory.

The ECC unit 226 inputs data transmitted between the modem 210 and the memory unit 230, and parity codes ECCDATAL [7: 0], ECCDATAH [7: 0], and ECCDATAX for the input data. [7; 0]). Thus, by providing the parity code to the modem 210, bit error checking and correction on the data is performed. That is, the mask ROM 224 is enabled by the enable signal ROM1_CSB from the modem 210 and read out by the predetermined address signal A [13: 1] from the modem 210. The data D [15: 0] is output to the modem 210. The NFC unit 222 controls the memory unit 230 to allow the modem 210 to write data to the memory unit 230 or to read data from the memory unit 230. do. That is, the NFC unit 220 inputs commands (ROM2_CSB, GP_CSB, WRB, RDB) from the modem 210, and controls the memory unit 230 by the input command (NFROM_CSB, CLE, ALE). , NAND_WRB, NAND_RDB) to perform the operation required by the modem 210. On the other hand, the NFC unit 220 includes a function for checking the current control state of the memory unit 230 and informs the modem 210. Meanwhile, the NFC unit 222 interfaces the parity code so that the modem 210 can read the parity code generated from the ECC unit 226.                     

The memory unit 230 includes a NAND flash memory 232 and a working memory 234. The NAND flash memory 232 records or reads the corresponding data under control from the memory controller 222. The working memory 234 temporarily stores data provided from the modem 210 to enable fast data access from the modem 210.

Next, in FIG. 2, the signals shown based on the interface unit 220 are defined.

First, when signals input to the interface unit 220 are defined, the ROM1_CSB is a chip select signal that enables the mask ROM 224 to be accessed. The ROM2_CSB is a chip select signal input to the NFC unit 222 and enabled when the NFC unit 222 accesses the ECC unit 226, the NAND flash memory 232, or the work memory 234. GP_CSB is a chip select signal input to the NFC unit 222 and enabled when the NFC unit 222 accesses the ECC unit 226 and the NAND flash memory 232. GP_CSB_OUT is a chip select signal, and A [13: 1] is an address bus signal. Read Enable signal (RDB) is a modem 210 is enabled to read data from an external chip, that is, the NAND flash memory 230, working memory 234, ECC unit 226, NFC unit 222 It is a signal. Write enable signal (WRB) is enabled for the modem 210 to write data to an external chip, that is, the NAND flash memory 230, the working memory 234, the ECC unit 226, and the NFC unit 222. Signal. D [15: 0] is a data bus signal.                     

Next, when signals output from the interface unit 220 are defined, an address latch enable signal (ALE) is a signal that enables writing of an address value to a data bus when the NAND flash memory 232 is accessed. The command latch enable signal (CLE) is a signal that enables to write a command value to the data bus when the NAND flash memory 232 is accessed. The command value is any value that can be defined according to the NAND flash memory. NFROM_CSB is a chip select signal that the memory controller 222 enables to access the NAND flash memory 232. NAND_WRB is a signal that is enabled when the NFC unit 222 attempts to write data to the NAND flash memory 232. NAND_RDB is a signal that is enabled when the NFC unit 222 tries to read data from the NAND flash memory 232.

On the other hand, when the internal signals of the interface unit 220 are defined, ECC_START is a signal that enables the ECC unit 226 so that the NFC unit 222 generates a parity code corresponding to the corresponding data. ECC_RCE is a chip select signal that enables the parity code to be read at the request of the NFC unit 222. ECCDATAL [7: 0], ECCDATAH [7: 0], and ECCDATAX [7: 0] are signals in which a parity code generated from the ECC unit 226 is output at the request of the NFC unit 222. to be.

If the other signals are defined, the RBB is a signal indicating the state of the NAND flash memory 232 and indicates whether it is in a ready state or a busy state. The modem 210 may not access data when the NAND flash memory 232 is in a busy state, and may only access data when the NAND flash memory 232 is in a busy state. The modem 210 checks the current state of the NAND flash memory 232 by the RBB input through GPIO_INT. The GPIO_INT is a general purpose input output pin for the modem 210 to interface with external components. RAM_CSB is a chip select signal enabled when the working memory 234 is accessed from the modem 210. The RAM_CSB may be used by connecting the ROM2_CSB to the RAM_CSB when the ROM2_CSB does not access the NAND flash memory 232.

When the mobile terminal having the configuration as described above is supplied with the initial operation power, basic codes (Vector Table, Boot Code, and Load Code) for initial setting are stored in the mask ROM 224. Therefore, when the initial operating power is supplied, the modem 210 reads data corresponding to the basic code stored in the mask ROM and performs booting. On the other hand, the modem 210 of the mobile terminal after the initial setting, the operating code (OS code) and call processing software (Call S / W) is read from the NAND flash memory 232 and copied to the working memory 234, Thereafter, the working memory 234 is accessed and driven. The reason why the modem 210 copies data from the NAND flash memory 232 to the working memory 234 is that the access time of the working memory 234 using SRAM is short. In other words, the necessary data can be accessed quickly. Meanwhile, the modem 210 may read or write various application data directly from the NAND flash memory 232, but may copy and access the application data to the working memory 234 as needed.

3 is a diagram illustrating a detailed configuration of the memory controller 222 of FIG. 2.

Referring to FIG. 3, when the chip enable signals GP_CSB and WRB are enabled from the modem 210 and a specific address value d and a specific data value are recorded in the address signal A and the data signal D, Q0, Control Q1, Q2, Q3. At this time, Q3 of the first resist group is a mux select signal (Mux_Select). When this value is '0', the CLE, ALE, NFROM_CSB, NAND_WRB, NAND_RDB, and ECC unit 226 controlling the NAND flash memory 232 is controlled. ECC_RCE to be controlled by the first combination logic and the first resist group. On the other hand, when Q3 of the first resist group is '1', CLE, ALE, NFROM_CSB, NAND_WRB, NAND_RDB for controlling the NAND flash memory 232, and ECC_RCE for controlling the ECC unit 226 may be combined with the second combination logic. 2 controlled by a group of resists. That is, the NAND flash memory 232 and the ECC unit 226 may be controlled by using a first combination logic and a first resist group or by using a second combination logic and a second resist group.

Hereinafter, an operation according to an embodiment of the present invention will be described with reference to the configuration described with reference to FIGS. 2 and 3 as follows. First, an operation according to an exemplary embodiment of the present disclosure may be roughly divided into an operation of writing data to an NAND flash memory 232 and an operation of reading data. Therefore, the operation according to the embodiment of the present invention to be described below will be divided into an operation of writing data to the NAND flash memory 232 and an operation of reading data.

4 is a diagram illustrating a control flow performed by the memory controller 222 constituting the interface unit 220 to write data to the NAND flash memory 232. 5 is a diagram illustrating a control flow performed by the memory controller 222 to read data from the NAND flash memory 232.

First, referring to FIG. 4, when the memory controller 222 writes data to the NAND flash memory 232 according to an exemplary embodiment of the present disclosure, the NFC unit 222 performs a modem in step 410. A data write request from 210 to the NAND flash memory 232 is sensed. The data write request to the NAND flash memory 232 can be detected by the address signal A and the data signal D, WRB, the chip enable signal GP_CSB or ROM2_CSB from the modem 210 by the detailed description of FIG. 3 described above. have.

When the NFC unit 222 detects the data write request, the NFC unit 222 proceeds to step 412 and issues a command to write data to NFROM_CSB, which is a chip select signal for accessing the NAND flash memory 232, and the NAND flash memory 232. Enable CLE to transmit. The NAND flash memory 232 is enabled by the NFROM_CSB, and prepares to receive a command from the NFC unit 222 by the CLE. In step 414, the NFC unit 222 transmits a write request command 80H requesting to record data as a data bus signal D [7: 0] transmitted through the data bus. The NAND flash memory 232 receives a write request command from the NFC unit 222 and waits for receiving an address to write data and data to be written. In operation 416, the NFC unit 222 disables the CLE enabled to transmit the write request command, and provides an address with an NFROM_CSB, which is a chip select signal for accessing the NAND flash memory 232. Enable ALE as an enable signal for transmission. By enabling the ALE, the NAND flash memory 232 waits for an address transmission from the NFC unit 222.

In step 418, the NFC unit 222 transmits an address to record data as the data bus signal D [7: 0]. The NFC unit 222 transmitting the address proceeds to step 420 to disable the ALE enabled to transmit the address, and enables ECC_START of the ECC unit 226 to generate a parity code.

Meanwhile, the modem 210 transmits data to be recorded as the data bus signal D [15: 0]. The transmitted data is provided to the NAND flash memory 232 and written to the designated address. In addition, the transmitted data is provided to the ECC unit 226, and the ECC unit 226 corresponds to parity codes ECDATAL [7: 0], ECDATAH [7: 0], and ECDATAX [7: corresponding to the received data. 0].

The modem 210 enables the ECC_RCE of the ECC unit 226 through the NFC unit 222 to enable the parity codes ECCDATAL [7: 0] and ECCDATAH generated by the ECC unit 226. Read [7: 0], ECCDATAX [7: 0]. The modem 210 that reads the parity code through the NFC unit 222 disables the ECC_START through the NFC unit 222 in step 424 and uses the read parity code as the NAND flash memory 232. Enable the NFROM_CSB to write In step 426, the modem 210 transmits the parity code to the data bus signal D [7: 0]. The transmitted parity code is provided to the NAND flash memory 232 and stored in a predetermined area.

On the other hand, the NFC unit 222 proceeds to step 428 to enable the CLE, and in step 430 a confirmation command (10H) for confirming whether or not the recording of the data is normally performed in the data bus signal D [7: 0]. The NFC unit 222 transmits the confirmation command 10H and proceeds to step 432 to disable the CLE.

The NAND flash memory 232 transmits its current state to D [6] of the data bus signals D [7: 0] upon receiving the confirmation command 10H. The current state may be divided into a busy state and a ready state. Meanwhile, the NAND flash memory 232 always reports its current state through the RBB even if the NAND flash memory 232 is not received. That is, the modem 210 may know the current state of the NAND flash memory 232 through the RBB. In addition, the NAND flash memory 232 reports whether the writing of the data is normally performed through the D [0] of the data bus signals D [7: 0].

In operation 434, the modem 210 determines whether the NAND flash memory 232 is in a standby state based on a current state reported by the data bus signal D [6] or RBB from the NAND flash memory 232. If the determination determines that the NAND flash memory 232 is in the standby state, the process proceeds to step 436. The modem 210 proceeds to step 436 and determines whether an error has occurred in writing the data based on the information provided from the NAND flash memory 232 to D [0]. If it is determined by the determination that the data has been normally recorded, the NFROM_CSB is disabled and the above operation for recording is terminated. However, if it is determined that the data is not normally recorded, the NFROM_CSB is disabled and the process returns to step 410 to perform the above-described operation again.

Next, referring to FIG. 5, when the memory controller 222 reads data from the NAND flash memory 232 according to an embodiment of the present disclosure, the NFC unit 222 may proceed to step 510. The modem 210 senses a data read request from the NAND flash memory 232. The data read request from the NAND flash memory 232 may be detected by the address signal A and the data signal D, the RDB, the chip enable signal GP_CSB or ROM2_CSB from the modem 210 according to the detailed description of FIG. 3. Can be.

When the NFC unit 222 detects the data read request, the NFC unit 222 proceeds to step 512 and reads data from the NFROM_CSB, which is a chip select signal for accessing the NAND flash memory 232, and the NAND flash memory 232. Enable CLE to send. The NAND flash memory 232 is enabled by the NFROM_CSB, and prepares to receive a command from the NFC unit 222 by the CLE. In step 514, the NFC unit 222 transmits a read request command (00H) requesting data read as a data bus signal D [7: 0]. The NAND flash memory 232 receives a read request command from the NFC unit 222 and waits for an address to read data. On the other hand, the NFC unit 222 proceeds to step 516 to disable the CLE enabled to transmit the write request command, and to enable the ALE as an enable signal for transmitting the address. By enabling the ALE, the NAND flash memory 232 waits for an address transmission from the NFC unit 222.

In step 518, the NFC unit 222 transmits an address for reading data to the data bus signal D [7: 0]. The NFC unit 222 transmitting the address proceeds to step 520 to disable the ALE that has been enabled to transmit the address. The NAND flash memory 232 transmits its current state to D [6] or RBB of the data bus signals D [7: 0] upon receiving the read request command 00H and the address. The current state may be divided into a busy state and a ready state. When the current state of the NAND flash memory 232 is in the standby state, the NAND flash memory 232 reads the data written corresponding to the provided address and transmits the data through the data bus signal D [7: 0].

In operation 524, the modem 210 determines whether the NAND flash memory 232 is in a standby state based on the current state reported by the data bus signal D [6] or RBB from the NAND flash memory 232. If the determination determines that the NAND flash memory 232 is in the standby state, the process proceeds to step 524. In step 524, the NFC unit 222 enables ECC_START to generate a parity code corresponding to the data read and transmitted by the NAND flash memory 232. The ECC unit 226 inputs the read data and generates parity codes ECCDATAL [7: 0], ECCDATAH [7: 0], and ECCDATAX [7: 0] in response to the read data.

The modem 210 reads the parity code generated by the ECC unit 226 by enabling the ECC_RCE of the ECC unit 226 in step 526 through the NFC unit 222 and proceeds to step 528. By disabling the ECC_START through the NFC unit 222. The modem 210 reads a parity code recorded in the NAND flash memory 232 in response to the read data in step 530 through the NFC unit 222. The modem 210 reads the recorded parity code and proceeds to step 532 to disable the NFROM_CSB.

The modem 210 which reads the generated parity code and the recorded parity code through the NFC unit 222 proceeds to step 534 and compares the two parity codes. The modem 210 determines whether an error has occurred in the read data based on the comparison result in step 536. The determination of the occurrence of the error is determined by whether the generated parity code matches the recorded parity code. If the generated parity code and the recorded parity code do not match, the modem 210 determines that an error has occurred in the read data. Otherwise, if the generated parity code and the recorded parity code match, it is determined that no error has occurred in the read data.

If it is determined in step 536 that an error has occurred, the modem 210 terminates the series of operations for reading the aforementioned data. However, if it is determined in step 536 that an error has occurred, the modem 210 performs a correcting operation on the bits in which the error occurs in step 538 and then ends the series of operations for reading the aforementioned data.

As described above, in the embodiment of the present invention, when data is written to the NAND flash memory 232, data to be actually written is written to the data area of the NAND flash memory 232. At this time, the ECC unit 226 receives the recorded data as an input and outputs the parity codes ECCDATAL [7: 0], ECCDATAH [7: 0], and ECCDATAX [7: 0] corresponding to the data as output values. do. The modem 210 records the parity code output from the ECC unit 226 in the NAND flash memory 232. Meanwhile, when the modem 210 reads data in the NAND flash memory 232, output data from the NAND flash memory 232 is applied as an input of the ECC unit 226, and the ECC unit ( 226 generates a new parity code for the applied data. The modem 210 compares the new parity code with the parity code stored in the area for parity storage of the NAND flash memory. The modem 210 checks whether there is an error bit through the comparison, and corrects the bit error if there is a bit error.

Meanwhile, as described above, the modem 210 accesses the mask ROM 224 when the initial power supply is performed, and reads basic codes to perform an initialization process.

Referring to FIG. 2, the initialization operation by the modem 210 enables the chip selection signal ROM1_CSB to access the mask ROM 224 when the initial power is supplied. The mask ROM 224 is enabled by the ROM1_CSB to wait for a request from the modem 210. The modem 210 provides the address where the basic data is stored to the mask ROM 224 as an address bus signal A [13: 1]. The mask ROM 224, having received the predetermined address with the address bus signal A [13: 1], reads a stored basic code corresponding to the predetermined address, and stores the read basic code as a data bus signal D [15:]. 0]. The modem 210 performs an initialization operation by the read basic code transmitted through the data bus signal D [15: 0].

In addition, as described above, the modem 210 copies the read data to the work memory 234 for quick access in using the data read from the NAND flash memory 232, and the work memory 234. ) To use the copied data.

Referring to FIG. 2, the operation of accessing the working memory 234 by the modem 210 enables the modem 210 to enable the chip select signal RAM_CSB for accessing the working memory 234. As described above, when the modem 210 does not access the NAND flash memory by the ROM2_CSB, the ROM 210 may be connected to the RAM_CSB. The working memory 234 is activated by the RAM_CSB to wait for a command from the modem 210. The modem 210 enables the WRB to copy the operation code, the call processing software, etc. read from the NAND flash memory 232 to the working memory 234. However, in order to read the operation code, the call processing software, etc. recorded in the working memory 234, the RDB is enabled. Meanwhile, the WRB enabled by the modem 210 is provided to the OE terminal of the working memory 234, and the RDB is provided to the WE terminal of the working memory 234. The working memory 234 waits for input of a predetermined address and data to be copied (operation code, call processing software, etc.) from the modem 210 when the OE terminal is enabled. The working memory 234 receives a predetermined address from the modem 210 as an address bus signal [21: 1], and provides data (operation code, call processing software, etc.) as the data bus signal D [15: 0]. Is written corresponding to the predetermined address.

Meanwhile, the working memory 234 waits for input of a predetermined address from the modem 210 when the WE terminal is enabled after being activated by the modem 210. When the work memory 234 receives a predetermined address from the modem 210 as an address bus signal [21: 1], the working memory 234 reads data (operation code, call processing software, etc.) recorded corresponding to the provided predetermined address. By transmitting the data bus signal D [15: 0], the modem 210 can receive the data.

3 is a diagram illustrating a detailed configuration of a memory controller (NFC unit) 222 of the components shown in FIG. As shown in FIG. 3, the NFC unit 222 inputs signals A [13: 0], D [15: 0], GP_CSB, WRB, RDB, and ROM2_CSB applied from the modem 210. As a result, the signals CLE, ALE, ECC_RCE, NFROM_CSB, GP_CSB_OUT, NAND_WRB, and NAND_RDB are outputted to the NAND flash memory 232.

Referring to FIG. 3, a signal output by a logic sum gate using the GP_CSB and the WRB as inputs is input to a first resist group clock CK. The first resist group outputs a mux select signal Mux_Select through Q3 among the four output terminals Q0 to Q3 to be used as an enable signal of MUXs muxing CLE, ALE, ECC_RCE, NFROM_CSB, NAND_WRB, and NAND_RDB, respectively. do. On the other hand, the first resist group is a CLE, ALE when a specific data value enters a specific address using a first combination logic (Combinational Logic) that is input to the A [13: 0] and the D [15: 0] , ECC_RCE, NFROM_CSB can be controlled easily. In addition, signals of A [10], A [11], A [12], A [13], and GP_CSB are input to the second combination logic. The second combination logic generates CLE, ALE, ECC_RCE, and NFROM_CSB using the signals. GP_CSB_OUT is a GP_CSB output from a modem, which is used as an interface signal for a NAND flash memory or an LCD module (not shown). Therefore, GP_CSB is enabled, and when both A [10] and A [13] are '1', the GP_CSB is enabled and configured to be used as another chip select signal (not shown). It was.

FIG. 6 is a diagram illustrating a configuration of some of the combination logic illustrated in FIG. 3. Next, the configuration of the combination logic according to the present invention will be described in detail with reference to FIG. 6.                     

First, the combination logic consists of a flip-flop (F / F). Next, the configuration and connection relationship of the combination logic will be described. The first inverting gate NOT1 inverts the input of the twelfth address signal A12, which is one of the address signals, and outputs it. The output of the first inverted gate NOT1 and the GP_CSB signal, which is a chip select signal, are input to the first logical sum operator OR1. The first logical sum operator OR1 performs a logical sum of the two input signals and outputs the result to the third logical sum operator OR3. The third logical sum operator OR3 receives the output signal and the write signal WRB of the first logical sum operator OR1, and outputs the result of the logical sum. The output of the third logical sum operator OR3 is input to the clock signal MSM_CLK of the resist group.

The second inverting gate NOT2 receives the thirteenth address signal A13, which is one of the address signals, as an input, inverts it, and outputs the inverted gate. The output of the second inversion gate NOT2 and the GP_CBS signal, which is the chip select signal, are input to the second logical sum operator OR2. The second logical sum operator OR2 performs a logical sum of the two input signals and outputs the result to the fourth logical sum operator OR3 and the fifth logical sum operator OR5. The fourth logical sum operator OR5 receives and outputs the output signal and the write signal WRB of the second logical sum operator OR2 and outputs the logical sum. The output of the fourth logical sum operator OR4 is output as an MSM_NAND_WRB signal, which is a write signal of the NAND flash memory. In addition, the output of the fifth logical sum operator OR5 receives a read enable signal RDB signal and an output signal of the second logical sum operator OR2 and outputs the result as an MSM_NAND_RDB signal that is a read signal of a NAND flash memory. .

In the case of the combination logic configured as described above, the timing of reading and writing may be illustrated in FIG. 7. 7 is a timing diagram of each signal when the combination logic according to the present invention is configured as shown in FIG. 6. Next, the timing of the read and write signals will be described with reference to FIG. 7.

When writing data is required, the signal of GP_CSB is first enabled at the time t0. The WRD signal is then enabled low by one clock, starting at the falling edge of t1. This may be the case when the process proceeds from step 410 to step 412 of FIG. 4 or to step 512 from step 510 of FIG. That is, since GP_CSB and WRB are enabled, the condition of step 410 or step 510 is satisfied. In this manner, when the enable signal according to the recording is received, the command latch enable (CLE) signal is high enabled at a time t2, and the BFROM_CSB signal is transitioned low to enable. That is, step 412 or 512 is performed. Thereafter, a read command (Read Cmd) or a write command (Write Cmd) is output between the polling edge at time t1 and the polling edge at t7 as the interface (I / O) output. As such, the read or write command corresponds to step 414 of FIG. 4 or step 514 of FIG. 5. After the read command or the write command is output, both the CLE and ALE signals that enable the transmission of the command are disabled at the falling edge of t7.

As described above, when the command is transmitted, an address for reading or writing is then output. Therefore, when all addresses are transmitted, the error correction code generator 226 must be activated before data can be recorded or read. This is because, as described above, the NAND flash memory has a high probability of an error occurring when reading and writing data.                     

Next, the start command time point of the error correction code generator 226 will be described. The GP_CSB signal is activated at the rising edge of t18 to transmit a start command to the error correction code generator 226. The WRB signal is then enabled at the falling edge of t19. Therefore, the CSB signal NFRON_CSB of the NAND flash memory transitions high at the falling edge of t19, and the ECC_RCE transitions low. This allows data to be read from the ECC. That is, the ECC start command is transmitted between the time t20 and the time t25. Thereafter, a read or write command of the data is performed.

As can be seen in FIG. 7, two clocks before the command signal is transmitted and two clocks are lost after the command signal is transmitted. It generates WR_CLK using the twelfth address signal [A12], which is one of the address signals, and the GP_CSB signal, and then WR_CLK acts as a clock of the flip-flop to generate ALE, CLE, NFROM_CSB and ECC_RCE according to the received data value. Because. The thirteenth address signal [A13] and GP_CSB generate NAND_WEB and NAND_REB. As a result, two clocks are lost before and after each command is delivered.

8 is a detailed circuit diagram illustrating a combination logic according to another embodiment of the present invention. Hereinafter, a circuit configuration and connection relationship of the combination logic according to the present invention will be described in detail with reference to FIG. 8.

The GP_CSB signal is input to the first logical sum gate OR1, the second logical sum gate OR2, and the second inversion gate NOT2. The second inversion gate NOT2 inverts the GP_CSB signal and outputs the inverted GP_CSB signal to the first logical gate AND1 and the second logical gate AND2. The first logical gate AND1 receives the twelfth address signal A12 and outputs a signal multiplied by the output of the second inverting gate NOT2 to MCP_NAND_CLE. The second logical gate AND2 performs an AND operation on the eleventh address signal A11 and the output signal of the second logical gate AND2 and outputs the result as MCP_NAND_CLE.

The first inverting gate NOT1 inverts the thirteenth address signal A13 and outputs it to one input of the first logical sum gate OR1. The other input becomes the signal of the GP_CSB as described above. Accordingly, the first logical sum gate OR1 outputs a NAND_CSB signal by ORing two signals. As described above, the second logic gate OR2 uses the GP_CSB signal as one input, and the other input signal is a signal obtained by inverting the tenth address signal A10 by the third inversion gate NOT3. Therefore, the second logical sum gate OR2 performs an OR over the two input signals and outputs the ECC_RCE signal.

The combination logic having the configuration as described above has a timing diagram as shown in FIG. 9 is a timing diagram of a signal input to an error correction code generation unit when the combination logic according to the second embodiment of the present invention is performed.

As shown in FIG. 9, in contrast to FIG. 7, a delay of 2 clocks does not occur before and after the command signal in the timing diagram. This is based on the nature of the GP_CSB signal. ECC_RCE is the GP_CSB signal, the tenth address signal [A10], the GP_CSB signal, the eleventh address signal [A11], the GP_CSB signal, the twelfth address signal [A12], and the GP_CSB signal and the thirteenth address signal [A13], respectively. This is because it generates ALE, CLE, and NAND_CSB. This is because the flip-flop is not used as in the first embodiment.

As described above, the present invention reduces the price of a mobile terminal by replacing the memory of the mobile terminal with an exclusive-OR gate flash memory capable of a high-capacity and low price in an exclusive-OR flash memory that is burdened with price, capacity, supply and purchase. Not only that, but it can also improve performance.

Claims (18)

An apparatus for interfacing data between an exclusive-OR flash memory for storing data and a modem for processing data for writing to the exclusive-OR flash memory, A work memory having a capacity smaller than that of the exclusive AND flash memory, copying partial information of the information stored in the exclusive AND logic memory, and storing a second address different from the first address of the exclusive AND logic flash memory. Wow, A programmable memory having basic data required for copying some of the information stored in the exclusive AND flash memory into the working memory; And a controller connected to the programmable memory and configured to control to randomly read the partial information stored in the working memory with the second second address. The method of claim 1, The controller reads the basic data from the programmable memory during initial operation, and controls copying of the partial information stored in the exclusive logical product flash memory to the working memory. Interface device. The method of claim 1, And an error correction code generator for generating an error correction code of the data and outputting the data to the controller when the data is written to or read from the exclusive logical product flash memory. The method of claim 3, The controller controls the error correction code generation unit to control the generation of the error correction code of the data when the data is written, and to store the generated error correction code in the exclusive logical product flash memory in a second address different from the data. Interface device between the modem and the memory in the mobile terminal characterized in that the control. The method of claim 3, wherein the controller, When the data is read, the error correction code generation unit is controlled to control generation of an error correction code of data, the error correction code stored in another second address is read from the data into the exclusive logical AND flash memory, and the error correction code The interface device between the modem and the memory in the mobile terminal, characterized in that for detecting the presence or absence of the error of the read data by comparing with the error correction code generated by the generation unit. The method of claim 1, And the basic data comprises a vector table, a boot code, and a load code. An apparatus for interfacing data between an exclusive-OR flash memory for storing data and a modem for processing data for writing to the exclusive-OR flash memory, A memory control unit controlling an error correction code written in the exclusive AND memory flash memory and data received from the modem when a chip select signal and a write command are enabled; A mask ROM activated by the modem and outputting a basic code required for initialization upon receipt of a read command from the modem when initial power is supplied to the mobile terminal; And an error correction code generator which is activated by control from the memory controller and generates an error correction code corresponding to the data from the modem and provides the error correction code to the modem through the memory controller. Interface device between modem and memory. The interface device of claim 7, wherein the error correction code generator is activated by control from the memory controller and provided to the modem through the memory controller. The method of claim 7, wherein And a working memory which is activated by the modem and receives some of the data stored in the exclusive AND memory requiring fast access, and outputs the data to the modem under the control of the memory controller. Interface device between the modem and the memory in the mobile terminal. A method of interfacing data between an exclusive logical AND flash memory and a modem in a mobile terminal having an exclusive logical AND flash memory for storing data and a modem for processing data recorded in the exclusive logical OR flash memory, When the first chip select signal and the write command are enabled by the modem, the second chip select signal and the command latch enable signal for activating the exclusive AND flash memory are enabled to enable the write command to perform the exclusive AND flash. Transfer to memory, Disabling the command latch enable signal, enabling the address latch enable signal to transmit a write address, and writing data output from the modem to the exclusive AND logic flash memory; And disabling the second chip selection signal. The method of claim 10, Before disabling the second chip select signal for activating the exclusive AND flash memory, the command latch enable signal is output to transmit a confirmation command, and then the current state of the exclusive AND flash memory and the written data are normal. And a step of checking whether or not it is recorded. An exclusive-OR flash memory for storing data, a modem for processing data recorded from the exclusive-OR flash memory, and an error correction code generation unit for generating an error correction code corresponding to the data recorded from the exclusive-OR flash memory. In the mobile terminal to interface the data between the exclusive logical AND flash memory and the modem, When the first chip select signal and the read command are enabled by the modem, the second chip select signal and the command latch enable signal for activating the exclusive AND flash memory are enabled, thereby reading the read command from the exclusive AND logic flash. Transfer to memory, Disable the command latch enable signal, enable the address latch enable signal, and send a read address to the exclusive AND logic memory; Reading data with an error correction code and a read address of the corresponding data; Generating an error correction code corresponding to the data from the error correction code generator by disabling the address latch enable signal and the third chip select signal; Comparing the generated error correction code with a read error correction code to determine whether an error occurs in the read data; And performing error correction on the read data when it is determined that the error has occurred. An exclusive AND flash memory for storing data, a programmable memory having basic data for initializing from the exclusive AND flash memory, a working memory having a different address from the exclusive AND flash memory, and the exclusive AND flash A method for interfacing data between the exclusive logical AND flash memory and the modem in a mobile terminal having a modem for processing data read from a memory, the method comprising: Initializing a modem based on basic data from the programmable memory; And reading out data from the exclusive AND flash memory based on the basic data, and writing the read data to the working memory. The method of claim 13, When the chip select signal and the write command are enabled by the modem, the chip select signal and the command latch enable signal for activating the exclusive AND flash memory are enabled, and the write command is transmitted to the exclusive AND flash memory. Process, Disabling the command latch enable signal, enabling the address latch enable signal, transmitting an address to which data is written from a modem to the exclusive logical AND flash memory, and writing data output from the modem; And disabling a second chip select signal for activating the exclusive logical AND flash memory. The method of claim 13, When the chip select signal and the read command are enabled by the modem, the read command is transmitted to the exclusive AND flash memory, and the chip select signal and the command latch enable signal for activating the exclusive AND flash memory are enabled. And activating the data to read the data. The method of claim 14, Enabling the chip select signal and the command latch enable signal to receive the data, and receiving an error correction code corresponding to the data of the modem from the error correction code generator; Enable the chip select signal for activating the exclusive AND logic memory, disable the chip select signal for error correction, transmit the error correction code to the exclusive AND logic memory, and write the data The method of the interface between the modem and the memory in the mobile terminal, characterized in that it further comprises the step of. The method of claim 16, When the chip select signal and the read command are enabled by the modem, the chip select signal and the command latch enable signal for activating the exclusive AND flash memory are enabled, and the read command is transferred to the exclusive AND flash memory. The method of the interface between the modem and the memory in the mobile terminal further comprising the step of transmitting. The method of claim 17, When the data is read, disabling the instruction latch enable signal, enabling the address latch enable signal, and reading the error correction code and data corresponding to the data by the exclusive AND logic flash memory; , Disabling the address latch enable signal and enabling the chip select signal to receive an error correction code corresponding to the read data from the error correction code generator; Disabling the chip select signal and comparing an error correction code of the error correction code generator with an error correction code of the read data to determine whether an error of the read data occurs; And performing error correction on the read data when it is determined that the error has occurred.

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