CA2424855A1 - Cascade low-pass filter to improve xdsl band attenuation for pots splitter - Google Patents
Cascade low-pass filter to improve xdsl band attenuation for pots splitter Download PDFInfo
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Abstract
Cascade low-pass filters are useful in attenuating the xDSL band in a POTS
splitter. The design of the low-pass filter is a sixth-order filter having two stages. A first stage includes a fourth-order filter, preferably with a stop-band frequency of approximately 48 kHz. A second stage includes a second-order filter in cascade with the fourth-order filter. For this filter, the stop-band frequency is preferably approximately 29 kHz. The inductance value of the second stage is relatively small in comparison to the inductance values of the first stage. In this manner, improvements in xDSL band attenuation are facilitated with little or no eroding of the voice band performance such as insertion loss, pass-band attenuation and return loss.
splitter. The design of the low-pass filter is a sixth-order filter having two stages. A first stage includes a fourth-order filter, preferably with a stop-band frequency of approximately 48 kHz. A second stage includes a second-order filter in cascade with the fourth-order filter. For this filter, the stop-band frequency is preferably approximately 29 kHz. The inductance value of the second stage is relatively small in comparison to the inductance values of the first stage. In this manner, improvements in xDSL band attenuation are facilitated with little or no eroding of the voice band performance such as insertion loss, pass-band attenuation and return loss.
Claims (40)
1. A low-pass filter, comprising:
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
first and second resistors in parallel with the first differential mode inductor;
first and second capacitors in parallel with the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor;
a first shunt leg interposed between the first and second differential mode inductors and coupled across the first and second differential mode inductors;
a second shunt leg interposed between the second and third differential mode inductors and coupled across the second and third differential mode inductors; and a third shunt leg coupled across the third differential mode inductor.
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
first and second resistors in parallel with the first differential mode inductor;
first and second capacitors in parallel with the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor;
a first shunt leg interposed between the first and second differential mode inductors and coupled across the first and second differential mode inductors;
a second shunt leg interposed between the second and third differential mode inductors and coupled across the second and third differential mode inductors; and a third shunt leg coupled across the third differential mode inductor.
2. The low-pass filter of claim 1, wherein the low-pass filter is a passive low-pass filter.
3. The low-pass filter of claim 1, wherein the first resistor and the second resistor have substantially the same resistance.
4. The low-pass filter of claim 1, wherein the first capacitor and the second capacitor have substantially the same capacitance.
5. The low-pass filter of claim 1, wherein the third capacitor and the fourth capacitor have substantially the same capacitance.
6. The low-pass filter of claim 1, wherein the first and second capacitors each have capacitance values of approximately one order of magnitude less than capacitance values of the third and fourth capacitors.
7. The low-pass filter of claim 1, wherein the first inductor has an inductance value greater than an inductance value of the second inductor and the second inductor has an inductance value greater than the inductance value of the third inductor.
8. The low-pass filter of claim 7, wherein the third inductor has an inductance value of less than half of the inductance value of the second inductor.
9. The low-pass filter of claim 7, wherein the third inductor has an inductance value of less than approximately 30% of the inductance value of the second inductor.
10. The low-pass filter of claim 7, wherein the first inductor has an inductance value of approximately 21 mH, the second inductor has an inductance value of approximately 10 mH, and the third inductor has an inductance value of approximately 2.8 mH.
11. The low-pass filter of claim 10, wherein the first and second capacitors each have capacitance values of approximately 0.002 µF, and the third and fourth capacitors each have capacitance values of approximately 0.02 µF.
12. The low-pass filter of claim 1, wherein the first shunt leg further comprises a fifth capacitor, the second shunt leg further comprises an sixth capacitor and the third shunt leg further comprises a seventh capacitor.
13. The low-pass filter of claim 12, wherein the first shunt leg further comprises a third resistor in series with the fifth capacitor.
14. The low-pass filter of claim 13, further comprising:
an eighth capacitor in parallel with the first resistor;
a ninth capacitor in parallel with the second resistor;
a fourth resistor in parallel with the first capacitor; and
an eighth capacitor in parallel with the first resistor;
a ninth capacitor in parallel with the second resistor;
a fourth resistor in parallel with the first capacitor; and
15 a fifth resistor in parallel with the second capacitor.
15. The low-pass filter of claim 14, wherein the eighth and ninth capacitors have substantially the same capacitance and wherein the fourth and fifth resistors have substantially the same resistance.
15. The low-pass filter of claim 14, wherein the eighth and ninth capacitors have substantially the same capacitance and wherein the fourth and fifth resistors have substantially the same resistance.
16. The low-pass filter of claim 15, wherein the eighth and ninth capacitors each have capacitance values of approximately one order of magnitude less than the capacitance values of the first and second capacitors.
17. The low-pass filter of claim 16, wherein the fourth and fifth resistors each have resistance values greater than the resistance values of the first and second resistors.
18. The low-pass filter of claim 17, wherein the second shunt leg further comprises a sixth resistor in series with the sixth capacitor and wherein the third shunt leg further comprises a seventh resistor in series with the seventh capacitor.
19. A low-pass filter, comprising:
a first differential mode inductor in series with a second differential mode inductor, wherein the first differential mode inductor has an inductance value of approximately 21 mH and wherein the second differential mode inductor has an inductance value of approximately 10 mH;
a third differential mode inductor in series with the second differential mode inductor, wherein the third differential mode inductor has an inductance value of approximately 2.8 mH;
first and second resistors in parallel with the first differential mode inductor, wherein the first and second resistors each have a resistance value of approximately 2.37 k.OMEGA.;
first and second capacitors in parallel with the second differential mode inductor, wherein the first and second capacitors each have a capacitance value of approximately 0.0022 µF;
third and fourth capacitors in parallel with the third differential mode inductor, wherein the third and fourth capacitors each have a capacitance value of approximately 0.022 µF;
a first shunt leg interposed between the first and second differential mode inductors and coupled across a first and second winding of the first differential mode inductor, wherein the first shunt leg comprises a fifth capacitor having a capacitance value of approximately 0.022 µF and a third resistor coupled in series with the fifth capacitor and having a resistance value of approximately 51.1 .OMEGA.;
a second shunt leg interposed between the second and third differential mode inductors and coupled across a first and second winding of the second differential mode inductor, wherein the second shunt leg comprises a sixth capacitor having a capacitance value of approximately 0.036 µF; and a third shunt leg coupled across a first and second winding of the third differential mode inductor, wherein the third shunt leg comprises a seventh capacitor having a capacitance value of approximately 0.01 µF;
wherein the third differential mode inductor is interposed between the second shunt leg and the third shunt leg.
a first differential mode inductor in series with a second differential mode inductor, wherein the first differential mode inductor has an inductance value of approximately 21 mH and wherein the second differential mode inductor has an inductance value of approximately 10 mH;
a third differential mode inductor in series with the second differential mode inductor, wherein the third differential mode inductor has an inductance value of approximately 2.8 mH;
first and second resistors in parallel with the first differential mode inductor, wherein the first and second resistors each have a resistance value of approximately 2.37 k.OMEGA.;
first and second capacitors in parallel with the second differential mode inductor, wherein the first and second capacitors each have a capacitance value of approximately 0.0022 µF;
third and fourth capacitors in parallel with the third differential mode inductor, wherein the third and fourth capacitors each have a capacitance value of approximately 0.022 µF;
a first shunt leg interposed between the first and second differential mode inductors and coupled across a first and second winding of the first differential mode inductor, wherein the first shunt leg comprises a fifth capacitor having a capacitance value of approximately 0.022 µF and a third resistor coupled in series with the fifth capacitor and having a resistance value of approximately 51.1 .OMEGA.;
a second shunt leg interposed between the second and third differential mode inductors and coupled across a first and second winding of the second differential mode inductor, wherein the second shunt leg comprises a sixth capacitor having a capacitance value of approximately 0.036 µF; and a third shunt leg coupled across a first and second winding of the third differential mode inductor, wherein the third shunt leg comprises a seventh capacitor having a capacitance value of approximately 0.01 µF;
wherein the third differential mode inductor is interposed between the second shunt leg and the third shunt leg.
20. A low-pass filter, comprising:
a fourth-order first stage comprising:
a first differential mode inductor in series with a second differential mode inductor;
first and second resistors in parallel with the first differential mode inductor, wherein the first and second resistors each have approximately the same resistance value;
first and second capacitors in parallel with the second differential mode inductor, wherein the first and second capacitors each have approximately the same capacitance value;
a first shunt leg interposed between the first and second differential mode inductors and coupled across a first and second winding of the first differential mode inductor; and a second shunt leg interposed between the second and third differential mode inductors and coupled across a first and second winding of the second differential mode inductor;
a second-order second stage in cascade with the first stage, the second stage comprising:
a third differential mode inductor having an inductance value of less than half of an inductance value of the first differential mode inductor or an inductance value of the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor, wherein the third and fourth capacitors each have approximately the same capacitance value; and a third shunt leg coupled across a first and second winding of the third differential mode inductor;
wherein the third differential mode inductor is interposed between the second shunt leg and the third shunt leg.
a fourth-order first stage comprising:
a first differential mode inductor in series with a second differential mode inductor;
first and second resistors in parallel with the first differential mode inductor, wherein the first and second resistors each have approximately the same resistance value;
first and second capacitors in parallel with the second differential mode inductor, wherein the first and second capacitors each have approximately the same capacitance value;
a first shunt leg interposed between the first and second differential mode inductors and coupled across a first and second winding of the first differential mode inductor; and a second shunt leg interposed between the second and third differential mode inductors and coupled across a first and second winding of the second differential mode inductor;
a second-order second stage in cascade with the first stage, the second stage comprising:
a third differential mode inductor having an inductance value of less than half of an inductance value of the first differential mode inductor or an inductance value of the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor, wherein the third and fourth capacitors each have approximately the same capacitance value; and a third shunt leg coupled across a first and second winding of the third differential mode inductor;
wherein the third differential mode inductor is interposed between the second shunt leg and the third shunt leg.
21. The low-pass filter of claim 20, wherein the first stage has a stop-band of approximately 48 kHz and the second stage has a stop-band of approximately 29 kHz.
22. A low-pass filter, consisting essentially of:
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
a first resistor in parallel with a first winding of the first differential mode inductor;
a second resistor in parallel with a second winding of the first differential made inductor;
a first capacitor in parallel with a first winding of the second differential mode inductor;
a second capacitor in parallel with a second winding of the second differential mode inductor;
a third capacitor in parallel with a first winding of the third differential mode inductor;
a fourth capacitor in parallel with a second winding of the third differential mode inductor;
a first shunt leg comprising a first end coupled between the first windings of the first and second differential mode inductors and a second end coupled between the second windings of the first and second differential mode inductors;
a second shunt leg comprising a first end coupled between the first windings of the second and third differential mode inductors and a second end coupled between the second windings of the second and third differential mode inductors; and a third shunt leg comprising a first end coupled to the first winding of the third differential mode inductor and a second end coupled to the second winding of the third differential mode inductor;
wherein the third differential mode inductor is coupled between the second and third shunt legs.
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
a first resistor in parallel with a first winding of the first differential mode inductor;
a second resistor in parallel with a second winding of the first differential made inductor;
a first capacitor in parallel with a first winding of the second differential mode inductor;
a second capacitor in parallel with a second winding of the second differential mode inductor;
a third capacitor in parallel with a first winding of the third differential mode inductor;
a fourth capacitor in parallel with a second winding of the third differential mode inductor;
a first shunt leg comprising a first end coupled between the first windings of the first and second differential mode inductors and a second end coupled between the second windings of the first and second differential mode inductors;
a second shunt leg comprising a first end coupled between the first windings of the second and third differential mode inductors and a second end coupled between the second windings of the second and third differential mode inductors; and a third shunt leg comprising a first end coupled to the first winding of the third differential mode inductor and a second end coupled to the second winding of the third differential mode inductor;
wherein the third differential mode inductor is coupled between the second and third shunt legs.
23. The low-pass filter of claim 22, wherein the first shunt leg consists essentially of a capacitor in series with a resistor and the second and third shunt legs each consist essentially of a capacitor.
24. A POTS splitter, comprising:
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter comprises:
first, second and third differential mode inductors in series between the POTS port and the xDSL out port;
first and second resistors in parallel with the first differential mode inductor;
first and second capacitors in parallel with the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor;
a first shunt leg interposed between the first and second differential mode inductors and coupled across the first and second differential mode inductors;
a second shunt leg interposed between the second and third differential mode inductors and coupled across the second and third differential mode inductors; and a third shunt leg coupled across the third differential mode inductor.
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter comprises:
first, second and third differential mode inductors in series between the POTS port and the xDSL out port;
first and second resistors in parallel with the first differential mode inductor;
first and second capacitors in parallel with the second differential mode inductor;
third and fourth capacitors in parallel with the third differential mode inductor;
a first shunt leg interposed between the first and second differential mode inductors and coupled across the first and second differential mode inductors;
a second shunt leg interposed between the second and third differential mode inductors and coupled across the second and third differential mode inductors; and a third shunt leg coupled across the third differential mode inductor.
25. The POTS splitter of claim 24, further comprising overvoltage and surge protection coupled between the low-pass filter and the xDSL out port.
26. The POTS splitter of claim 24, further comprising signature resistance and loop presence indication coupled between the low-pass filter and the POTS port.
27. The POTS splitter of claim 24, wherein the low-pass filter has a pass-band of approximately 0-4 kHz and the high-pass filter has a pass-band of approximately 32 kHz and above.
28. The POTS splitter of claim 24, wherein the low-pass filter is a passive low-pass filter.
29. The POTS splitter of claim 24, further comprising a high-pass filter for coupling between an xDSL in port and the xDSL out port.
30. The POTS splitter of claim 29, wherein the high-pass filter is an RC
filter.
filter.
31. The POTS splitter of claim 29, wherein the high-pass filter comprises a capacitor coupled between a tip line of the xDSL in port and the xDSL out port and a capacitor coupled between a ring line of the xDSL in port and the xDSL out port.
32. The POTS splitter of claim 24, wherein the first resistor and the second resistor have substantially the same resistance.
33. The POTS splitter of claim 24, wherein the first capacitor and the second capacitor have substantially the same capacitance and the third capacitor and the fourth capacitor have substantially the same capacitance.
34. A POTS splitter, comprising:
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter comprises:
a first differential mode inductor having a first winding and a second winding, wherein the first winding corresponds to a tip line and the second winding corresponds to a ring line;
a second differential mode inductor in series with the first differential made inductor and having a first winding and a second winding, wherein the first winding corresponds to the tip line and the second winding corresponds to the ring line;
a third differential mode inductor in series with the first and second differential mode inductors and having a first winding and a second winding, wherein the first winding corresponds to the tip line and the second winding corresponds to the ring line;
a first resistance in parallel with the first winding of the first differential mode inductor;
a second resistance in parallel with the second winding of the first differential mode inductor;
a first capacitance in parallel with the first winding of the second differential mode inductor;
a second capacitance in parallel with the second winding of the second differential mode inductor;
a third capacitance in parallel with the first winding of the third differential mode inductor;
a fourth capacitance in parallel with the second winding of the third differential mode inductor;
a fifth capacitance in series with a third resistance coupled between the tip line and the ring line;
a sixth capacitance coupled between the tip line and the ring line; and a seventh capacitance coupled between the tip line and the ring line;
wherein the fifth capacitance and the third resistance are interposed between the first and second differential mode inductors;
wherein the sixth capacitance is interposed between the second and third differential mode inductors; and wherein the third differential mode inductor in interposed between the sixth and seventh capacitances.
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter comprises:
a first differential mode inductor having a first winding and a second winding, wherein the first winding corresponds to a tip line and the second winding corresponds to a ring line;
a second differential mode inductor in series with the first differential made inductor and having a first winding and a second winding, wherein the first winding corresponds to the tip line and the second winding corresponds to the ring line;
a third differential mode inductor in series with the first and second differential mode inductors and having a first winding and a second winding, wherein the first winding corresponds to the tip line and the second winding corresponds to the ring line;
a first resistance in parallel with the first winding of the first differential mode inductor;
a second resistance in parallel with the second winding of the first differential mode inductor;
a first capacitance in parallel with the first winding of the second differential mode inductor;
a second capacitance in parallel with the second winding of the second differential mode inductor;
a third capacitance in parallel with the first winding of the third differential mode inductor;
a fourth capacitance in parallel with the second winding of the third differential mode inductor;
a fifth capacitance in series with a third resistance coupled between the tip line and the ring line;
a sixth capacitance coupled between the tip line and the ring line; and a seventh capacitance coupled between the tip line and the ring line;
wherein the fifth capacitance and the third resistance are interposed between the first and second differential mode inductors;
wherein the sixth capacitance is interposed between the second and third differential mode inductors; and wherein the third differential mode inductor in interposed between the sixth and seventh capacitances.
35. The POTS splitter of claim 34, wherein the low-pass filter is substantially devoid of active components.
36. The POTS splitter of claim 34, further comprising:
a third resistance in parallel with the first capacitance and the first winding of the second differential mode inductor;
a fourth resistance in parallel with the second capacitance and the second winding of the second differential mode inductor;
an eighth capacitance in parallel with the first resistance and the first winding of the first differential mode inductor;
a ninth capacitance in parallel with the second resistance and the second winding of the first differential mode inductor; and a fifth resistance in series with the fifth capacitance and coupled between the tip line and the ring line.
a third resistance in parallel with the first capacitance and the first winding of the second differential mode inductor;
a fourth resistance in parallel with the second capacitance and the second winding of the second differential mode inductor;
an eighth capacitance in parallel with the first resistance and the first winding of the first differential mode inductor;
a ninth capacitance in parallel with the second resistance and the second winding of the first differential mode inductor; and a fifth resistance in series with the fifth capacitance and coupled between the tip line and the ring line.
37. A. remote-side xDSL modern, comprising:
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter consists essentially of:
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
a first resistor in parallel with a first winding of the first differential mode inductor, wherein the first winding of the first differential mode inductor corresponds to a tip line of the xDSL out port;
a second resistor in parallel with a second winding of the first differential mode inductor, wherein the second winding of the first differential mode inductor corresponds to a ring line of the xDSL out port;
a first capacitor in parallel with a first winding of the second differential mode inductor, wherein the first winding of the second differential mode inductor corresponds to the tip line of the xDSL out port;
a second capacitor in parallel with a second winding of the second differential mode inductor, wherein the second winding of the second differential mode inductor corresponds to the ring line of the xDSL out port;
a third capacitor in parallel with a first winding of the third differential mode inductor, wherein the first winding of the third differential mode inductor corresponds to the tip line of the xDSL out port;
a fourth capacitor in parallel with a second winding of the third differential mode inductor, wherein the second winding of the third differential mode inductor corresponds to the ring line of the xDSL out port;
a first shunt leg comprising a first end coupled between the first windings of the first and second differential mode inductors and a second end coupled between the second windings of the first arid second differential mode inductors;
a second shunt leg comprising a first end coupled between the first windings of the second and third differential mode inductors and a second end coupled between the second windings of the second and third differential mode inductors; and a third shunt leg comprising a first end coupled to the first winding of the third differential mode inductor and a second end coupled to the second winding of the third differential mode inductor;
wherein the third differential mode inductor is coupled between the second and third shunt legs.
a low-pass filter for coupling between an xDSL out port and a POTS port, wherein the low-pass filter consists essentially of:
a first differential mode inductor in series with a second differential mode inductor and a third differential mode inductor;
a first resistor in parallel with a first winding of the first differential mode inductor, wherein the first winding of the first differential mode inductor corresponds to a tip line of the xDSL out port;
a second resistor in parallel with a second winding of the first differential mode inductor, wherein the second winding of the first differential mode inductor corresponds to a ring line of the xDSL out port;
a first capacitor in parallel with a first winding of the second differential mode inductor, wherein the first winding of the second differential mode inductor corresponds to the tip line of the xDSL out port;
a second capacitor in parallel with a second winding of the second differential mode inductor, wherein the second winding of the second differential mode inductor corresponds to the ring line of the xDSL out port;
a third capacitor in parallel with a first winding of the third differential mode inductor, wherein the first winding of the third differential mode inductor corresponds to the tip line of the xDSL out port;
a fourth capacitor in parallel with a second winding of the third differential mode inductor, wherein the second winding of the third differential mode inductor corresponds to the ring line of the xDSL out port;
a first shunt leg comprising a first end coupled between the first windings of the first and second differential mode inductors and a second end coupled between the second windings of the first arid second differential mode inductors;
a second shunt leg comprising a first end coupled between the first windings of the second and third differential mode inductors and a second end coupled between the second windings of the second and third differential mode inductors; and a third shunt leg comprising a first end coupled to the first winding of the third differential mode inductor and a second end coupled to the second winding of the third differential mode inductor;
wherein the third differential mode inductor is coupled between the second and third shunt legs.
38. The remote-side modem of claim 37, wherein the first shunt leg consists essentially of a fifth capacitor in series with a third resistor, the second shunt leg consists essentially of a sixth capacitor, and the third shunt leg consists essentially of a seventh capacitor.
39. The remote-side modem of claim 37, further comprising overvoltage and surge protection coupled between the low-pass filter and the xDSL out port.
40. The remote-side modem of claim 38, further comprising:
wherein the first inductor has an inductance value of approximately 21 mH;
wherein the second inductor has an inductance value of approximately 10 mH;
wherein the third inductor has an inductance value of approximately 2.8 mH;
wherein the first and second resistors each have a resistance value of approximately 2.37 k.OMEGA.;
wherein the third resistor has a resistance value of approximately 51.1 .OMEGA.;
wherein the first and second capacitors each have a capacitance value of approximately 0.0022 µF;
wherein the third and fourth capacitors each have a capacitance value of approximately 0.022 µF;
wherein the fifth capacitor has a capacitance value of approximately 0.022 µF;
wherein the sixth capacitor has a capacitance value of approximately 0.036 µF; and wherein the seventh capacitor has a capacitance value of approximately 0.01 µF.
wherein the first inductor has an inductance value of approximately 21 mH;
wherein the second inductor has an inductance value of approximately 10 mH;
wherein the third inductor has an inductance value of approximately 2.8 mH;
wherein the first and second resistors each have a resistance value of approximately 2.37 k.OMEGA.;
wherein the third resistor has a resistance value of approximately 51.1 .OMEGA.;
wherein the first and second capacitors each have a capacitance value of approximately 0.0022 µF;
wherein the third and fourth capacitors each have a capacitance value of approximately 0.022 µF;
wherein the fifth capacitor has a capacitance value of approximately 0.022 µF;
wherein the sixth capacitor has a capacitance value of approximately 0.036 µF; and wherein the seventh capacitor has a capacitance value of approximately 0.01 µF.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/119,485 US6853724B2 (en) | 2001-12-14 | 2002-04-10 | Cascade low-pass filter to improve xDSL band attenuation for POTS splitter |
| US10/119,485 | 2002-04-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2424855A1 true CA2424855A1 (en) | 2003-10-10 |
| CA2424855C CA2424855C (en) | 2012-01-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2424855 Expired - Fee Related CA2424855C (en) | 2002-04-10 | 2003-04-09 | Cascade low-pass filter to improve xdsl band attenuation for pots splitter |
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| Country | Link |
|---|---|
| CA (1) | CA2424855C (en) |
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2003
- 2003-04-09 CA CA 2424855 patent/CA2424855C/en not_active Expired - Fee Related
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| CA2424855C (en) | 2012-01-17 |
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