200828797 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種使用於通訊領域之濾波電路，特 別是針對可適用在VDSL ( Very high bit-rate DSL )通 訊領域之濾波電路。 【先前技術】 請參照圖1，為一種習知應用於VDSL通訊領域之 濾波電路1之電路組成示意圖，該濾波電路1具有一輸 入端input及一輸出端output，且於該輸入端input與該 輸出端output之間包括有複數個電感器組L1〜L6、複數 個電容器C1〜C9及複數個電阻器R1〜R4。 該濾波電路1之輸入端input係包括二接腳tip、 ring，其係電性連接於一通訊設備（圖中未示）之一通 吼線路，而該輸出端output亦包括二接腳tip、ring，其 係可電性連接於一交換機（例如電話），該濾波電路1 接收該通訊線路之一訊號後，係可對其經過的訊號頻率 產生過濾之作用，並輸出至該交換機。 該複數個電感組L1〜L6係以串聯方式連接在該輸 =端111PUt與該輸出端0utPut之間，且該些電感組L1〜L6 =具有_ 一第一繞組L1 及一第二繞組L12〜L62，而 每一第一繞組LU〜L61與其相對應的每一第二繞組 L12〜L62係可繞設在一環形鐵心（圖未示）上，以形成 200828797 該些電感組L1〜L6。 該電容器ci設置於該電感組L1與該電感組L2之 間，且該電容器ci之一端係電性連接於該第一繞組L1 i 及該第一繞組L21，另一端則電性連接於該第二繞組 L12及該第二繞組L22 ;該電容器C4設置於該電感組 L4與該電感組L5之間’且該電容器之一端係電性 連接於該第一繞組L41及該第一繞組L51，另一端則電 性連接於該第二繞組L42及該第二繞組L52;該電容器 C7設置於該電感組L5與該電感組L6之間，且該電容 器C7之一端係電性連接於該第一繞組L51及該第一繞 組L61，另一端則電性連接於該第二繞組l52及該第二 繞組L62。 该電容l§ C2電性跨接於該電感組L2的第一繞組 L21且更電性連接於該電容器ci與該電阻器R1之 間；該電阻器R1電性跨接於該電感組L3的第一繞組 L31，且更電性連接於該電容器〔丨與該電阻器r3之 間’该電阻器R3電性跨接於該電感組L4的第一繞組 且更電ϋ連接於該電阻器R1與該些電容器、 婊之門亥電谷器C5電性跨接於該電感組L5的第一 、 且更電性連接於該電容器L7該電阻器R3斑 該些電容器C7、C8之間。 ” ㈣ί二電谷态C3、C6、C9及該些電阻器R2、R4係 連接於該些電感組L1〜L6的第二繞㉟L12〜L62，其 200828797 連接關係由圖中可知係與該些電容器C2、C5、C8及該 t電阻器R1、R3相同，故在此不另多做說明。 睛參閱® 2所示，係為圖1之該渡波電路1的頻率 響應圖圖中所示，其係具有一第_頻率響應線 lmeH、一第一頻率響應線lineL，以及上述該濾波電路 為1所產生之一實際頻率響應線lineR，該第一頻率響 應線lineH與該第二頻率響應線lineL皆為歐洲電訊標 準局（ETSI)所制定有關於VDSL2傳輸協定中Ts 1〇1 952-2_1規範之臨界值，其中該規範規定頻率響應於 30MHZ以上時，其雜訊應在_55dB以下始通過標準，惟 如圖中所不，習知濾波電路1頻率響應在30MHZ時， 其雜訊僅為-42.093dB，明顯無法適用於歐洲電訊標準 局所制訂的規範。再者，習知濾波電路1係至少應用了 六個電感組L1〜L6、九個電容器C1〜C9及四個電阻器 R1 R4 ’其整體架構所須消耗元件數量過多，對於愈來 ，‘愈4求電子通訊產品小型化及低成本化的產業界，此一 習知濾波電路1效能實顯不足，故有改善之必要。 因此，如何提供一種可適用於歐洲通訊協定且能降 低產製成本之濾波電路，實屬當前重要課題之一。 【發明内容】 有鑑於上述課題，本發明提供一種可符合歐洲通訊 協定且低產製成本之濾波電路。 200828797 緣：’為達上述目的’本發明提供一種濾波電路， -糸由複數個電感組、複數個共振電容器、複數個阻抗 ，配電路及複數個衰減電容器所組成，其中該複數個電 感組係以串聯方式電性連接在㈣波電路之—輸入端 與一輸出端之間，每—共振電容器係以並聯方式電性連 接在兩兩電感組之間’該複數個阻抗匹配電路係各自電 I*生連接於4些電感組其中之―，該複數個衰減電容器係 各自電性連接於該些阻抗匹配電路與該些電感組其中 之一〇 山根據上述構想，該電性連接於該濾波電路之該輸出 之4電感、、且係可為一共模抑制電感組，而該複數個電 感組、複數個共振電容器、複數個阻抗匹配電路及複數 個衰減電容H係可料算後選擇適#值，而使得該滤波 電路旎更完全符合歐洲通訊協定之規範，且可藉由較少 的元件組合以避免增加不必要的成本。 【實施方式】 凊參照圖3，圖中所示為本發明實施例之濾波電路 2之電路組成示意圖；如圖所示，該濾波電路2係具有 一輸入端input及一輸出端output，且於該輸入端input 與該輸出端output之間包括有一第一電感組L7、一第 二電感組L8、一第三電感組L9、一第四電感組u〇、 一第一共振電容器cio' —第二共振電容器cu、一第 200828797 二共振電容器C12、一第一阻抗匹配電路1〇、一第二阻 抗匹配電路20、一第一衰減電容器C15及一第二衰減 電容器C16，其中該些電感組L7〜L1〇係以串聯方式電 性連接在該濾波電路2之該輸入端input與該輸出端 output之間，每一共振電容器cl〇〜C12係以並聯方式電 性連接在兩兩電感組之間，該些複數個阻抗匹配電路 10〜20係各自電性連接於該些電感組L7〜L10其中之 一，忒些衰減電容器C15〜C10則各自電性連接於該些 阻抗匹配電路10〜20及該些電感組L7〜L10其中之一。 戎濾波電路2之輸入端input係包括二接腳tip、 ring，其係電性連接於一通訊設備（圖中未示）之一通 訊線路，而該輸出端output亦包括二接腳tip、ring，其 係可電性連接於—交換機（圖中未示），該濾、波電路2 接收該通訊線路之一訊號後，係可對其經過的訊號頻率 產生過濾之作用，並輸出至該交換機。 ， A些電感組L7〜L1〇各包括有一第一繞組 L7:〜L101及—第二繞組L72〜L102,每一電感組L7〜L10 之=二繞組L71〜li〇1與第二繞組L72〜L1〇2係繞設於 一環形鐵心上，因而形成該些電感組L7〜L10。另外， 在此實施例當中，該第-電感組L7、該第二電感組L8 及該第三電感組L9係為一差模抑制電感組，而該第四 電感組L10係為一共模抑制電感组，其係可提供渡除雜 汛之效，而將處理後之訊號輸出之該輸出端output。 9 200828797 遠第一共振電容器CIO係設置於該第一電感組L7 與該第二電感組L8之間，且該第一共振電容器cl〇之 一端係電性連接於該第一繞組L71及該第一繞組L81， 另一端則電性連接於該第二繞組L72及該第二繞組 L82’该第二共振電容器cu設置於該第二電感組L8 與该第二電感組L9之間，且該第二共振電容器€11之 一鳊係電性連接於該第一繞組L8丨及該第一繞組L9 i， 另一端則電性連接於該第二繞組L82及該第二繞組 L82 ;該第三共振電容器C12設置於該第三電感組L9 與该第四電感組L1〇之間，且該第三共振電容器C12 之一端係電性連接於該第一繞組L91及該第一繞組 L101，另一端則電性連接於該第二繞組ί92及該第二繞 組 L10 2 〇 該第一阻抗匹配電路10電性連接於該第二電感組 L8之第一繞組L81，且其包括有一電阻器R5及一電容 器C13，該電阻器R5與該電容器C13係並聯連接，且 該第一阻抗匹配電路1〇乃藉由該電容器C13並聯連接 於該第一繞組L81。 該第二阻抗匹配電路20電性連接於該第二電感組 L8之第二繞組L82，且其包括有一電阻器R6及一電容 器C14 ’該電阻器R6與該電容器c 14係並聯連接，且 該第二阻抗匹配電路20乃藉由該電容器C14並聯連接 於該第二繞組L82。 200828797 上述該第一阻抗匹配電路10與該第二阻抗匹配電 路2〇主要係可與該輸入端inputm連接之該通訊線路阻 抗匹配，以避免因訊號反射導致訊號強度降低或干擾臨 近線路。 该弟一哀減電容器C15係電性連接於該電容器c 13 與δ亥第二共振電容器C12’而該第二衰減電容器ci6係 電性連接於该電容器C14與該第三共振電容器ci2，藉 由該二衰減電容器C15、C16的組合，即可令訊號中的 雜訊部份衰減。 在此特別要強調的是，藉由適當地計算選取上述該 濾、波電路2内各元件的值，係可使得該渡波電路2的頻 率響應更符合歐洲通訊協定之規範，在此係舉例各元件 的適當選取值： 第一電感組之電感值：2. 5Mh ; 弟一電感組之電感值：7. OmH ; 第三電感組之電感值：2. OmH ; 該第四電感組之電感值：600#!!; 該第一共振電容器之電容值：12 nF; 該第二共振電容器之電容值：18nF; 該第三共振電容器之電容值：27nF ; 該第一阻抗匹配電路之該電阻器之電阻值：91 Ω ; 該第一阻抗匹配電路之該電容器之電容值：27〇nF ; 該第二阻抗匹配電路之該電阻器之電阻值·· 9丨◦; 11 200828797 該第二阻抗匹配電路之該電容器之電容值：270nF， 該第一衰減電容器之電容值：5.6nF ; 該第二衰減電容器之電容值：5· 6nF ° 請參閱圖4所示，係為圖3之濾波電路2之頻率響 應圖，如圖所示，本發明之該濾波電路2所產生之一實 際頻率響應線lineR，其係座落於該第一頻率響應線 lineH與該第二頻率響應線lineL之間，並未超出該二頻 率響應線lineH、lineL之臨界值，如圖所示，渡波電路 1頻率響應在30MHZ時，其雜訊為-62.583dB，已能符 合雜訊應在-55dB以下之標準。也就是說，上述該濾波 電路2的頻率響應已能符合歐洲地區通訊協定的規 範:而能提供至歐洲市場使用；再者，本發明藉由較少 的兀件，而可刪除不必要的成本支出，對於電子通1產 ==化及低成本化可謂—大助益，實可稱為一進步 離 更 A工岍现惶馮舉例性，而非為限制性者。任 本發明之精神與範疇，而對其進行之 η 、 ’均應包含於後附之申請專利範圍中。^改或璧 【圖式簡單說明】 口；：習知渡波電路之電路組成示意圖; 圖2為圖1之濾波電路之頻率響應圖； 12 200828797 圖3為本發明較佳實施例所述之濾波電路之電路組成 示意圖。 圖4為圖3之濾波電路之頻率響應圖。 元件符號說明： 1、2 濾波電路 LI、L2、L3、L4、L5、L0 電感器組 L7 第一電感組 L8 第二電感組 L9 第三電感組 L10 第四電感組BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit for use in the field of communication, and in particular to a filter circuit applicable to the VDSL (very high bit-rate DSL) communication field. [Prior Art] Please refer to FIG. 1 , which is a circuit diagram of a conventional filter circuit 1 applied to the VDSL communication field. The filter circuit 1 has an input terminal and an output terminal, and the input terminal inputs The output ends include a plurality of inductor groups L1 L L6, a plurality of capacitors C1 C C9 and a plurality of resistors R1 R R4. The input terminal of the filter circuit 1 includes two pins tip and ring, which are electrically connected to one of the communication devices (not shown), and the output terminal also includes two pin tips and rings. The filter circuit 1 can be electrically connected to a switch (for example, a telephone). After receiving the signal of the communication line, the filter circuit 1 can filter the frequency of the signal passing through and output to the switch. The plurality of inductor groups L1 L L6 are connected in series between the input terminal 111PUt and the output terminal ButPut, and the inductor groups L1 L L6 = have a first winding L1 and a second winding L12. L62, and each of the first windings LU~L61 and its corresponding second windings L12~L62 can be wound around a toroidal core (not shown) to form the inductive groups L1~L6 of 200828797. The capacitor ci is disposed between the inductor group L1 and the inductor group L2, and one end of the capacitor ci is electrically connected to the first winding L1 i and the first winding L21, and the other end is electrically connected to the first a second winding L12 and a second winding L22; the capacitor C4 is disposed between the inductor group L4 and the inductor group L5' and one end of the capacitor is electrically connected to the first winding L41 and the first winding L51, and One end is electrically connected to the second winding L42 and the second winding L52; the capacitor C7 is disposed between the inductor group L5 and the inductor group L6, and one end of the capacitor C7 is electrically connected to the first winding The other end of the L51 and the first winding L61 is electrically connected to the second winding l52 and the second winding L62. The capacitor § C2 is electrically connected across the first winding L21 of the inductor group L2 and is electrically connected between the capacitor ci and the resistor R1. The resistor R1 is electrically connected across the inductor group L3. The first winding L31 is further electrically connected between the capacitor [丨 and the resistor r3]. The resistor R3 is electrically connected across the first winding of the inductor group L4 and is further electrically connected to the resistor R1. The capacitors and the capacitors C5 are electrically connected to the first group of the inductor group L5, and are electrically connected to the capacitor L7. The resistor R3 is between the capacitors C7 and C8. (4) ί 二电谷 state C3, C6, C9 and the resistors R2, R4 are connected to the second windings 35L12~L62 of the inductance groups L1~L6, and the connection relationship of the 200828797 is known from the figure C2, C5, C8 and the t resistors R1, R3 are the same, so there is no further explanation here. The eye is shown in Fig. 2, which is shown in the frequency response diagram of the wave circuit 1 of Fig. 1, The system has a first frequency response line lmeH, a first frequency response line lineL, and an actual frequency response line lineR generated by the filter circuit 1 as described above, the first frequency response line lineH and the second frequency response line lineL Both the European Telecommunications Standards Institute (ETSI) has a threshold value for the Ts 1〇1 952-2_1 specification in the VDSL2 transmission protocol, where the specification specifies that the frequency response should be below _55dB when the frequency response is above 30 MHz. Standard, but as shown in the figure, the frequency response of the conventional filter circuit 1 is 30MHZ, and its noise is only -42.093dB, which is obviously not applicable to the specifications developed by the European Telecommunications Standards Bureau. Furthermore, the conventional filter circuit 1 At least six inductor groups L1~L6, nine are applied Capacitors C1 to C9 and four resistors R1 R4 'there are too many components to be consumed in the overall structure. For the more and more, the industry is looking for a small-scale and low-cost electronic communication product. The performance is not enough, so it is necessary to improve. Therefore, how to provide a filter circuit that can be applied to the European communication protocol and can reduce the cost of production is one of the current important topics. [Invention] In view of the above problems, The invention provides a filter circuit which can meet the European communication protocol and has low production cost. 200828797 Edge: 'To achieve the above purpose', the present invention provides a filter circuit, which is composed of a plurality of inductor groups, a plurality of resonance capacitors, a plurality of impedances, and a power distribution system. The circuit and the plurality of attenuation capacitors are formed, wherein the plurality of inductance groups are electrically connected in series between the input end and the output end of the (four) wave circuit, and each of the resonance capacitors is electrically connected in parallel in two Between the two inductive groups, the plurality of impedance matching circuits are electrically connected to each of the four inductive groups, and the plurality of inductive groups are The capacitors are electrically connected to the impedance matching circuit and one of the inductor groups. According to the above concept, the output is electrically connected to the output of the filter circuit, and the mode can be a common mode rejection. The inductor group, and the plurality of inductor groups, the plurality of resonance capacitors, the plurality of impedance matching circuits, and the plurality of attenuation capacitors H can be selected to calculate the value of the appropriate value, so that the filter circuit is more in full compliance with the specifications of the European Protocol And the combination of fewer components can be used to avoid unnecessary cost increase. [Embodiment] Referring to FIG. 3, a circuit diagram of a filter circuit 2 according to an embodiment of the present invention is shown; The filter circuit 2 has an input terminal input and an output terminal output, and includes a first inductor group L7, a second inductor group L8, and a third inductor group L9 between the input terminal input and the output terminal output. a fourth inductive group u〇, a first resonant capacitor cio'-second resonant capacitor cu, a 200828797 two-resonant capacitor C12, a first impedance matching circuit 1〇, a second The anti-matching circuit 20, a first attenuating capacitor C15 and a second attenuating capacitor C16, wherein the inductive groups L7 L L1 are electrically connected in series to the input end of the filter circuit 2 and the output end Each of the resonant capacitors c1 to C12 is electrically connected in parallel between the two inductive groups, and the plurality of impedance matching circuits 10 to 20 are electrically connected to the inductive groups L7 to L10, respectively. For example, the attenuation capacitors C15 to C10 are electrically connected to the impedance matching circuits 10 to 20 and one of the inductance groups L7 to L10. The input end of the 戎 filter circuit 2 includes two pins, a ring, which is electrically connected to a communication line of a communication device (not shown), and the output terminal also includes two pin tips and rings. The system can be electrically connected to the switch (not shown). After receiving the signal of the communication line, the filter circuit 2 can filter the signal frequency passing through the filter and output to the switch. . A plurality of inductance groups L7 to L1 〇 each include a first winding L7: 〜L101 and _ second windings L72 〜 L102, each of the inductance groups L7 〜 L10 = two windings L71 〇 li 〇 1 and second winding L 72 〜 The L1〇2 is wound around a toroidal core, thereby forming the inductance groups L7 to L10. In addition, in this embodiment, the first inductor group L7, the second inductor group L8, and the third inductor group L9 are a differential mode suppression inductor group, and the fourth inductor group L10 is a common mode rejection inductor. The group, which provides the effect of removing the chowder, and outputs the output of the processed signal. 9 200828797 The far first resonant capacitor CIO is disposed between the first inductive group L7 and the second inductive group L8, and one end of the first resonant capacitor cl〇 is electrically connected to the first winding L71 and the first a winding L81, the other end is electrically connected to the second winding L72 and the second winding L82'. The second resonant capacitor cu is disposed between the second inductive group L8 and the second inductive group L9, and the first One of the two resonant capacitors 11 is electrically connected to the first winding L8 丨 and the first winding L9 i , and the other end is electrically connected to the second winding L82 and the second winding L82 ; the third resonance The capacitor C12 is disposed between the third inductor group L9 and the fourth inductor group L1, and one end of the third resonant capacitor C12 is electrically connected to the first winding L91 and the first winding L101, and the other end is Electrically connected to the second winding ί92 and the second winding L10 2 , the first impedance matching circuit 10 is electrically connected to the first winding L81 of the second inductor group L8 , and includes a resistor R5 and a capacitor C13, the resistor R5 is connected in parallel with the capacitor C13, and The first impedance matching circuit 1 is connected in parallel to the first winding L81 via the capacitor C13. The second impedance matching circuit 20 is electrically connected to the second winding L82 of the second inductor group L8, and includes a resistor R6 and a capacitor C14 'the resistor R6 is connected in parallel with the capacitor c 14 , and the The second impedance matching circuit 20 is connected in parallel to the second winding L82 via the capacitor C14. 200828797 The first impedance matching circuit 10 and the second impedance matching circuit 2 are mainly matched with the communication line impedance connected to the input terminal inputm to avoid signal strength degradation or interference with nearby lines due to signal reflection. The second snubber capacitor C15 is electrically connected to the capacitor c 13 and the second resonant capacitor C12 ′, and the second snubber capacitor ci6 is electrically connected to the capacitor C14 and the third resonant capacitor ci2. The combination of the two attenuation capacitors C15 and C16 can attenuate the noise portion of the signal. In particular, it is emphasized that by appropriately calculating the values of the components in the filter circuit 2, the frequency response of the wave circuit 2 can be made more in line with the specifications of the European Protocol. The appropriate value of the component: the inductance value of the first inductance group: 2. 5Mh; the inductance value of the first inductance group: 7. OmH; the inductance value of the third inductance group: 2. OmH; the inductance value of the fourth inductance group : 600#!!; The capacitance of the first resonant capacitor: 12 nF; the capacitance of the second resonant capacitor: 18 nF; the capacitance of the third resonant capacitor: 27 nF; the resistor of the first impedance matching circuit The resistance value is 91 Ω; the capacitance value of the capacitor of the first impedance matching circuit: 27〇nF; the resistance value of the resistor of the second impedance matching circuit·· 9丨◦; 11 200828797 the second impedance matching The capacitance value of the capacitor of the circuit: 270 nF, the capacitance value of the first attenuation capacitor: 5.6 nF; the capacitance value of the second attenuation capacitor: 5·6 nF ° See FIG. 4, which is the filter circuit 2 of FIG. Frequency response diagram, as shown, the present invention The actual frequency response line lineR generated by the filter circuit 2 is located between the first frequency response line lineH and the second frequency response line lineL, and does not exceed the criticality of the two frequency response lines lineH and lineL. The value, as shown in the figure, when the frequency response of the wave circuit 1 is 30 MHz, the noise is -62.583 dB, which can meet the standard that the noise should be below -55 dB. That is to say, the frequency response of the filter circuit 2 described above can meet the specifications of the European Regional Communication Protocol: it can be provided for use in the European market; in addition, the present invention can remove unnecessary costs by using fewer components. Expenditure, for e-commerce, production, and low-cost, can be described as a big benefit, which can be called a progress from the A-worker, now von, for example, rather than restrictive. The spirit and scope of the present invention are to be construed as being included in the scope of the appended claims. ^改改璧 [schematic description] port; schematic diagram of the circuit composition of the conventional wave circuit; Figure 2 is the frequency response diagram of the filter circuit of Figure 1; 12 200828797 Figure 3 is a filter according to a preferred embodiment of the present invention Schematic diagram of the circuit composition of the circuit. 4 is a frequency response diagram of the filter circuit of FIG. 3. Component symbol description: 1, 2 filter circuit LI, L2, L3, L4, L5, L0 inductor group L7 first inductor group L8 second inductor group L9 third inductor group L10 fourth inductor group
Lll、L21、L31、L41、L51、L6卜 L7卜 L8卜 L91、 L101 第一繞組 L12、L22、L32、L42、L52、L62、L72、L82、L92、 L102 第二繞組 CM、C2、C3、C4、C5、C6、C7、C8、C9、C13、C14 電容器 C10 第一共振電容器 C12 第三共振電容器 C16 第二衰減電容器 ΪΠ、R2、R3、R4、R5、 input 輸入端 lineH 第一頻率響應線 lineR實際頻率響應線 C11 第二共振電容器 C15 第一衰減電容器 R6 電阻器 output輸出端 lineL第二頻率響應線 13Lll, L21, L31, L41, L51, L6, L7, L8, L91, L101, first winding L12, L22, L32, L42, L52, L62, L72, L82, L92, L102, second winding CM, C2, C3, C4, C5, C6, C7, C8, C9, C13, C14 Capacitor C10 First resonant capacitor C12 Third resonant capacitor C16 Second attenuation capacitor ΪΠ, R2, R3, R4, R5, input Input line lineH First frequency response line lineR actual frequency response line C11 second resonance capacitor C15 first attenuation capacitor R6 resistor output output line line second frequency response line 13