CN101207368A - Wave filter circuit - Google Patents

Wave filter circuit Download PDF

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Publication number
CN101207368A
CN101207368A CNA2006101717341A CN200610171734A CN101207368A CN 101207368 A CN101207368 A CN 101207368A CN A2006101717341 A CNA2006101717341 A CN A2006101717341A CN 200610171734 A CN200610171734 A CN 200610171734A CN 101207368 A CN101207368 A CN 101207368A
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CN
China
Prior art keywords
inductive bank
filter circuit
capacitor
impedance matching
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101717341A
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Chinese (zh)
Inventor
李宗宪
李丽娥
施华盛
许汉正
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Delta Electronics Inc
Delta Optoelectronics Inc
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Delta Optoelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Delta Optoelectronics Inc filed Critical Delta Optoelectronics Inc
Priority to CNA2006101717341A priority Critical patent/CN101207368A/en
Publication of CN101207368A publication Critical patent/CN101207368A/en
Pending legal-status Critical Current

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Abstract

The invention provides a filter circuit, which is applied to the VDSL communication field. The invention consists of a plurality of inductor units, a plurality of resonant capacitors, a plurality of impedance matching circuits, and a plurality of attenuation capacitors. The inductor units are communicated in series between the input end and the output end of the filter circuit, each resonant capacitor is communicated in parallel between every two inductor units. Each of the impedance matching circuits is communicated to one of the inductor units respectively, and each of the attenuation capacitors is communicated to one of the impedance matching circuits and to one of the inductor units respectively.

Description

Filter circuit
Technical field
The present invention is about a kind of filter circuit that is used in the communications field, particularly at applicable filter circuit in VDSL (the Very high bit-rate DSL) communications field.
Background technology
Please refer to Fig. 1, for a kind of known application is formed schematic diagram in the circuit of the filter circuit 1 of the VDSL communications field, this filter circuit 1 has an input input and an output output, and includes a plurality of bank of inductors L1-L6, a plurality of capacitor C1-C9 and a plurality of resistor R 1-R4 between this input input and this output output.
The input input of this filter circuit 1 comprises two pin contacts, loop (tip, ring), it is electrically connected to a communication line of a communication equipment (not shown), and this output output also comprises two pin contacts, loop (tip, ring), it can be electrically connected to a switch (for example phone), after this filter circuit 1 receives a signal of this communication line, can produce the effect of filtering to the signal frequency of its process, and export this switch to.
These a plurality of inductive bank L1-L6 are connected between this input input and this output output with series system, and these a plurality of inductive bank L1-L6 all have one first winding L 11-L61 and one second winding L 12-L62, and but each first winding L 11-L61 each second winding L 12-L62 winding corresponding with it is on a ring-shaped core (figure does not show), to form these a plurality of inductive bank L1-L6.
This capacitor C1 is arranged between this inductive bank L1 and this inductive bank L2, and the end of this capacitor C1 is electrically connected to this first winding L 11 and this first winding L 21, and the other end then is electrically connected to this second winding L 12 and this second winding L 22; This capacitor C4 is arranged between this inductive bank L4 and this inductive bank L5, and the end of this capacitor C4 is electrically connected to this first winding L 41 and this first winding L 51, and the other end then is electrically connected to this second winding L 42 and this second winding L 52; This capacitor C7 is arranged between this inductive bank L5 and this inductive bank L6, and the end of this capacitor C7 is electrically connected to this first winding L 51 and this first winding L 61, and the other end then is electrically connected to this second winding L 52 and this second winding L 62.
This capacitor C2 electricity is connected to first winding L 21 among this inductive bank L2, and also is electrically connected between this capacitor C1 and this resistor R 1; This resistor R 1 electricity is connected to first winding L 31 of this inductive bank L3, and also is electrically connected between this capacitor C1 and this resistor R 3; These resistor R 3 electricity are connected to first winding L 41 of this inductive bank L4, and also are electrically connected between this resistor R 1 and this a plurality of capacitor C4, the C5; This capacitor C5 electricity is connected to first winding L 51 of this inductive bank L5, and also is electrically connected between this resistor R 3 of this capacitor L7 and this a plurality of capacitor C7, the C8.
These a plurality of capacitor C3, C6, C9 and this a plurality of resistor R 2, R4 are electrically connected to the second winding L 12-L62 of these a plurality of inductive bank L1-L6, it connect to close by identical with these a plurality of capacitor C2, C5, C8 and this a plurality of resistor R 1, R3 as can be known among the figure, so other does not do explanation more at this.
See also shown in Figure 2, frequency response chart for this filter circuit 1 of Fig. 1, as shown in FIG., it has a first frequency line of response lineH, one second frequency line of response lineL, and the actual frequency line of response lineR that produced of above-mentioned this filter circuit device 1, this first frequency line of response lineH and this second frequency line of response lineL are all the threshold value of the European telecommunication Bureau of Standards (ETSI) formulation relevant for TS 101 952-2-1 standards in the VDSL2 transfer protocol, wherein this regulation and stipulation frequency response is when 30MHZ is above, its noise should pass through standard in-beginning below the 55dB, only as shown in FIG., known filter circuit 1 frequency response is when 30MHZ, its noise only is-42.093dB, obviously can't be applicable to the standard that the European telecommunication Bureau of Standards is worked out.Moreover, known filter circuit 1 has been used six inductive bank L1-L6, nine capacitor C1-C9 and four resistor R 1-R4 at least, its overall structure institute palpus consumers quantity is too much, for the industrial circle of more and more stressing electronic communication product miniaturization and cost degradation, this known filter circuit 1 usefulness is real inadequate, so necessity of improvement is arranged.
Therefore, how to provide a kind of applicable to European communications agreement and can reduce the filter circuit that produces cost, one of current important topic of reality genus.
Summary of the invention
Because above-mentioned problem, the invention provides a kind of European communications agreement and low yield of meeting and make this filter circuit.
For reaching above-mentioned purpose, the invention provides a kind of filter circuit,
It is made up of a plurality of inductive bank, a plurality of resonant capacitor, a plurality of impedance matching circuit and a plurality of attenuation capacitor, wherein these a plurality of inductive bank are connected electrically between the input and an output of this filter circuit with series system, each resonant capacitor is connected electrically in twos between the inductive bank with parallel way, these a plurality of impedance matching circuits be electrically connected to separately these a plurality of inductive bank one of them, these a plurality of attenuation capacitor be electrically connected to separately these a plurality of impedance matching circuits and these a plurality of inductive bank one of them.
According to above-mentioned conception, this this inductive bank that is electrically connected to this output of this filter circuit can be a common mode and suppresses inductive bank, and these a plurality of inductive bank, a plurality of resonant capacitor, a plurality of impedance matching circuit and a plurality of attenuation capacitor are selected appropriate value in the back as calculated, and make this filter circuit can meet the standard of European communications agreement more fully, and can be by the less elements combination to avoid increasing unnecessary cost.
Description of drawings
Fig. 1 is that the circuit of known filter circuit is formed schematic diagram;
Fig. 2 is the frequency response chart of the filter circuit of Fig. 1;
Fig. 3 forms schematic diagram for the circuit of the described filter circuit of preferred embodiment of the present invention.
Fig. 4 is the frequency response chart of the filter circuit of Fig. 3.
The component symbol explanation:
1,2 filter circuits
L1, L2, L3, L4, L5, L6 bank of inductors
The L7 first inductive bank L8 second inductive bank
L9 the 3rd inductive bank L10 the 4th inductive bank
L11, L21, L31, L41, L51, L61, L71, L81, L91, L101 first winding
L12, L22, L32, L42, L52, L62, L72, L82, L92, L102 second winding
C1, C2, C3, C4, C5, C6, C7, C8, C9, C13, C14 capacitor
The C10 first resonant capacitor C11 second resonant capacitor
C12 the 3rd resonant capacitor C15 first attenuation capacitor
C16 second attenuation capacitor
R1, R2, R3, R4, R5, R6 resistor
Input input output output
LineH first frequency line of response lineL second frequency line of response
LineR actual frequency line of response
Embodiment
Please refer to Fig. 3, is that the circuit of the filter circuit 2 of the embodiment of the invention is formed schematic diagram shown in the figure; As shown in the figure, this filter circuit 2 has an input input and an output output, and between this input input and this output output, include one first inductive bank L7, one second inductive bank L8, one the 3rd inductive bank L9, one the 4th inductive bank L10, one first resonant capacitor C10, one second resonant capacitor C11, one the 3rd resonant capacitor C12, one first impedance matching circuit 10, one second impedance matching circuit 20, one first attenuation capacitor C15 and one second attenuation capacitor C16, wherein these a plurality of inductive bank L7-L10 are connected electrically between this input input and this output out put of this filter circuit 2 with series system, each resonant capacitor C10-C12 is connected electrically in twos between the inductive bank with parallel way, these a plurality of impedance matching circuit 10-20 be electrically connected to separately these a plurality of inductive bank L7-L10 one of them, these a plurality of attenuation capacitor C15-C16 then be electrically connected to separately these a plurality of impedance matching circuit 10-20 and these a plurality of inductive bank L7-L10 one of them.
The input input of this filter circuit 2 comprises two pin contacts, loop (tip, ring), it is electrically connected to a communication line of a communication equipment (not shown), and this output out put also comprises two pin contacts, loop (tip, ring), it can be electrically connected to a switch (not shown), after this filter circuit 2 receives a signal of this communication line, can produce the effect of filtering to the signal frequency of its process, and export this switch to.
These a plurality of inductive bank L7-L10 respectively include one first winding L 71-L101 and one second winding L 72-L102, the first winding L 71-L101 and the second winding L 72-L102 of each inductive bank L7-L10 are set around on the ring-shaped core, thereby form these a plurality of inductive bank L7-L10.In addition, in the middle of this embodiment, this first inductive bank L7, this second inductive bank L8 and the 3rd inductive bank L9 are that a differential mode suppresses inductive bank, and the 4th inductive bank L10 is a common mode inhibition inductive bank, it can provide the effect of filtering noise, and this output out put of the output of the signal after will handling.
This first resonant capacitor C10 is arranged between this first inductive bank L7 and this second inductive bank L8, and the end of this first resonant capacitor C10 is electrically connected to this first winding L 71 and this first winding L 81, and the other end then is electrically connected to this second winding L 72 and this second winding L 82; This second resonant capacitor C11 is arranged between this second inductive bank L8 and the 3rd inductive bank L9, and the end of this second resonant capacitor C11 is electrically connected to this first winding L 81 and this first winding L 91, and the other end then is electrically connected to this second winding L 82 and this second winding L 82; The 3rd resonant capacitor C12 is arranged between the 3rd inductive bank L9 and the 4th inductive bank L10, and the end of the 3rd resonant capacitor C12 is electrically connected to this first winding L 91 and this first winding L 101, and the other end then is electrically connected to this second winding L 92 and this second winding L 102.
This first impedance matching circuit 10 is electrically connected to first winding L 81 of this second inductive bank L8, and it includes a resistor R 5 and a capacitor C13, this resistor R 5 is connected in parallel with this capacitor C13, and this first impedance matching circuit 10 is to be connected in parallel in this first winding L 81 by this capacitor C13.
This second impedance matching circuit 20 is electrically connected to second winding L 82 of this second inductive bank L8, and it includes a resistor R 6 and a capacitor C14, this resistor R 6 is connected in parallel with this capacitor C14, and this second impedance matching circuit 20 is to be connected in parallel in this second winding L 82 by this capacitor C14.
This communication line impedance matching that above-mentioned this first impedance matching circuit 10 and this second impedance matching circuit 20 mainly can be connected with this input input causes signal strength signal intensity to reduce or disturbs nearby lines because of signal reflex avoiding.
This first attenuation capacitor C15 is electrically connected to this capacitor C13 and the 3rd resonant capacitor C12, and this second attenuation capacitor C16 is electrically connected to this capacitor C14 and the 3rd resonant capacitor C12, combination by this two attenuation capacitor C15, C16 can make the noise in the signal partly decay.
Be stressed that especially at this,, can make the frequency response of this filter circuit 2 more meet the standard of European communications agreement by suitably calculating the value choose each element in above-mentioned this filter circuit 2, in the suitable selected value of this each element of giving an example:
The inductance value of first inductive bank: 2.5Mh;
The inductance value of second inductive bank: 7.0mH;
The inductance value of the 3rd inductive bank: 2.0mH;
The inductance value of the 4th inductive bank: 600 μ H;
The capacitance of this first resonant capacitor: 12nF;
The capacitance of this second resonant capacitor: 18nF;
The capacitance of the 3rd resonant capacitor: 27nF;
The resistance value of this resistor of this first impedance matching circuit: 91 Ω;
The capacitance of this capacitor of this first impedance matching circuit: 270nF;
The resistance value of this resistor of this second impedance matching circuit: 91 Ω;
The capacitance of this capacitor of this second impedance matching circuit: 270nF;
The capacitance of this first attenuation capacitor: 5.6nF;
The capacitance of this second attenuation capacitor: 5.6nF.
See also shown in Figure 4, frequency response chart for the filter circuit 2 of Fig. 3, as shown in the figure, the actual frequency line of response lineR that this filter circuit 2 of the present invention is produced, it is located between this first frequency line of response lineH and this second frequency line of response lineL, does not exceed the threshold value of this two frequency response line lineH, lineL, as shown in the figure, filter circuit 1 frequency response is when 30MHZ, and its noise is-62.583dB, and can meet noise should be in-standard below the 55dB.That is to say that the frequency response of above-mentioned this filter circuit 2 can meet the standard of European Region communication protocol, uses and can provide to the European market; Moreover the present invention is by less elements, and can delete unnecessary cost expenditure, is one to benefit greatly for the miniaturization of electronic communication product and cost degradation, can be described as the design of a progressive in fact.
The above only is an illustrative, but not is restricted person.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the accompanying claim its equivalent modifications of carrying out or change.

Claims (16)

1. filter circuit, it comprises:
A plurality of inductive bank are connected electrically in series system between the input and an output of this filter circuit;
A plurality of resonant capacitors, wherein each resonant capacitor is connected electrically in twos between the inductive bank with parallel way;
A plurality of impedance matching circuits, be electrically connected to separately these a plurality of inductive bank one of them; And
A plurality of attenuation capacitor, be electrically connected to separately these a plurality of impedance matching circuits and these a plurality of inductive bank one of them.
2. filter circuit as claimed in claim 1, wherein these a plurality of inductors are that a differential mode suppresses inductive bank.
3. filter circuit as claimed in claim 1, this inductive bank that wherein is connected in this output of this filter circuit are that a common mode suppresses inductive bank.
4. filter circuit as claimed in claim 1, wherein this impedance matching circuit is made up of a resistor and electric capacity resistance.
5. filter circuit as claimed in claim 1, wherein this filter circuit comprises one first inductive bank, one second inductive bank, one the 3rd inductive bank and one the 4th inductive bank, and this first inductive bank is electrically connected to this input, and the 4th inductive bank is electrically connected to this output.
6. filter circuit as claimed in claim 5, wherein this filter circuit comprises one first resonant capacitor, one second resonant capacitor and one the 3rd resonant capacitor, this first resonant capacitor is attempted by between this first inductive bank and this second inductive bank, this second resonant capacitor is attempted by between this second inductive bank and the 3rd inductive bank, and the 3rd resonant capacitor is attempted by between the 3rd inductive bank and the 4th inductive bank.
7. filter circuit as claimed in claim 6, wherein this filter circuit comprises one first impedance matching circuit and one second impedance matching circuit, this first impedance matching circuit is electrically connected to a side of this second inductive bank, and this second impedance matching circuit is electrically connected to the opposite side of this second inductive bank.
8. filter circuit as claimed in claim 7, wherein this filter circuit comprises one first attenuation capacitor and one second attenuation capacitor, this first attenuation capacitor is electrically connected to the 3rd inductive bank and this first impedance matching circuit, and this second attenuation capacitor is electrically connected to the 3rd inductive bank and this second impedance matching circuit.
9. filter circuit as claimed in claim 5, wherein the 4th inductive bank is the common mode inhibition inductive bank, this first and second and three inductive bank be that differential mode suppresses inductive bank.
10. filter circuit as claimed in claim 5, wherein the inductance value of this first inductive bank is 2.5mH, and the inductance value of this second inductive bank is 7.0mH, and the inductance value of the 3rd inductive bank is 2.0mH, and the inductance value of the 4th inductive bank is 600 μ H.
11. filter circuit as claimed in claim 6, wherein the capacitance of this first resonant capacitor is 12nF, and the capacitance of this second resonant capacitor is 18nF, and the capacitance of the 3rd resonant capacitor is 27nF.
12. filter circuit as claimed in claim 7, wherein this first impedance matching circuit and this second impedance matching circuit respectively comprise a resistor and a capacitor, and the resistance value of this resistor is 91 Ω, and the capacitance of this capacitor is 270nF.
13. filter circuit as claimed in claim 8, wherein the capacitance of this first attenuation capacitor is 5.6nF, and the capacitance of this second attenuation capacitor is 5.6nF.
14. filter circuit as claimed in claim 1, wherein this input of this filter circuit is electrically connected to a phone line end of a communication equipment.
15. filter circuit as claimed in claim 1, wherein this output of this filter circuit is electrically connected to a switch.
16. filter circuit as claimed in claim 1, wherein these a plurality of inductive bank respectively include one first winding and one second winding, and first winding of each inductive bank and second winding are set around on the ring-shaped core.
CNA2006101717341A 2006-12-19 2006-12-19 Wave filter circuit Pending CN101207368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2006101717341A CN101207368A (en) 2006-12-19 2006-12-19 Wave filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2006101717341A CN101207368A (en) 2006-12-19 2006-12-19 Wave filter circuit

Publications (1)

Publication Number Publication Date
CN101207368A true CN101207368A (en) 2008-06-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101717341A Pending CN101207368A (en) 2006-12-19 2006-12-19 Wave filter circuit

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728071B (en) * 2008-10-30 2012-05-30 三星电机株式会社 Transformer
CN103208975A (en) * 2012-01-17 2013-07-17 立积电子股份有限公司 Matching circuit system
CN104702238A (en) * 2015-04-03 2015-06-10 徐园园 Impedance matching circuit
CN107196622A (en) * 2017-04-21 2017-09-22 北京海尔集成电路设计有限公司 A kind of constant attenuation factor of input impedance

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728071B (en) * 2008-10-30 2012-05-30 三星电机株式会社 Transformer
CN103208975A (en) * 2012-01-17 2013-07-17 立积电子股份有限公司 Matching circuit system
CN103208975B (en) * 2012-01-17 2016-09-21 立积电子股份有限公司 Matching circuit system
CN104702238A (en) * 2015-04-03 2015-06-10 徐园园 Impedance matching circuit
CN107196622A (en) * 2017-04-21 2017-09-22 北京海尔集成电路设计有限公司 A kind of constant attenuation factor of input impedance
CN107196622B (en) * 2017-04-21 2021-05-18 北京海尔集成电路设计有限公司 Attenuation system with constant input impedance

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Open date: 20080625