CN218603462U

CN218603462U - Duplexer and duplexer structure

Info

Publication number: CN218603462U
Application number: CN202222478359.2U
Authority: CN
Inventors: 王志华; 林亚梅; 刘季超; 肖倩; 胡志明; 蒙腾奥
Original assignee: Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
Current assignee: Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
Priority date: 2022-09-19
Filing date: 2022-09-19
Publication date: 2023-03-10
Anticipated expiration: 2032-09-19

Abstract

The application provides a duplexer and a duplexer structure, wherein the duplexer comprises a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port and a grounding port; the high-pass filter circuit comprises a first LC resonance unit and a capacitance unit connected between the input port and the first output port in series, and the first LC resonance unit is connected between the first output port and the ground port in series; the low-pass filter circuit comprises a second LC resonance unit and an inductance unit connected between the input port and the second output port in series, and the second LC resonance unit is connected between the second output port and the ground port in series. The duplexer provided by the embodiment of the application solves the problem that the traditional duplexer is poor in out-of-band rejection performance.

Description

Duplexer and duplexer structure

Technical Field

The application belongs to the technical field of duplexers, and particularly relates to a duplexer and a duplexer structure.

Background

The duplexer is a main accessory in a communication system, and has the function of isolating a transmitting signal from a receiving signal and ensuring that the receiving and the transmitting can work normally at the same time. The out-of-band rejection is an important index for showing the performance of the duplexer, and the traditional duplexer generally needs to install a metal shield on the outer side to improve the out-of-band rejection of the duplexer, but the out-of-band rejection performance of the traditional duplexer is poor.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a duplexer and a duplexer structure, and can solve the problem that the out-of-band rejection performance of the traditional duplexer is poor.

In a first aspect, an embodiment of the present application provides a duplexer, including a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port, and a ground port;

the high-pass filter circuit comprises a first LC resonance unit and a capacitance unit connected between the input port and the first output port in series, and the first LC resonance unit is connected between the first output port and the ground port in series;

the low-pass filter circuit comprises a second LC resonance unit and an inductance unit connected between the input port and the second output port in series, and the second LC resonance unit is connected between the second output port and the ground port in series.

In a possible implementation manner of the first aspect, the first LC resonant unit includes a first inductor and a first capacitor, a first end of the first inductor is connected to the first output port, a second end of the first inductor is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to the ground port.

In a possible implementation manner of the first aspect, the second LC resonant unit includes a second inductor and a second capacitor, a first end of the second inductor is connected to the second output port, a second end of the second inductor is connected to a first end of the second capacitor, and a second end of the second capacitor is connected to the ground port.

In a possible implementation manner of the first aspect, the capacitance unit includes a third capacitor, and the third capacitor is connected in series between the input port and the first output port.

In a possible implementation manner of the first aspect, the inductance unit includes a third inductance, and the third inductance is connected in series between the input port and the second output port.

In a second aspect, an embodiment of the present application provides a duplexer structure, including a substrate, a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port, and a ground port, where the high-pass filter circuit includes a first LC resonance unit and a capacitor unit connected in series between the input port and the first output port, and the first LC resonance unit is connected in series between the first output port and the ground port; the low-pass filter circuit comprises a second LC resonance unit and an inductance unit connected between the input port and the second output port in series, and the second LC resonance unit is connected between the second output port and the ground port in series;

the base body includes a plurality of circuit layers stacked, and the first LC resonance unit, the second LC resonance unit, the capacitance unit, the inductance unit, the input port, the first output port, the second output port, and the ground port are respectively provided on the plurality of circuit layers.

In a possible implementation manner of the second aspect, the first LC resonant unit includes a first inductor and a first capacitor, a first end of the first inductor is connected to the first output port, a second end of the first inductor is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to the ground port;

the two electrodes of the first capacitor are arranged on different circuit layers, and the first inductor is arranged on one or more circuit layers.

In a possible implementation manner of the second aspect, the second LC resonant unit includes a second inductor and a second capacitor, a first end of the second inductor is connected to the second output port, a second end of the second inductor is connected to a first end of the second capacitor, and a second end of the second capacitor is connected to the ground port;

the two electrodes of the second capacitor are arranged on different circuit layers, and the second inductor is arranged on one or more circuit layers.

In a possible implementation manner of the second aspect, the material of the substrate is a ceramic dielectric.

In one possible implementation manner of the second aspect, the inductance in the inductance unit, the inductance in the first LC resonance unit, and the inductance in the second LC resonance unit are all in a spiral shape.

Compared with the prior art, the embodiment of the application has the advantages that:

the duplexer provided by the embodiment of the application comprises a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port and a ground port, wherein the input port is used for receiving an input signal. The high-pass filter circuit comprises a first LC resonance unit and a capacitance unit connected between the input port and the first output port in series, and the first LC resonance unit is connected between the first output port and the ground port in series. The capacitance unit is used for filtering low-frequency signals in the input signals, and the residual high-frequency signals in the input signals are output through the first output port. The first LC resonance unit is used for filtering out signals with the same resonance frequency as the first LC resonance unit in the high-frequency signals, so that the high-frequency signals output by the first output port are more accurate, and the out-of-band rejection performance of the high-pass filter circuit is improved. The low-pass filter circuit comprises a second LC resonance unit and an inductance unit connected between the input port and the second output port in series, and the second LC resonance unit is connected between the second output port and the ground port in series. The inductance unit is used for filtering high-frequency signals in the input signals, and residual low-frequency signals in the input signals are output through the second output port. The second LC resonance unit is used for filtering out signals with the same resonance frequency as the second LC resonance unit in the low-frequency signals, so that the low-frequency signals output by the second output port are more accurate, and the out-of-band rejection performance of the low-pass filter circuit is improved. The duplexer provided by the embodiment of the application improves the out-of-band rejection performance of the duplexer by arranging the first LC resonance unit and the second LC resonance unit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic circuit diagram of a duplexer provided in an embodiment of the present application;

fig. 2 is a port schematic diagram of a duplexer according to an embodiment of the present application;

fig. 3 is a schematic circuit diagram of a duplexer according to an embodiment of the present application;

fig. 4 is an overall structural diagram of a duplexer according to an embodiment of the present application.

In the figure: 01. a substrate; 10. a high-pass filter circuit; 20. a low-pass filter circuit; 30. a first LC resonance unit; 40. a second LC resonance unit; 50. a capacitive unit; 60. an inductance unit.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in the specification and appended claims, the term "if" may be interpreted contextually as "when 8230that" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.

In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.

Fig. 1 shows a schematic circuit diagram of a duplexer provided in an embodiment of the present application. Referring to fig. 1, the duplexer includes a high-pass filter circuit 10, a low-pass filter circuit 20, an input port P0, a first output port P1, a second output port P2, and a ground port GND; the high-pass filter circuit 10 includes a first LC resonance unit 30 and a capacitance unit 50 connected in series between the input port P0 and the first output port P1, and the first LC resonance unit 30 is connected in series between the first output port P1 and the ground port GND; the low pass filter circuit 20 includes a second LC resonance unit 40 and an inductance unit 60 connected in series between the input port P0 and the second output port P2, and the second LC resonance unit 40 is connected in series between the second output port P2 and the ground port GND.

Specifically, the input port P0 is configured to receive an input signal, the capacitance unit 50 is configured to filter a low-frequency signal in the input signal, and a remaining high-frequency signal in the input signal is output from the first output port P1. The first LC resonant unit 30 is configured to filter a signal in the high frequency signal, where the signal has the same resonant frequency as that of the first LC resonant unit 30, so that the high frequency signal output by the first output port P1 is more accurate, and the out-of-band rejection performance of the high-pass filter circuit 10 is improved.

The inductance unit 60 is used for filtering out a high frequency signal in the input signal, and a remaining low frequency signal in the input signal is output from the second output port P2. The second LC resonance unit 40 is configured to filter a signal having the same resonance frequency as the second LC resonance unit 40 from the low-frequency signal, so that the low-frequency signal output by the second output port P2 is more accurate, and the out-of-band rejection performance of the low-pass filter circuit 20 is improved. The duplexer provided by the embodiment of the application improves the out-of-band rejection performance of the duplexer by arranging the first LC resonance unit 30 and the second LC resonance unit 40.

Illustratively, assuming that a signal having a signal frequency between 3 and 30MHz is a high frequency signal and a signal lower than 3MHz is a low frequency signal, the resonance frequency of the first LC resonance unit 30 is between 15 and 20 MHz. If the frequency of the signal input from the input port P0 is between 1 MHz and 20MHz, the low-frequency signal smaller than 3MHz is filtered out by the effect of passing the high-frequency and low-frequency impedance through the capacitance unit 50, and the high-frequency signal with the frequency between 3MHz and 20MHz is output from the first output port P1. And then the signal with the frequency between 15 and 20MHz is filtered by the first LC resonance unit 30, at this time, the frequency of the signal output from the high-pass output end is 3 to 15MHz, that is, the frequency of the signal required by the user is 3 to 15MHz. Therefore, the high-frequency signal output by the first output port P1 is more accurate, and the out-of-band rejection performance of the high-pass filter circuit 10 is improved.

Assuming that a signal having a signal frequency between 3 and 30MHz is a high frequency signal and a signal lower than 3MHz is a low frequency signal, the resonance frequency of the second LC resonance unit 40 is between 1 and 1.5 MHz. If the frequency of the signal input by the input port P0 is between 1 and 20MHz, the high-frequency signal larger than 3MHz is filtered out under the action of the low-frequency resistance and the high-frequency resistance of the first inductor L1, and the low-frequency signal with the frequency between 1 and 3MHz is output at the second output port P2. And then the signal with the frequency of 1-1.5 MHz is filtered by the second LC resonance unit 40, at this time, the frequency of the signal output from the low-pass output end is 1.5-3 MHz, namely, the frequency of the signal required by the user is 1.5-3 MHz. Therefore, the low-frequency signal output by the second output port P2 is more accurate, and the out-of-band rejection performance of the low-pass filter circuit 20 is improved.

In an embodiment of the present application, the first LC resonant unit 30 includes a first inductor L1 and a first capacitor C1, a first end of the first inductor L1 is connected to the first output port P1, a second end of the first inductor L1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to the ground port GND.

Specifically, the first inductor L1 and the first capacitor C1 are connected in series, at this time, the sum of the impedance of the first inductor L1 and the impedance of the first capacitor C1 is zero, and a short circuit is formed between the first output port P1 and the ground port GND, so that a first transmission zero point is formed at the second end of the first capacitor C1, attenuation of an input signal is increased, and out-of-band rejection performance of the high-pass filter circuit 10 is further improved.

The impedance of the first inductor L1 is j ω L ₁ Impedance of the first capacitor C1Is composed of

The impedance of the first inductor L1 is j ω L ₁ And the impedance of the first capacitor C1 is

Adding to obtain a sum of impedances

Calculated after simplification

Transmission zero refers to a frequency point at which the transfer function is equal to zero. Increasing the number of transmission zeros increases the attenuation of the input signal and improves the out-of-band rejection performance of the high-pass filter circuit 10. Those skilled in the art can set a plurality of resonant units according to requirements, and increase the number of transmission zeros, thereby improving the out-of-band rejection performance of the high-pass filter circuit 10.

In an embodiment of the present application, the second LC resonant unit 40 includes a second inductor L2 and a second capacitor C2, a first end of the second inductor L2 is connected to the second output port P2, a second end of the second inductor L2 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the ground port GND.

Specifically, the second inductor L2 and the second capacitor C2 are connected in series, at this time, the sum of the impedance of the second inductor L2 and the impedance of the second capacitor C2 is zero, and a short circuit is formed between the second output port P2 and the ground port GND, so that a second transmission zero point is formed at the second end of the second capacitor C2, attenuation of an input signal is increased, and out-of-band rejection performance of the low-pass filter circuit 20 is further improved.

The impedance of the second inductor L2 is j ω L ₂ The impedance of the second capacitor C2 is

At this time, the impedance j ω L of the second inductor L2 ₂ And the impedance of the second capacitor C2

Adding to obtain the sum of impedances of

Calculated after simplification

Transmission zero refers to a frequency point at which the transfer function is equal to zero. Increasing the number of transmission zeros increases the attenuation of the input signal and improves the out-of-band rejection of the low pass filter circuit 20. Those skilled in the art can set a plurality of resonant units according to requirements, and increase the number of transmission zeros, thereby improving the out-of-band rejection performance of the low-pass filter circuit 20.

In one embodiment of the present application, the capacitor unit 50 includes a third capacitor C3, and the third capacitor C3 is connected in series between the input port P0 and the first output port P1.

Specifically, the third capacitor C3 is connected in series between the input port P0 and the first output port P1, so that the low-frequency signal in the input signal can be filtered out by using the effect of the third capacitor C3 in passing high-frequency and low-frequency, and the remaining high-frequency signal in the input signal is output from the first output port P1. The designer can select the capacitors with corresponding models and parameters according to actual conditions so as to achieve the effect of passing high frequency and blocking low frequency. Meanwhile, the designer may select the number of capacitors according to actual conditions, for example, 1, 2 or other number of capacitors may be selected to be connected in series between the input port P0 and the first output port P1 to form the capacitor unit 50. In the embodiment of the application, one capacitor is selected to be connected in series between the input port P0 and the first output port P1, so that the design requirement can be met, and the effect of high-frequency resistance and low-frequency resistance is achieved.

In one embodiment of the present application, the inductance unit 60 includes a third inductance C3, and the third inductance C3 is connected in series between the input port P0 and the second output port P2.

Specifically, the third inductor C3 is connected in series between the input port P0 and the second output port P2, so that the high-frequency signal in the input signal can be filtered by using the function of low-frequency resistance and high-frequency resistance of the third inductor C3, and the remaining low-frequency signal in the input signal is output from the second output port. The designer can select the inductors with corresponding models and parameters according to actual conditions so as to achieve the effect of passing low frequency resistance and high frequency resistance. Meanwhile, the designer may select the number of inductors according to the actual situation, for example, 1, 2 or another number of inductors are selected to be connected in series between the input port P0 and the second output port P2 to form the inductor unit 60. And in this application embodiment, choose an inductance to concatenate between input port P0 and second output port P2 for use, can satisfy the design demand, reach the effect of leading to the low frequency and hinder the high frequency, for the traditional duplexer that uses a plurality of inductances, the inductance that this application used is small in quantity, and is small, is favorable to the miniaturized design of duplexer.

It should be noted that the third inductor L3 is formed by multiple circuit layers, so that a coupling phenomenon occurs between each circuit layer, and the coupled capacitors are connected in parallel to two ends of the third inductor L3, so that the third inductor L3 can couple out the fourth capacitor C4 by itself, and the third inductor L3 and the fourth capacitor C4 are connected in parallel, and the capacitance value of the fourth capacitor C4 is equal to the sum of the coupled capacitance values of each circuit layer. At this time, the sum of the admittance of the third inductor L3 and the admittance of the fourth capacitor C4 is zero, and an open circuit is formed between the second output port P2 and the input port P0, so that a third transmission zero is formed at the second end of the third inductor L3, the attenuation of the input signal is increased, and the out-of-band rejection performance of the low-pass filter circuit 20 is further improved.

Illustratively, the third inductance L3 has an admittance of

The admittance of the fourth capacitor C4 is j ω C ₄ At this time, the third inductance L3 admittance is

And the admittance j ω C of the fourth capacitor C4 ₄ Adding to give a sum of admittances of

Calculated after simplification

In an embodiment of the present application, the duplexer structure includes a substrate 01, a high-pass filter circuit 10, a low-pass filter circuit 20, an input port P0, a first output port P1, a second output port P2, and a ground port GND, where the high-pass filter circuit 10 includes a first LC resonant unit 30 and a capacitor unit 50 connected in series between the input port P0 and the first output port P1, and the first LC resonant unit 30 is connected in series between the first output port P1 and the ground port GND; the low pass filter circuit 20 includes a second LC resonance unit 40 and an inductance unit 60 connected in series between the input port P0 and the second output port P2, and the second LC resonance unit 40 is connected in series between the second output port P2 and the ground port GND; the base 01 includes a plurality of circuit layers stacked, and the first LC resonance unit 30, the second LC resonance unit 40, the capacitance unit 50, the inductance unit 60, the input port P0, the first output port P1, the second output port P2, and the ground port GND are respectively provided on the plurality of circuit layers.

Specifically, because the first LC resonant unit 30, the second LC resonant unit 40, the capacitor unit 50, the inductor unit 60, the input port P0, the first output port P1, the second output port P2, and the ground port GND are respectively disposed on multiple circuit layers, the first LC resonant unit 30 and the capacitor unit 50 are vertically distributed, so that the structure of the high-pass filter circuit 10 is more compact, the volume is reduced, and the miniaturized design of the duplexer is facilitated; the second LC resonance unit 40 and the inductance unit 60 are vertically distributed, so that the structure of the low-pass filter circuit 20 is more compact, the size is reduced, and the miniaturization design of the duplexer is facilitated.

It should be noted that fig. 2 shows a port schematic diagram of a duplexer provided in an embodiment of the present application, and refer to fig. 2. The duplexer port includes an input port P0, a first output port P1, a second output port P2, and ground ports GND1, GND2, and GND3.

The input port P0, the first output port P1, the second output port P2 and the grounding ports GND1, GND2 and GND3 are all formed by three-layer structures and comprise inner-layer silver, middle-layer nickel and outermost-layer tin.

In an embodiment of the present application, the first LC resonant unit 30 includes a first inductor L1 and a first capacitor C1, a first end of the first inductor L1 is connected to the first output port P1, a second end of the first inductor L1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to the ground port GND 3; the two electrodes of the first capacitor C1 are disposed on different circuit layers, and the first inductor L1 is disposed on one or more circuit layers. The second LC resonant unit 40 includes a second inductor L2 and a second capacitor C2, a first end of the second inductor L2 is connected to the second output port P2, a second end of the second inductor L2 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the ground port GND 2; the two electrodes of the second capacitor C2 are arranged on different circuit layers and the second inductor L2 is arranged on one or more circuit layers.

In particular, as shown in fig. 3-4. The circuit layer has nine layers in total and is of a laminated structure, the first layer, the third layer and the fifth layer are all metal plates C0, the first layer to the fifth layer form a first capacitor C1 and a second capacitor C2, the sixth layer forms a first inductor L1 and a second inductor L2, and the seventh layer, the eighth layer and the ninth layer form a third inductor L3 and a third capacitor C3.

A first layer, printing a first layer of metal plate 1-C0 on the ceramic medium, wherein the metal 1-C0 is respectively connected with a first grounding terminal GND1, a second grounding terminal GND2 and a third grounding terminal GND 3; a second layer, printing a first capacitor 2-C1 and a second capacitor 2-C2 on the ceramic dielectric, wherein the first capacitor 2-C1 is connected with the metal column D1, and the second capacitor 2-C2 is connected with the metal column D2; a third layer, printing a second layer of metal plate 3-C0 on the ceramic medium, wherein the metal plate 3-C0 is respectively connected with a first grounding terminal GND1, a second grounding terminal GND2 and a third grounding terminal GND3, and the through hole 3-V1 is connected with the through hole 1-V1 through a connecting wire; a fourth layer, printing a first capacitor 4-C1 and a second capacitor 4-C2 on the ceramic dielectric, wherein a first end of the first capacitor 4-C1 is connected with the metal column D1, a second end of the first capacitor 4-C1 is connected with a third grounding terminal GND3, a first end of the second capacitor 4-C2 is connected with the metal column D2, and a second end of the second capacitor 4-C2 is connected with the second grounding terminal GND 2; a fifth layer, printing a third layer of metal plate 5-C0 on the ceramic medium, wherein the metal plate 5-C0 is respectively connected with a first grounding terminal GND1, a second grounding terminal GND2 and a third grounding terminal GND3, and the through hole 5-V1 is connected with the through hole 3-V1 through a connecting wire; a sixth layer, printing a first inductor 6-L1 and a second inductor 6-L2 on the ceramic medium, wherein a first end of the first inductor 6-L1 is connected with the metal column D1, a second end of the first inductor 6-L1 is connected with the through hole 6-V4 through a connecting wire, a third end of the first inductor 6-L1 is connected with the first output port P1 through the connecting wire, a first end of the second inductor 6-L2 is connected with the metal column D2, a second end of the second inductor 6-L2 is connected with the through hole 6-V3 through the connecting wire, and a third end of the second inductor 6-L2 is connected with the second output port P2 through the connecting wire; a seventh layer, printing a third inductor 7-L3 and a third capacitor 7-C3 on the ceramic medium, wherein the third inductor 7-L3 is connected with the through hole 7-V3 through a connecting wire, the through hole 7-V3 is connected with the through hole 6-V3 through a connecting wire, the first end of the third capacitor 7-C3 is connected with the through hole 7-V4 through a connecting wire, the second end of the third capacitor 7-C3 is connected with the first output port P1 through a connecting wire, and the through hole 7-V4 is connected with the through hole 6-V4 through a connecting wire; printing a third inductor 8-L3 and a third capacitor 8-C3 on the ceramic medium, wherein the third inductor 8-L3 is connected with the through hole 8-V3 through a connecting wire, the through hole 8-V3 is connected with the through hole 7-V3 through a connecting wire, the first end of the third capacitor 8-C3 is connected with the through hole 8-V4 through a connecting wire, the second end of the third capacitor 8-C3 is connected with the input port P0 through a connecting wire, and the through hole 8-V4 is connected with the through hole 7-V4 through a connecting wire; and a ninth layer, printing a third inductor 9-L3 and a third capacitor 9-C3 on the ceramic medium, wherein the first end of the third inductor 9-L3 is connected with the input port P0 through a connecting wire, the second end of the third inductor 9-L3 is connected with the second output port P2 through a connecting wire, the third inductor 9-L3 is connected with the through hole 8-V3 through a connecting wire, the third capacitor 9-C3 is connected with the first output port P1 through a connecting wire, and the third capacitor 9-C3 is connected with the through hole 8-V4 through a connecting wire. The circuit layer has nine layers in a laminated structure, which is beneficial to the miniaturization design of the duplexer.

In one embodiment of the present application, the substrate 01 is made of a ceramic dielectric.

Specifically, the Ceramic dielectric is an LTCC (Low Temperature Co-fired Ceramic) dielectric. The LTCC technology has the characteristics of high reliability, high inhibition, small volume, light weight, easiness in integration, low cost, suitability for large-scale production and the like, the dielectric medium is not easy to oxidize, electroplating protection is not needed, and the packaging size is greatly reduced. Therefore, the ceramic dielectric is selected as the material of the substrate 01, which is beneficial to the miniaturization design of the duplexer.

It should be noted that, a designer can select a ceramic medium with a small relative dielectric constant and a small dielectric loss according to actual conditions, so that the insertion loss can be reduced, and the out-of-band rejection capability of the passband can be improved. For example, a ceramic dielectric with a relative dielectric constant of 5.0 and a dielectric loss tan α of 0.001 or less may be selected according to actual conditions to meet the requirements of small electronic products for duplexers.

In one embodiment of the present application, the inductance in the inductance unit 60, the inductance in the first LC resonance unit 30, and the inductance in the second LC resonance unit 40 are all in a spiral shape.

Specifically, designers can select inductors with corresponding models and parameters according to actual conditions so as to achieve the effect of passing low frequency resistance and high frequency resistance. Meanwhile, the shape of the inductor can be selected by a designer according to actual conditions, such as a spiral shape, an iron core inductor or other inductors. And in this application embodiment, all select the heliciform inductance for use when designing the duplexer, for the duplexer of traditional use other inductances, every layer of inductance that this application used is the stromatolite design, and is small, is favorable to the miniaturized design of duplexer.

Note that the capacitance in the capacitance unit 50, the capacitance in the first LC resonance unit 30, and the capacitance in the second LC resonance unit 40 are all interdigital capacitances.

Illustratively, the interdigital Capacitor may be a VIC (vertical-interleaved-Capacitor).

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present application, and they should be construed as being included in the present application.

Claims

1. A duplexer is characterized by comprising a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port and a ground port;

2. The duplexer of claim 1, wherein the first LC resonant unit comprises a first inductor and a first capacitor, a first end of the first inductor is connected to the first output port, a second end of the first inductor is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to the ground port.

3. The duplexer of claim 1, wherein the second LC resonant unit comprises a second inductor and a second capacitor, a first end of the second inductor is connected to the second output port, a second end of the second inductor is connected to a first end of the second capacitor, and a second end of the second capacitor is connected to the ground port.

4. The duplexer of claim 1, wherein the capacitance unit comprises a third capacitance connected in series between the input port and the first output port.

5. The duplexer of claim 1, wherein the inductance unit comprises a third inductance connected in series between the input port and the second output port.

6. A duplexer structure is characterized by comprising a base body, a high-pass filter circuit, a low-pass filter circuit, an input port, a first output port, a second output port and a ground port, wherein the high-pass filter circuit comprises a first LC resonance unit and a capacitor unit connected between the input port and the first output port in series, and the first LC resonance unit is connected between the first output port and the ground port in series; the low-pass filter circuit comprises a second LC resonance unit and an inductance unit connected between the input port and the second output port in series, and the second LC resonance unit is connected between the second output port and the ground port in series;

7. The duplexer structure according to claim 6, wherein the first LC resonant unit includes a first inductor and a first capacitor, a first end of the first inductor is connected to the first output port, a second end of the first inductor is connected to a first end of the first capacitor, and a second end of the first capacitor is connected to the ground port;

8. The duplexer structure according to claim 6, wherein the second LC resonant cell includes a second inductor and a second capacitor, a first end of the second inductor is connected to the second output port, a second end of the second inductor is connected to a first end of the second capacitor, and a second end of the second capacitor is connected to the ground port;

9. The duplexer structure according to claim 6, wherein the substrate is made of a ceramic dielectric.

10. The duplexer structure of claim 6, wherein the inductance in the inductance unit, the inductance in the first LC resonance unit, and the inductance in the second LC resonance unit are each in the shape of a spiral.