CA2418123A1 - Universal power converter - Google Patents
Universal power converter Download PDFInfo
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- CA2418123A1 CA2418123A1 CA 2418123 CA2418123A CA2418123A1 CA 2418123 A1 CA2418123 A1 CA 2418123A1 CA 2418123 CA2418123 CA 2418123 CA 2418123 A CA2418123 A CA 2418123A CA 2418123 A1 CA2418123 A1 CA 2418123A1
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- power converter
- universal power
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
A universal power converter includes a clock input supplying a delay network for producing a delay at the positive and negative clock transitions and a signal input accepting a pulse width modulated signal, a logic circuitry to combine the delays with the signal so as to produce a low and high limit for the pulse duration of the signal, a shut down logic that protects the output devices from destruction, a second set of delay networks to produce a turn on delay for the output devices, a switched current source to drive the upper output device, a pair of capacitive level shifters driving a pair of gate drive buffers usually with substantially higher operating voltage in order to ensure the full enhancement of the output switching devices without degradation in speed, and a voltage sensor to sample the current across the output device initiating a shut down condition via a monostable multi-vibrator in the event that safe current limit is exceeded.
Description
BACKGROUND OF THE INVENTION
1. Field ofthe Invention The present invemion relates to power converters and more directly to those utilizing bridge configuration of same type of switching elements, i.e. N-channel MOSFETs, and more specifically to power converters having very high speed capability combined with very high voltage and power.
1. Field ofthe Invention The present invemion relates to power converters and more directly to those utilizing bridge configuration of same type of switching elements, i.e. N-channel MOSFETs, and more specifically to power converters having very high speed capability combined with very high voltage and power.
2. Description of the Prior Art In power conversion the bridge configuration is the one that can be used in an extremely large number of applications including those that use pulse width modulation to amplify low frequency signals at high e~ciency.
The applications can be divided into following major categories: AC to DC, DC
to DC, DC to AC, and AC to AC converters.
The most common approach would be to choose a standard high side drive, include a dead zone processing circuit to avoid shoot through and use a series low valued resistor between the supply and the switching device for current sensing. It turns out that for each different application a new design needs to be created with additional waste of engineering time. Also, the prior art solutions above 100V supply voltage have so much variation in propagational delay that direct paralleling of these solutions is not permitted. In the case of a pulse width modulation input signal at modulation extreme, most solutions utilizing a bootstrap circuit will fall apart due to the finite value which the holdup capacitor may have.
Also, chip solutions have to deal with the quadratic power loss increase as a function of operating voltage at a given frequency. The series current sensing resistor, especially at higher power, becomes very troublesome, not just as a result of the extra heat, but also the increase of ESL of the bypassing circuit.
Due to the high dv/dt and di/dt involved in high speed, high power circuitry, the design of the printed circuit board becomes a major task for accomplishing a sound design.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of this invention is to provide a topology for a universal power converter free from the defects encountered in the prior art bridge mode power converters. Another object of the invention is to provide a method of constructing a power converter of the widest possible use without fundamental change in the topology or even in the printed circuit board design, i.e. to enable the bridge mode converter to be truly universal use. In accordance with the present invention, a universal power converter is provided having a well defined, very low propagational delay, typically 4 times less the conventional solutions, to enable direct paralleling of converters without the need for the reduction of frequency of operation, having a well defined limit in minimum and maximum duty cycle in the event that the input signal has a duty cycle variation of 0 to 100 %, and also having a lossless current sensing method that tracks switching device on resistance change versus temperature to ensure a safe over current protection level at all allowable temperatures without dissipating extra power or introducing any inductance to the circuit. Yet another advantage ofthe present invention is that the same printed circuit board can be used for power levels of a few hundred watts to several kilowatts economically by simply reselecting the devices. The universal power converter of the present invention has myriad applications ranging from high fidelity audio to high power miniature welders, battery chargers, etc.
BRIEF DESCRIPTION OF DRAW INGS
FIG. 1 is a schematic circuit diagram showing a prior art power converter;
FIG. 2 is a schematic circuit diagram showing an example of the universal power converter according to the present invention; and FIGS. 3A to 3H are waveform diagrams used for explaining the operation of the example of the invention shown in FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In order to better understand the present invention a prior art power converter will be described with reference to FIG.1 which is a half bridge power converter building block.
The PWM signal is applied to signal input terminal 1 which is also the input for input buffer 2.
The output of input buffer 2 is then connected to upper delay network 3 and lower delay network 4. The outputs of upper and lower delay networks 3 and 4, respectively, are connected to inputs of high/low side drive and shut down circuit 5. The upper drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of the upper switching element 6. The lower drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of lower switching element 7.
Current sensing resistor 8 is connected between supply terminal of the lower switching element 7 and negative DC supply 12 and the junction is then fed to the shut down input of high/low side drive circuit 5.
Bootstrap capacitor 9 is connected to high/low side drive and shut down circuit 5 to supply power to the upper switching element 6 when it is turned on. The output terminal of upper switching element 6 is connected to the positive DC
supply 10. The output terminal of upper switching element 6 and output terminal of lower switching element 7 are connected together to output terminal 11.
With the prior art power converter shown in FIG. 1, if the PWM signal applied to signal input terminal 1 exceeds 100% duty cycle, the upper switching element 6 may lose its supply, which is usually stored in bootstrap capacitor 9, causing severe distortion.
The dead zone protection delay networks 3 and 4 are supplying the signal for the upper and lower drive outputs of high/low side drive and shut down circuit 5. This results in a propagational delay of turn offofthe upper and lower switching elements 6 and 7, respectively, as high as 100 nanoseconds with large variation in operating conditions and from device to device. Therefore, paralleling of such power converters is only possible if the dead zones are selected very high which would impair the quality of the low frequency signal to be reproduced.
Current sensing resistor 8 is installed in series with negative DC supply 12 introducing power loss and inductance which is an impairment from the bypassing point of view and can easily introduce distortion.
An example ofthe universal power converter according to the present invention, which is free from the defects above, will be described with reference to FIG. 2.
In the example of the invention shown in FIG. 2, clock input terminal 11 is connected to first upper delay network 13 and first lower delay network 14. PWM input terminal 12 is connected to an input of logic circuit 15. Output of logic circuit 15 is connected to an input of shut down circuit 16. The upper drive output of shut down circuit 16 is connected to second upper delay network 18. The lower drive output of shut down circuit 16 is connected to second lower delay network 19.
The output of second upper delay network 18 is connected to switched current source 20 and output of switched current source 20 is connected to input of first buffer 22. The output of first buffer 22 is connected to input of upper capacitive level shifter 23 and output of upper capacitive level shifter 23 is connected to input of second buffer 26. Output of second buffer 26 is connected to control electrode of upper switching element 29.
Supply terminal of upper switching element 29 is connected to a power supply terminal 28 which is supplied with a positive DC voltage +VCC and supply terminal of lower switching element 31 is connected to a power supply terminal 32 which is supplied with a negative DC
voltage -VCC whose absolute value is same as that of positive DC voltage +VCC. Output of second lower delay network 19 is connected to input of lower capacitive level shifter 24 and control input of controlled switch 21.
Controlled switch 21 is connected to voltage sense circuit 25. Input of voltage sense circuit 25 is connected to a output terminal 30. Output of voltage sense circuit 25 is connected to input of monostable circuit 17 and output of monostable circuit 17 is connected to an input of shut down circuit 16. Output of lower capacitive level shifter 24 is connected to input of third buffer 27 and output of third buffer 27 is connected to control electrode of lower switching element 31. Output terminal of lower switching element 31 and output terminal of upper switching element 29 are connected together to output terminal 30.
The operation ofthe above-described circuit will now be explained. Clock input signal Sl, such as that shown in FIG. 3A, supplied to clock input terminal 11 is then input to the first upper delay network 13 which will be initiated at the positive going transition of the clock input signal S1. The first tower delay network 14 will be initiated at the negative going transition of the clock input signal Sl at clock input terminal 11 and will have such output as that shown in FIG. 3B.
Logic circuit 15 will combine the two delayed clock signals such that if PWM signal input S2, such as that shown in FIG. 3E, which is then input to PWM input terminal 12, approaches the 100% modulation angle or 0 modulation angle and then a maximum and minimum pulse width, respectively, in both directions ofthe modulation shall be supplied at the output of logic circuit 15 as shown in FIGS. 4C and 4D respectively. Here T is the period ofthe clock and Ot is the delay interval.
As logic circuit signal S3 is fed through the shut-down circuit 16, a disable fimetion may be facilitated, if monostable circuit 17 is triggered by voltage sense circuit 25 due to over current condition, by rendering upper switching element 29 and lower switching element 31 inactive by producing zero voltage at the c~trol electrodes of said devices. Shut down circuit 16 via second upper delay network 18 drives a switched current source 20 that is configured such that under no condition shall said switched current source 20 saturate. This configuration then yields a very high speed level translator, that has a typical propagational delay similar to the high speed first buffer 22, approximately 5 nanoseconds. Low voltage logic level signal S4 at the output terminal of first buffer 22 is fed to second buffer 26 via upper capacitive level shifter 23. Second buffer 26 is of high current capacity such that the propagational delay can be maintained again at approximately 5 nanosecond while signal levels are increased typically three fold to drive the control electrode of upper switching element 29 with signal such as that shown in FIG.
3F. As a final result, the delay from the output of first buffer 22 to control electrode of upper switching element 29 will be approximately 15 nanoseconds with a source and sink current of 10 amperes or greater thereby enabling very high speed drive of the high side upper switching element 29 at rail voltages of several hundred volts and output current of over 100 amperes (which is usually associated with very large control electrode to supply terminal capacitance).
The low side lower switching element 31 is driven in a similar fashion to maintain high power and high speed. Low voltage logic level signal S5, such as that shown in FIG.
3G, at the lower drive output of shut down circuit 16 is fed to third buffer 27 via second lower delay network 19 and via lower capacitive level shifter 24. The resultant signal at the control electrode of lower switching element 31 is such as that shown in FIG. 3H.
The applications can be divided into following major categories: AC to DC, DC
to DC, DC to AC, and AC to AC converters.
The most common approach would be to choose a standard high side drive, include a dead zone processing circuit to avoid shoot through and use a series low valued resistor between the supply and the switching device for current sensing. It turns out that for each different application a new design needs to be created with additional waste of engineering time. Also, the prior art solutions above 100V supply voltage have so much variation in propagational delay that direct paralleling of these solutions is not permitted. In the case of a pulse width modulation input signal at modulation extreme, most solutions utilizing a bootstrap circuit will fall apart due to the finite value which the holdup capacitor may have.
Also, chip solutions have to deal with the quadratic power loss increase as a function of operating voltage at a given frequency. The series current sensing resistor, especially at higher power, becomes very troublesome, not just as a result of the extra heat, but also the increase of ESL of the bypassing circuit.
Due to the high dv/dt and di/dt involved in high speed, high power circuitry, the design of the printed circuit board becomes a major task for accomplishing a sound design.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of this invention is to provide a topology for a universal power converter free from the defects encountered in the prior art bridge mode power converters. Another object of the invention is to provide a method of constructing a power converter of the widest possible use without fundamental change in the topology or even in the printed circuit board design, i.e. to enable the bridge mode converter to be truly universal use. In accordance with the present invention, a universal power converter is provided having a well defined, very low propagational delay, typically 4 times less the conventional solutions, to enable direct paralleling of converters without the need for the reduction of frequency of operation, having a well defined limit in minimum and maximum duty cycle in the event that the input signal has a duty cycle variation of 0 to 100 %, and also having a lossless current sensing method that tracks switching device on resistance change versus temperature to ensure a safe over current protection level at all allowable temperatures without dissipating extra power or introducing any inductance to the circuit. Yet another advantage ofthe present invention is that the same printed circuit board can be used for power levels of a few hundred watts to several kilowatts economically by simply reselecting the devices. The universal power converter of the present invention has myriad applications ranging from high fidelity audio to high power miniature welders, battery chargers, etc.
BRIEF DESCRIPTION OF DRAW INGS
FIG. 1 is a schematic circuit diagram showing a prior art power converter;
FIG. 2 is a schematic circuit diagram showing an example of the universal power converter according to the present invention; and FIGS. 3A to 3H are waveform diagrams used for explaining the operation of the example of the invention shown in FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In order to better understand the present invention a prior art power converter will be described with reference to FIG.1 which is a half bridge power converter building block.
The PWM signal is applied to signal input terminal 1 which is also the input for input buffer 2.
The output of input buffer 2 is then connected to upper delay network 3 and lower delay network 4. The outputs of upper and lower delay networks 3 and 4, respectively, are connected to inputs of high/low side drive and shut down circuit 5. The upper drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of the upper switching element 6. The lower drive output of high/low side drive and shut down circuit 5 is connected to the control electrode of lower switching element 7.
Current sensing resistor 8 is connected between supply terminal of the lower switching element 7 and negative DC supply 12 and the junction is then fed to the shut down input of high/low side drive circuit 5.
Bootstrap capacitor 9 is connected to high/low side drive and shut down circuit 5 to supply power to the upper switching element 6 when it is turned on. The output terminal of upper switching element 6 is connected to the positive DC
supply 10. The output terminal of upper switching element 6 and output terminal of lower switching element 7 are connected together to output terminal 11.
With the prior art power converter shown in FIG. 1, if the PWM signal applied to signal input terminal 1 exceeds 100% duty cycle, the upper switching element 6 may lose its supply, which is usually stored in bootstrap capacitor 9, causing severe distortion.
The dead zone protection delay networks 3 and 4 are supplying the signal for the upper and lower drive outputs of high/low side drive and shut down circuit 5. This results in a propagational delay of turn offofthe upper and lower switching elements 6 and 7, respectively, as high as 100 nanoseconds with large variation in operating conditions and from device to device. Therefore, paralleling of such power converters is only possible if the dead zones are selected very high which would impair the quality of the low frequency signal to be reproduced.
Current sensing resistor 8 is installed in series with negative DC supply 12 introducing power loss and inductance which is an impairment from the bypassing point of view and can easily introduce distortion.
An example ofthe universal power converter according to the present invention, which is free from the defects above, will be described with reference to FIG. 2.
In the example of the invention shown in FIG. 2, clock input terminal 11 is connected to first upper delay network 13 and first lower delay network 14. PWM input terminal 12 is connected to an input of logic circuit 15. Output of logic circuit 15 is connected to an input of shut down circuit 16. The upper drive output of shut down circuit 16 is connected to second upper delay network 18. The lower drive output of shut down circuit 16 is connected to second lower delay network 19.
The output of second upper delay network 18 is connected to switched current source 20 and output of switched current source 20 is connected to input of first buffer 22. The output of first buffer 22 is connected to input of upper capacitive level shifter 23 and output of upper capacitive level shifter 23 is connected to input of second buffer 26. Output of second buffer 26 is connected to control electrode of upper switching element 29.
Supply terminal of upper switching element 29 is connected to a power supply terminal 28 which is supplied with a positive DC voltage +VCC and supply terminal of lower switching element 31 is connected to a power supply terminal 32 which is supplied with a negative DC
voltage -VCC whose absolute value is same as that of positive DC voltage +VCC. Output of second lower delay network 19 is connected to input of lower capacitive level shifter 24 and control input of controlled switch 21.
Controlled switch 21 is connected to voltage sense circuit 25. Input of voltage sense circuit 25 is connected to a output terminal 30. Output of voltage sense circuit 25 is connected to input of monostable circuit 17 and output of monostable circuit 17 is connected to an input of shut down circuit 16. Output of lower capacitive level shifter 24 is connected to input of third buffer 27 and output of third buffer 27 is connected to control electrode of lower switching element 31. Output terminal of lower switching element 31 and output terminal of upper switching element 29 are connected together to output terminal 30.
The operation ofthe above-described circuit will now be explained. Clock input signal Sl, such as that shown in FIG. 3A, supplied to clock input terminal 11 is then input to the first upper delay network 13 which will be initiated at the positive going transition of the clock input signal S1. The first tower delay network 14 will be initiated at the negative going transition of the clock input signal Sl at clock input terminal 11 and will have such output as that shown in FIG. 3B.
Logic circuit 15 will combine the two delayed clock signals such that if PWM signal input S2, such as that shown in FIG. 3E, which is then input to PWM input terminal 12, approaches the 100% modulation angle or 0 modulation angle and then a maximum and minimum pulse width, respectively, in both directions ofthe modulation shall be supplied at the output of logic circuit 15 as shown in FIGS. 4C and 4D respectively. Here T is the period ofthe clock and Ot is the delay interval.
As logic circuit signal S3 is fed through the shut-down circuit 16, a disable fimetion may be facilitated, if monostable circuit 17 is triggered by voltage sense circuit 25 due to over current condition, by rendering upper switching element 29 and lower switching element 31 inactive by producing zero voltage at the c~trol electrodes of said devices. Shut down circuit 16 via second upper delay network 18 drives a switched current source 20 that is configured such that under no condition shall said switched current source 20 saturate. This configuration then yields a very high speed level translator, that has a typical propagational delay similar to the high speed first buffer 22, approximately 5 nanoseconds. Low voltage logic level signal S4 at the output terminal of first buffer 22 is fed to second buffer 26 via upper capacitive level shifter 23. Second buffer 26 is of high current capacity such that the propagational delay can be maintained again at approximately 5 nanosecond while signal levels are increased typically three fold to drive the control electrode of upper switching element 29 with signal such as that shown in FIG.
3F. As a final result, the delay from the output of first buffer 22 to control electrode of upper switching element 29 will be approximately 15 nanoseconds with a source and sink current of 10 amperes or greater thereby enabling very high speed drive of the high side upper switching element 29 at rail voltages of several hundred volts and output current of over 100 amperes (which is usually associated with very large control electrode to supply terminal capacitance).
The low side lower switching element 31 is driven in a similar fashion to maintain high power and high speed. Low voltage logic level signal S5, such as that shown in FIG.
3G, at the lower drive output of shut down circuit 16 is fed to third buffer 27 via second lower delay network 19 and via lower capacitive level shifter 24. The resultant signal at the control electrode of lower switching element 31 is such as that shown in FIG. 3H.
The operation of the short circuit protection of the above mentioned circuit will now be explained. The voltage drop across lower switching element 31 is directly proportional to the current flowing through it and is being sensed by voltage sense circuit 25. if current across lower switching element 34 exceeds defined limit, overload condition, voltage sense circuit 25 will turn on and trigger monostable circuit 17 which, in tum, shall initiate shut down condition via shut down circuit 16. The shut down condition is maintained until monostable circuit 17 times out (i.e.
several hundred milliseconds).
This process then repeats until the overload condition is removed. Switch 21 is to keep voltage sense circuit 25 in the off state during off states of lower switching element 31.
Thus, lossless current sensing is achieved having the additional feature of moving the current limit to a lower value when the junction temperature increases, further increasing the reliability of the circuit.
Also, it is of great advantage that series sensing resistance is nat used, the use ofwhich would result in a decrease ofthe effectiveness of bypassing the upper and lower switching elements 29 and 31 and would decrease the efficiency of the circuit.
several hundred milliseconds).
This process then repeats until the overload condition is removed. Switch 21 is to keep voltage sense circuit 25 in the off state during off states of lower switching element 31.
Thus, lossless current sensing is achieved having the additional feature of moving the current limit to a lower value when the junction temperature increases, further increasing the reliability of the circuit.
Also, it is of great advantage that series sensing resistance is nat used, the use ofwhich would result in a decrease ofthe effectiveness of bypassing the upper and lower switching elements 29 and 31 and would decrease the efficiency of the circuit.
Claims (15)
1. A universal power converter comprising:
(a) signal input means for supplying a rectangular waveform with varying duty cycle to be power amplified;
(b) a clock signal input means with fixed duty cycle rectangular waveform for timing reference;
(c) a first upper and lower delay means having said clock signal supplied to their respective inputs and each having an output;
(d) logic circuit means having a first, second, third input, wherein first input is connected to said upper delay, second input is connected to said lower delay, and third input is connected to said signal input, and an output;
(e) a shut down circuit means having a first input connected to the output of said logic circuit means, a second input, a high side drive output, and a low side drive output;
(f) a second upper delay means having an input connected to said high side drive output of said shut down circuit and an output;
(g) a switched current source means having an input connected to the output of said high side drive and an output;
(h) a first buffer means having an input connected to the output of said high side drive and an output;
(i) an upper capacitive level shifter means having an input connected to the output of said switched current source and an output;
(j) a second buffer means having an input connected to said upper capacitive level shifter and an output;
(k) an upper switching element means having a control electrode connected to the output of said second buffer, a supply terminal, and an output terminal;
(1) a second lower delay means having an input connected to said lower side output of said shut down circuit and an output;
(m) a lower capacitive level shifter means having an input terminal connected to the output of said second lower delay circuit and an output;
(n) a third buffer means having an input connected to the output of said lower capacitive level shifter and an output;
(o) a lower switching element means having a control electrode connected to the output of said third buffer, a supply terminal, and an output terminal;
(p) a voltage sense circuit means having a first input connected to the output terminal of said lower switching element, a second input, and an output;
(q) a controlled switch means having an input terminal connected to the output of said second lower delay and an output connected to the second input of said voltage sense circuit; and (r) a monostable multi-vibrator means having an input connected to the output terminal of said voltage sense circuit and an output connected to said second input of said shut down circuit.
(a) signal input means for supplying a rectangular waveform with varying duty cycle to be power amplified;
(b) a clock signal input means with fixed duty cycle rectangular waveform for timing reference;
(c) a first upper and lower delay means having said clock signal supplied to their respective inputs and each having an output;
(d) logic circuit means having a first, second, third input, wherein first input is connected to said upper delay, second input is connected to said lower delay, and third input is connected to said signal input, and an output;
(e) a shut down circuit means having a first input connected to the output of said logic circuit means, a second input, a high side drive output, and a low side drive output;
(f) a second upper delay means having an input connected to said high side drive output of said shut down circuit and an output;
(g) a switched current source means having an input connected to the output of said high side drive and an output;
(h) a first buffer means having an input connected to the output of said high side drive and an output;
(i) an upper capacitive level shifter means having an input connected to the output of said switched current source and an output;
(j) a second buffer means having an input connected to said upper capacitive level shifter and an output;
(k) an upper switching element means having a control electrode connected to the output of said second buffer, a supply terminal, and an output terminal;
(1) a second lower delay means having an input connected to said lower side output of said shut down circuit and an output;
(m) a lower capacitive level shifter means having an input terminal connected to the output of said second lower delay circuit and an output;
(n) a third buffer means having an input connected to the output of said lower capacitive level shifter and an output;
(o) a lower switching element means having a control electrode connected to the output of said third buffer, a supply terminal, and an output terminal;
(p) a voltage sense circuit means having a first input connected to the output terminal of said lower switching element, a second input, and an output;
(q) a controlled switch means having an input terminal connected to the output of said second lower delay and an output connected to the second input of said voltage sense circuit; and (r) a monostable multi-vibrator means having an input connected to the output terminal of said voltage sense circuit and an output connected to said second input of said shut down circuit.
2. A universal power converter as in claim 1, in which said signal input is a waveform, essentially rectangular, with varying duty cycle.
3. A universal power converter as in claim 1, in which the positive and negative transition of said clock signal is delayed by said first upper delay and said first lower delay amount.
4. A universal power converter as in claim 3, wherein said delayed transition are set so as to produce an output signal of said logic circuit such that a minimum and maximum pulse width is always maintained regardless of the amount of modulation at said signal input.
5. A universal power converter as in claim 4, wherein said output signal of said logic circuit is fed through said shut down circuit for protection.
6. A universal power converter as in claim 5, wherein said upper drive output of said shut down circuit is followed by a second upper delay in order to achieve delayed turn on of said upper switching element.
7. A universal power converter as in claim 6, wherein said second upper delay output is driving said switched current source having an output signal 180 degrees out of phase with the signal at said control terminal of said upper switching element.
8. A universal power converter as in claim 6, in which the output of said switched current source is driving first buffer having substantial hysteresis.
9. A universal power converter as in claim 7, having said second buffer connected between said upper capacitive level shifter and the control electrode of said upper switching element and said second buffer is allowed to have substantially greater voltage than said upper capacitive level shifter without significant change in propagational delay.
10. A universal power converter as in claim 5, wherein said lower drive output of said shut down circuit is followed by a second lower delay in order to achieve delayed turn on of said lower switching element.
11. A universal power converter as in claim 10, wherein output of said second lower delay is feeding said lower capacitive level shifter.
12. A universal power converter as in claim 11, having said third buffer connected between said lower capacitive level shifter and the control electrode of said lower switching element and said third buffer is allowed to operate at substantially greater voltage than said lower capacitive level shifter without significant change in propagational delay.
13. A universal power converter as in claims 9 and 11, wherein said upper switching and lower switching elements are N-channel type MOSFETs having the drain of said lower MOSFET
connected to the source of said upper MOSFET and the drain of said upper MOSFET is connected to a positive supply and the source of said lower MOSFET is connected to a negative supply.
connected to the source of said upper MOSFET and the drain of said upper MOSFET is connected to a positive supply and the source of said lower MOSFET is connected to a negative supply.
14. A universal power converter as in claim 13, wherein the connection of the source of said upper MOSFET and the drain of said lower MOSFET forms a load output where a signal is available to a load with high current and voltage capability and its duty cycle is limited to a predetermined maximum and minimum value in case the duty cycle of said drive signal approaches 100% or 0 respectively.
15. A universal power converter as in claim 14, wherein said voltage sense circuit input is sensing the voltage on said load output:
(a) and said voltage sense circuit is turned off by said controlled switch if said lower switching element is turned off;
(b) and said voltage sense circuit shall trigger monostable multi-vibrator to terminate the operation until the fault condition is removed;
(c) and said voltage sense circuit will detect over current of decreasing value as temperature due to positive temperature co-efficient of on resistance of said lower MOSFET
and said over current limit can be made to closely track safe current values of said lower MOSFET at elevated temperature.
(a) and said voltage sense circuit is turned off by said controlled switch if said lower switching element is turned off;
(b) and said voltage sense circuit shall trigger monostable multi-vibrator to terminate the operation until the fault condition is removed;
(c) and said voltage sense circuit will detect over current of decreasing value as temperature due to positive temperature co-efficient of on resistance of said lower MOSFET
and said over current limit can be made to closely track safe current values of said lower MOSFET at elevated temperature.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2418123 CA2418123A1 (en) | 2003-02-05 | 2003-02-05 | Universal power converter |
| PCT/CA2004/000138 WO2004070923A2 (en) | 2003-02-05 | 2004-02-03 | Universal power converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2418123 CA2418123A1 (en) | 2003-02-05 | 2003-02-05 | Universal power converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2418123A1 true CA2418123A1 (en) | 2004-08-05 |
Family
ID=32831542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2418123 Abandoned CA2418123A1 (en) | 2003-02-05 | 2003-02-05 | Universal power converter |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA2418123A1 (en) |
| WO (1) | WO2004070923A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011017712A1 (en) | 2011-04-28 | 2012-10-31 | Robert Bosch Gmbh | Method and control device for guard time adjustment in an electric drive system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3859586A (en) * | 1973-09-26 | 1975-01-07 | Bell Telephone Labor Inc | Overcurrent protection circuit utilizing peak detection circuit with variable dynamic response |
| DE3937447A1 (en) * | 1989-11-10 | 1991-05-16 | Hanning Elektro Werke | PROTECTIVE DEVICE FOR FREQUENCY INVERTER |
| DE19543956C1 (en) * | 1995-11-25 | 1997-04-03 | Wolfgang Dipl Ing Schuster | Control of electronic switching stages of bridge pairs |
-
2003
- 2003-02-05 CA CA 2418123 patent/CA2418123A1/en not_active Abandoned
-
2004
- 2004-02-03 WO PCT/CA2004/000138 patent/WO2004070923A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004070923A3 (en) | 2004-09-30 |
| WO2004070923A2 (en) | 2004-08-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |
Effective date: 20121029 |