CA2248337C - Offset correction circuit and dc amplification circuit - Google Patents
Offset correction circuit and dc amplification circuit Download PDFInfo
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- CA2248337C CA2248337C CA002248337A CA2248337A CA2248337C CA 2248337 C CA2248337 C CA 2248337C CA 002248337 A CA002248337 A CA 002248337A CA 2248337 A CA2248337 A CA 2248337A CA 2248337 C CA2248337 C CA 2248337C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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Abstract
An offset correction circuit containing an integrator is provided between output of a first DC amplifier and input of a second DC amplifier, and the integrator corrects not only an offset error caused by an input signal in the first DC
amplifier, but also an offset error caused by an input signal in the second DC amplifier. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the two DC amplifiers can be canceled.
amplifier, but also an offset error caused by an input signal in the second DC amplifier. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the two DC amplifiers can be canceled.
Description
OFFSET CORRECTION CIRCUIT AND DC AMPLIFICATION CIRCUIT
BACKGROUND OF THE INVENTION
1. Field of the Invention This invention relates to an offset correction circuit for correcting an offset error caused by an input signal of a s DC amplifier and a DC amplification circuit including the offset correction circuit.
BACKGROUND OF THE INVENTION
1. Field of the Invention This invention relates to an offset correction circuit for correcting an offset error caused by an input signal of a s DC amplifier and a DC amplification circuit including the offset correction circuit.
2. Description of the Related Art In a conventional DC amplifier for amplifying an input signal and outputting the amplified signal, it is ideal that if 0 an input signal is 0, an output signal becomes 0. However, if just after an input signal of a large amplitude is added, it is set to 0, an output signal does not become 0 and an offset error caused by the input signal occurs. Some offset errors caused by the input signal continue for 10 milliseconds to several ten seconds; the cause of continuation of the offset error for a long time may depend on temperature stability and power supply voltage variation rate.
FIG. 5 is a basic circuit diagram of a DC amplifier.
First, occurrence of an offset error depending on the temperature stability resulting from an input signal will be discussed. In FIG. 5, a DC amplifier 5 is made up of a differential amplifier 5S and a voltage amplifier 56. The differential amplifier 55 consists of transistors TR51 and TRS2 and resistors R51, RS2, and R53. The voltage amplifier 56 -consists of a transistor TR53 and resistors R54 and R55. A
positive input terminal IN51 is connected to a base of the transistor TR51 and a negative input terminal IN52 is connected to a base of the transistor TR52. An output terminal O51 is connected to the resistor R55. A positive power supply is connected to a power supply input terminal V51 and a negative power supply is connected to a power supply input terminal V52.
A signal is input through the positive input terminal IN51 or the negative input terminal IN52 and is output to the o output terminal O51. Normally, a part of signal output from the output terminal O51 is fed back into the negative input terminal IN52, but not fed back in FIG. 5 for simplicity. The transistors TR51 and TR52 are of the same structure and characteristics and the resistors R51 and R52 are of the same resistance value. Further, if the applied voltage to the positive input terminal IN51 is set to 0 and the negative input terminal IN52 is grounded, the current flowing into the resistors R51 and R52 is reduced to half the current flowing into the resistor R53, and the characteristics of the transistor TR53 and the resistor R55 are adjusted so that the voltage of the output terminal O51 becomes 0.
First, when a positive voltage is applied to the positive input terminal IN51, in the differential amplifier 55, a collector current of the transistor TR51 increases and a collector current of the transistor TR52 decreases. As the collector current of the transistor TR51 increases, the voltage of the resistor R51 increases and the collector-emitter voltage of the transistor TR51 decreases. Normally, to widen the differential input range, the collector-emitter voltage of the transistor TR51 or TR52 is large as compared with the voltage of the resistor R51 or R52. Thus, the decrease rate of the collector-emitter voltage of the transistor TR51 is small as compared with the increase rate of the current of the transistor TR51. Therefore, power consumption of the transistor TRSl is increased and the device temperature of the lo transistor TR51 rises. Since power consumption of the transistor TR52 is decreased and the device temperature of the transistor TR52 lowers, the temperature of the transistor TR51 becomes higher than that of the transistor TR52. The temperature difference between the transistors TR51 and TR52 is as in the following expression (l):
1 ~ ~T(51)~ T(52)~
l P(Sl) - dt - J P(52) - dt Q(51) ~(51) Q(52) ~(52) where Q(51), Q(52): Heat capacity of transistor TR51, TR52, P(51), P(52): Heating value of transistor TR51, TR52, ~T(51), ~T(52): Temperature difference between device of transistor TR51, TR52 and environment, and ~(51), ~(52): Heat resistance between device of transistor TR51, TR52 and environment.
Next, the applied voltage to the positive input terminal IN51 is set to 0. If there is no temperature difference between the transistors TR51 and TR52, the currents flowing into the resistors R51 and R52 become the same and the voltage of the output terminal 051 becomes 0. However, since the temperature of the transistor TR51 is higher than that of the transistor TR52 as described above, the base-emitter voltage of the transistor TR51 becomes smaller than the base-emitter voltage of the transistor TR52. Thus, the base current of the transistor TR51 becomes larger than the base current of the transistor TR52 and the collector current of the transistor TR51 becomes larger than the collector current of the transistor TR52. As the collector current of the transistor TR51 becomes larger than the collector current of the transistor TR52, the voltage of the resistor R51 becomes larger than the voltage of the resistor R52 and a positive offset error voltage occurs at the output terminal 051.
The offset error voltage occurring at the output terminal 051 is caused by the temperature difference between the transistors TR51 and TR52; the cause of temperature difference occurrence between the transistors TRS1 and TR52 is eliminated already by setting the applied voltage of the positive input terminal IN51 to 0, but the temperature difference caused by the power consumption difference between the transistors TR51 and TR52 when a potential difference occurs between the positive input terminal IN51 and the negative input terminal IN52 is accumulated because of the heat capacities of the transistors TR51 and TR52. The accumulated ., .~
temperature difference gradually lessens according to the condition under which P(51) and P(52) in Expression (1) become the same. As the temperature difference lessens, the offset error voltage occurring at the output terminal O51 also lessens. When the temperature difference between the transistors TR51 and TR52 is eliminated, the offset error occurring at the output terminal 051 is also eliminated.
As described above, in the conventional DC amplifier 5, the temperature stability is degraded because of temperature lo variation of the components of the DC amplifier 5 caused by the input signal and an offset error occurs.
Next, occurrence of an offset error because of power supply voltage variation caused by an input signal in the DC
amplifier 5 will be discussed. First, power supply voltage variation caused by an input signal will be discussed. In FIG.
5, if the voltage of the output terminal O51 of the DC
amplifier 5 is positive, the collector current of the transistor TR53 grows as compared with the case where the voltage of the output terminal O51 is 0. Thus, the power supply current of the positive power supply input terminal V51 and the negative power supply input terminal V52 grows; the current flowing out through the output terminal O51 flows out from the positive power supply input terminal V51 via the transistor TR53 to the output terminal O51 and the current flowing in through the output terminal O51 flows into the negative power supply input terminal V52 via the resistor R55 from the output terminal 051. Therefore, output of the DC
amplifier 5 changes with the input voltage, thus the power supply current varies with the input voltage and if the power supply current varies, variation of the power supply voltage commensurate with output resistance of the power supply connected to the DC amplifier 5 occurs. The power supply voltage variation caused by the input signal thus occurs.
Next, occurrence of an offset error because of power supply voltage variation in the DC amplifier 5 will be o discussed. In FIG. 5, the applied voltage of the positive input terminal IN51 is set to 0 and the differential amplifier consisting of the transistors TR51 and TR52 and the resistors R51, RS2, and RS3 is placed in an equilibrium state.
The transistor TR53 operates so as to adjust the collector current of the transistor TR53 so that the voltage of the resistor R51 becomes equal to the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54. If the voltage generated at the resistor R55 by the collector current of the transistor TR53 is equal to the voltage of the negative power supply input terminal V52, the voltage of the output terminal OSl becomes 0.
Next, if the negative power supply input terminal V52 varies and the voltage thereof is reduced to half, the voltage of the resistor R53 is reduced to about half because the positive input terminal IN51 and the negative input terminal IN52 are at ground potential. When the voltage of the resistor R53 is reduced to about half, the current of the resistor R53 is reduced to half and the current flowing into the resistors R51 and R52 is reduced to half. The voltage of the resistor R51 is reduced to half and the transistor TR53 operates so as to adjust the collector current of the transistor TR53 so that the voltage of the resistor R51 becomes equal to the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54. Thus, the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54 is reduced to half.
lo Since the base-emitter voltage of the transistor TR53 is not proportional to the emitter current of the transistor TR53 and is almost constant, if the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54 is reduced to half, the voltage of the resistor R54 is lessened to half or lS less. This means that the current flowing between the collector and emitter of the transistor TR53 is lessened to half or less and the voltage of the resistor RSS is lessened to half or less. When the voltage of the resistor R55 is lessened to half or less, the voltage of the output terminal 051 becomes the voltage difference between the resistor R55 and the negative power supply input terminal VS2, thus a negative offset error occurs.
Thus, variation of the power supply current of the DC
amplifier S is caused by the input signal and as the power 2s supply current varies, the power supply voltage varies. When the power supply voltage varies, an offset error occurs in the DC amplifier 5. Therefore, in the DC amplifier S, an offset error occurs because of the power supply voltage variation caused by the input signal. Hitherto, to suppress power supply voltage variation caused by power supply current variation, a capacitor has been added to the power supply connected to the DC amplifier 5; the power supply current variation is replaced with charge/discharge of the capacitor of the power supply and the power supply voltage is proportional to the charge amount accumulated in the capacitor and thus proportional to the change amount integral value of the power supply current.
Therefore, the power supply voltage variation caused by the input signal is proportional to the integral value of the charge amount accumulated in the capacitor, thus the offset error occurring because of the power supply voltage variation is proportional to the integral value of the input signal strength.
Thus, in the conventional DC amplifier, an offset error occurs depending on the temperature stability or power supply voltage variation rate resulting from an input signal. The offset error is proportional to the integral value of the input signal strength.
SUMMARY QF THE INVENTION
It is therefore an object of the invention to provide an offset correction circuit for predicting an offset error from the input signal strength in a DC amplifier of known electric characteristics and a known structure and generating a signal for canceling the offset error, thereby correcting the offset error caused by the input signal, and a high-accurate DC
amplification circuit including the offset correction circuit.
According to the invention, there is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, the offset correction circuit comprising:
lo an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC
g amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC
amplifiers, the offset correction circuit comprising: an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the input stage of the DC
lo amplifier at the preceding stage and the input stage of the DC
amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC
amplification circuit, caused by the input signal to each DC
amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC
amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC
amplifiers, the offset correction circuit comprising: an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, the integrator being connected between the output stage of the DC
amplifier at the preceding stage and the input stage of the DC
amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC
lo amplification circuit, caused by the input signal to each DC
amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit, the offset correction circuit comprising: an A/D converter for converting an output signal from the DC amplification circuit into a time series numeric signal and outputting the numeric signal, the A/D converter being connected to an output stage of the DC amplification circuit; and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from the A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, the processing unit being connected to an output stage of the A/D converter, wherein an offset error occurring in an output signal of the DC
, amplification circuit, caused by the input signal to the DC
amplification circuit is corrected.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC
amplifier at a preceding stage to generate a correction signal lo and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC
-amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier o at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC
amplifier at a preceding stage to generate a correction signal zo and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at . .
the intermediate stage via the match resistor to the DC
amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC amplifier.
There is provided a DC amplification circuit comprising: a DC amplifier; an A/D converter for converting an output signal from the DC amplifier into a time series numeric signal and outputting the numeric signal, the A/D converter being connected to an output stage of the DC amplifier; and a 0 processing unit for performing predetermined integration processing for integrating the time series numeric signal output from the A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, the processing unit being connected to an output stage of the A/D converter, wherein an offset error correction function is provided for correcting an offset error occurring in an output signal of the DC
amplification circuit, caused by an input signal to the DC
amplifier.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a diagram to show a DC amplification circuit including an offset correction circuit of a first embodiment of the invention;
_ FIG. 2 is a diagram to show a DC amplification circuit including an offset correction circuit of a second embodiment of the invention;
FIG. 3 is a diagram to show a DC amplification circuit including an offset correction circuit of a third embodiment of the invention;
FIG. 4 is a diagram to show a DC amplification circuit including an offset correction circuit of a fourth embodiment of the invention; and 0 FIG. 5 is a diagram to show a basic circuit configuration of a conventional DC amplifier.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the accompanying drawings, there are shown preferred embodiments of the invention.
(First Embodiment) FIG. 1 is a diagram to show a first embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 1 is a diagram to show the circuit configuration of a DC amplification circuit 1 including an offset correction circuit 11 of the first embodiment of the invention. In FIG.
1, the DC amplification circuit 1 is made up of the offset correction circuit 11 consisting of an integrator Sll and resistors Rll and R13, DC amplifiers All and A12, and resistors R12 and R14.
. _ The DC amplifier All amplifies a signal input through an input terminal IN11 and outputs the amplified signal to the resistor Rll of the offset correction circuit 11 and the resistor R12.
sThe resistor R12 is connected to output of the DC
amplifier All in series and the resistor R14 is connected to input of the DC amplifier A12 at the stage following the resistor R12 in parallel and is grounded at one end. The resistors R12 and R14 are match resistors for cascading the DC
loamplifiers All and A12. The resistor R12 has a larger impedance than that of the output resistor of the DC amplifier All.
The offset correction circuit 11, which is made up of the integrator Sll and the resistors Rll and R13, corrects an 5offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from an input signal in the DC amplifiers All and A12.
The integrator Sll is connected in parallel with the 20resistor R12 between output of the DC amplifier All and input of the DC amplifier A12. The resistor Rll is connected to input of the integrator Sll in series and the resistor R13 is connected to output of the integrator Sll in series. The integrator Sll, which has predetermined characteristics, z5performs integration-based operation processing according to a separation signal input through the resistor Rll and outputs to the resistor R13 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A11 and A12.
5The DC amplifier A12 amplifies a signal provided by combining a signal from the resistor R12 and the correction signal from the resistor R13 of the offset correction circuit 11 and input through the resistor R14, and outputs the amplified signal to an output terminal O11.
loNext, the operation of the first embodiment is as follows:
A signal input through an input terminal IN11 in FIG.
1 to the DC amplifier A11 is amplified and output to the resistor Rll of the offset correction circuit 11 and the 5resistor R12. The signal input to the resistor R12 is matched and output to the resistor R14 and the DC amplifier A12. In the offset correction circuit 11, a separation signal input through the resistor Rll to the integrator Sll is converted by integration-based operation processing into a correction signal 20for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers All and A12, and the correction signal is output to the resistor R13.
25The correction signal output through the resistor R13 of the offset correction circuit 11 is combined with the signal output through the resistor R12 and the resultant signal is input to the DC amplifier A12 through the resistor R14 of a match resistor. The signal input to the DC amplifier A12 is amplified and output to the output terminal O11.
If the input and output signals of the integrator Sll are of the same sign, a positive feedback path from the resistor R13 via the resistor R12 to the resistor Rll is produced; the impedance of the resistor R12 is large as compared with the impedance of the output resistor of the DC
lo amplifier All, thus the feedback amount does not exceed 1 and output of the DC amplifier All is little affected by the correction signal from the integrator Sll.
As described above, with the offset correction circuit 11 and the DC amplification circuit 1 of the first embodiment, the offset correction circuit 11 containing the integrator Sll is placed between the output of the DC amplifier All and the input of the DC amplifier A12 and the integrator S11 corrects not only an offset error caused by the input signal in the DC
amplifier All, but also an offset error caused by the input signal in the DC amplifier A12. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers All and A12 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect ._ of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Second Embodiment) A second embodiment of the invention will be discussed wherein an offset correction circuit containing an integrator for correcting an offset error in two DC amplifiers cascaded as in the DC amplification circuit l of the first embodiment is lo connected in another circuit configuration.
FIG. 2 is a diagram to show a second embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 2 is a diagram to show the circuit configuration of a DC amplification circuit 2 including an offset correction circuit 21 of the second embodiment of the invention. In FIG.
2, the DC amplification circuit 2 is made up of the offset correction circuit 21 consisting of an integrator S21 and resistors R21 and R23, DC amplifiers A21 and A22, and resistors R22 and R24.
The DC amplifier A21 amplifies a signal input through an input terminal IN21 and outputs the amplified signal to the resistor R22.
The resistor R22 is connected to output of the DC
amplifier A21 in series and the resistor R24 is connected to input of the DC amplifier A22 at the stage following the resistor R22 in parallel and is grounded at one end. The resistors R22 and R24 are match resistors for cascading the DC
amplifiers A21 and A22.
The offset correction circuit 21, which is made up of the integrator S21 and the resistors R21 and R23, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from lo an input signal in the DC amplifiers A21 and A22.
The integrator S21 is connected in parallel with the DC
amplifier A21 and the resistor R22 between input of the DC
amplifier A21 and input of the DC amplifier A22. The resistor R21 is connected to input of the integrator S21 in series and the resistor R23 is connected to output of the integrator S21 in series. The integrator S21, which has predetermined characteristics, performs integration-based operation processing according to a separation signal input through the resistor R21 and outputs to the resistor R23 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A21 and A22.
The DC amplifier A22 amplifies a signal provided by combining a signal from the resistor R22 and the correction signal from the resistor R23 of the offset correction circuit _..
21 and input through the resistor R24, and outputs the amplified signal to an output terminal 021.
Next, the operation of the second embodiment is as follows:
s A signal is input through an input terminal IN21 in FIG. 2 to the DC amplifier A21 and the resistor R21 of the offset correction circuit 21 and the signal input to the DC
amplifier A21 is amplified and output to the resistor R22. The signal input to the resistor R22 is matched and output to the lo resistor R24 and the DC amplifier A22. In the offset correction circuit 21, a separation signal input through the resistor R21 to the integrator S21 is converted by integration-based operation processing into a correction signal for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers A21 and A22, and the correction signal is output to the resistor R23.
The correction signal output through the resistor R23 of the offset correction circuit 21 is combined with the signal output through the resistor R22 and the resultant signal is input to the DC amplifier A22 through the resistor R24 of a match resistor. The signal input to the DC amplifier A22 is amplified and output to the output terminal 021.
As described above, with the offset correction circuit 21 and the DC amplification circuit 2 of the second embodiment, the offset correction circuit 21 containing the integrator S21 is placed between the input of the DC amplifier A21 and the input of the DC amplifier A22 in parallel with the DC amplifier A21 and the resistor R22, and the integrator S21 corrects not only an offset error caused by the input signal in the DC
amplifier A21, but also an offset error caused by the input signal in the DC amplifier A22. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or lo power supply voltage variation rate resulting from the input signal in the DC amplifiers A21 and A22 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Third Embodiment) In the first and second embodiments, the DC
amplification circuit including the offset correction circuit for correcting an offset error in the two DC amplifiers cascaded has been discussed. In a third embodiment of the invention, a DC amplification circuit using three DC amplifiers cascaded will be discussed.
._ FIG. 3 is a diagram to show a third embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 3 is a diagram to show the circuit configuration of a DC amplification circuit 3 including an offset correction circuit 31 of the third embodiment of the invention. In FIG.
FIG. 5 is a basic circuit diagram of a DC amplifier.
First, occurrence of an offset error depending on the temperature stability resulting from an input signal will be discussed. In FIG. 5, a DC amplifier 5 is made up of a differential amplifier 5S and a voltage amplifier 56. The differential amplifier 55 consists of transistors TR51 and TRS2 and resistors R51, RS2, and R53. The voltage amplifier 56 -consists of a transistor TR53 and resistors R54 and R55. A
positive input terminal IN51 is connected to a base of the transistor TR51 and a negative input terminal IN52 is connected to a base of the transistor TR52. An output terminal O51 is connected to the resistor R55. A positive power supply is connected to a power supply input terminal V51 and a negative power supply is connected to a power supply input terminal V52.
A signal is input through the positive input terminal IN51 or the negative input terminal IN52 and is output to the o output terminal O51. Normally, a part of signal output from the output terminal O51 is fed back into the negative input terminal IN52, but not fed back in FIG. 5 for simplicity. The transistors TR51 and TR52 are of the same structure and characteristics and the resistors R51 and R52 are of the same resistance value. Further, if the applied voltage to the positive input terminal IN51 is set to 0 and the negative input terminal IN52 is grounded, the current flowing into the resistors R51 and R52 is reduced to half the current flowing into the resistor R53, and the characteristics of the transistor TR53 and the resistor R55 are adjusted so that the voltage of the output terminal O51 becomes 0.
First, when a positive voltage is applied to the positive input terminal IN51, in the differential amplifier 55, a collector current of the transistor TR51 increases and a collector current of the transistor TR52 decreases. As the collector current of the transistor TR51 increases, the voltage of the resistor R51 increases and the collector-emitter voltage of the transistor TR51 decreases. Normally, to widen the differential input range, the collector-emitter voltage of the transistor TR51 or TR52 is large as compared with the voltage of the resistor R51 or R52. Thus, the decrease rate of the collector-emitter voltage of the transistor TR51 is small as compared with the increase rate of the current of the transistor TR51. Therefore, power consumption of the transistor TRSl is increased and the device temperature of the lo transistor TR51 rises. Since power consumption of the transistor TR52 is decreased and the device temperature of the transistor TR52 lowers, the temperature of the transistor TR51 becomes higher than that of the transistor TR52. The temperature difference between the transistors TR51 and TR52 is as in the following expression (l):
1 ~ ~T(51)~ T(52)~
l P(Sl) - dt - J P(52) - dt Q(51) ~(51) Q(52) ~(52) where Q(51), Q(52): Heat capacity of transistor TR51, TR52, P(51), P(52): Heating value of transistor TR51, TR52, ~T(51), ~T(52): Temperature difference between device of transistor TR51, TR52 and environment, and ~(51), ~(52): Heat resistance between device of transistor TR51, TR52 and environment.
Next, the applied voltage to the positive input terminal IN51 is set to 0. If there is no temperature difference between the transistors TR51 and TR52, the currents flowing into the resistors R51 and R52 become the same and the voltage of the output terminal 051 becomes 0. However, since the temperature of the transistor TR51 is higher than that of the transistor TR52 as described above, the base-emitter voltage of the transistor TR51 becomes smaller than the base-emitter voltage of the transistor TR52. Thus, the base current of the transistor TR51 becomes larger than the base current of the transistor TR52 and the collector current of the transistor TR51 becomes larger than the collector current of the transistor TR52. As the collector current of the transistor TR51 becomes larger than the collector current of the transistor TR52, the voltage of the resistor R51 becomes larger than the voltage of the resistor R52 and a positive offset error voltage occurs at the output terminal 051.
The offset error voltage occurring at the output terminal 051 is caused by the temperature difference between the transistors TR51 and TR52; the cause of temperature difference occurrence between the transistors TRS1 and TR52 is eliminated already by setting the applied voltage of the positive input terminal IN51 to 0, but the temperature difference caused by the power consumption difference between the transistors TR51 and TR52 when a potential difference occurs between the positive input terminal IN51 and the negative input terminal IN52 is accumulated because of the heat capacities of the transistors TR51 and TR52. The accumulated ., .~
temperature difference gradually lessens according to the condition under which P(51) and P(52) in Expression (1) become the same. As the temperature difference lessens, the offset error voltage occurring at the output terminal O51 also lessens. When the temperature difference between the transistors TR51 and TR52 is eliminated, the offset error occurring at the output terminal 051 is also eliminated.
As described above, in the conventional DC amplifier 5, the temperature stability is degraded because of temperature lo variation of the components of the DC amplifier 5 caused by the input signal and an offset error occurs.
Next, occurrence of an offset error because of power supply voltage variation caused by an input signal in the DC
amplifier 5 will be discussed. First, power supply voltage variation caused by an input signal will be discussed. In FIG.
5, if the voltage of the output terminal O51 of the DC
amplifier 5 is positive, the collector current of the transistor TR53 grows as compared with the case where the voltage of the output terminal O51 is 0. Thus, the power supply current of the positive power supply input terminal V51 and the negative power supply input terminal V52 grows; the current flowing out through the output terminal O51 flows out from the positive power supply input terminal V51 via the transistor TR53 to the output terminal O51 and the current flowing in through the output terminal O51 flows into the negative power supply input terminal V52 via the resistor R55 from the output terminal 051. Therefore, output of the DC
amplifier 5 changes with the input voltage, thus the power supply current varies with the input voltage and if the power supply current varies, variation of the power supply voltage commensurate with output resistance of the power supply connected to the DC amplifier 5 occurs. The power supply voltage variation caused by the input signal thus occurs.
Next, occurrence of an offset error because of power supply voltage variation in the DC amplifier 5 will be o discussed. In FIG. 5, the applied voltage of the positive input terminal IN51 is set to 0 and the differential amplifier consisting of the transistors TR51 and TR52 and the resistors R51, RS2, and RS3 is placed in an equilibrium state.
The transistor TR53 operates so as to adjust the collector current of the transistor TR53 so that the voltage of the resistor R51 becomes equal to the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54. If the voltage generated at the resistor R55 by the collector current of the transistor TR53 is equal to the voltage of the negative power supply input terminal V52, the voltage of the output terminal OSl becomes 0.
Next, if the negative power supply input terminal V52 varies and the voltage thereof is reduced to half, the voltage of the resistor R53 is reduced to about half because the positive input terminal IN51 and the negative input terminal IN52 are at ground potential. When the voltage of the resistor R53 is reduced to about half, the current of the resistor R53 is reduced to half and the current flowing into the resistors R51 and R52 is reduced to half. The voltage of the resistor R51 is reduced to half and the transistor TR53 operates so as to adjust the collector current of the transistor TR53 so that the voltage of the resistor R51 becomes equal to the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54. Thus, the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54 is reduced to half.
lo Since the base-emitter voltage of the transistor TR53 is not proportional to the emitter current of the transistor TR53 and is almost constant, if the base-emitter voltage of the transistor TR53 plus the voltage of the resistor R54 is reduced to half, the voltage of the resistor R54 is lessened to half or lS less. This means that the current flowing between the collector and emitter of the transistor TR53 is lessened to half or less and the voltage of the resistor RSS is lessened to half or less. When the voltage of the resistor R55 is lessened to half or less, the voltage of the output terminal 051 becomes the voltage difference between the resistor R55 and the negative power supply input terminal VS2, thus a negative offset error occurs.
Thus, variation of the power supply current of the DC
amplifier S is caused by the input signal and as the power 2s supply current varies, the power supply voltage varies. When the power supply voltage varies, an offset error occurs in the DC amplifier 5. Therefore, in the DC amplifier S, an offset error occurs because of the power supply voltage variation caused by the input signal. Hitherto, to suppress power supply voltage variation caused by power supply current variation, a capacitor has been added to the power supply connected to the DC amplifier 5; the power supply current variation is replaced with charge/discharge of the capacitor of the power supply and the power supply voltage is proportional to the charge amount accumulated in the capacitor and thus proportional to the change amount integral value of the power supply current.
Therefore, the power supply voltage variation caused by the input signal is proportional to the integral value of the charge amount accumulated in the capacitor, thus the offset error occurring because of the power supply voltage variation is proportional to the integral value of the input signal strength.
Thus, in the conventional DC amplifier, an offset error occurs depending on the temperature stability or power supply voltage variation rate resulting from an input signal. The offset error is proportional to the integral value of the input signal strength.
SUMMARY QF THE INVENTION
It is therefore an object of the invention to provide an offset correction circuit for predicting an offset error from the input signal strength in a DC amplifier of known electric characteristics and a known structure and generating a signal for canceling the offset error, thereby correcting the offset error caused by the input signal, and a high-accurate DC
amplification circuit including the offset correction circuit.
According to the invention, there is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, the offset correction circuit comprising:
lo an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC
g amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC
amplifiers, the offset correction circuit comprising: an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the input stage of the DC
lo amplifier at the preceding stage and the input stage of the DC
amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC
amplification circuit, caused by the input signal to each DC
amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit comprising a plurality of DC
amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC
amplifiers, the offset correction circuit comprising: an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, the integrator being connected between the output stage of the DC
amplifier at the preceding stage and the input stage of the DC
amplifier at the following stage, wherein the correction signal output from the integrator is combined with an input signal input from the DC amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC
lo amplification circuit, caused by the input signal to each DC
amplifier is corrected.
There is provided an offset correction circuit for correcting an offset error occurring in an output signal from a DC amplification circuit, the offset correction circuit comprising: an A/D converter for converting an output signal from the DC amplification circuit into a time series numeric signal and outputting the numeric signal, the A/D converter being connected to an output stage of the DC amplification circuit; and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from the A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, the processing unit being connected to an output stage of the A/D converter, wherein an offset error occurring in an output signal of the DC
, amplification circuit, caused by the input signal to the DC
amplification circuit is corrected.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC
amplifier at a preceding stage to generate a correction signal lo and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC
-amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, the integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier o at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
There is provided a DC amplification circuit comprising: a plurality of DC amplifiers connected at a plurality of stages; a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC
amplifier at a preceding stage to generate a correction signal zo and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, the integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from the integrator with an input signal input from the DC amplifier at . .
the intermediate stage via the match resistor to the DC
amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC amplifier.
There is provided a DC amplification circuit comprising: a DC amplifier; an A/D converter for converting an output signal from the DC amplifier into a time series numeric signal and outputting the numeric signal, the A/D converter being connected to an output stage of the DC amplifier; and a 0 processing unit for performing predetermined integration processing for integrating the time series numeric signal output from the A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, the processing unit being connected to an output stage of the A/D converter, wherein an offset error correction function is provided for correcting an offset error occurring in an output signal of the DC
amplification circuit, caused by an input signal to the DC
amplifier.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a diagram to show a DC amplification circuit including an offset correction circuit of a first embodiment of the invention;
_ FIG. 2 is a diagram to show a DC amplification circuit including an offset correction circuit of a second embodiment of the invention;
FIG. 3 is a diagram to show a DC amplification circuit including an offset correction circuit of a third embodiment of the invention;
FIG. 4 is a diagram to show a DC amplification circuit including an offset correction circuit of a fourth embodiment of the invention; and 0 FIG. 5 is a diagram to show a basic circuit configuration of a conventional DC amplifier.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the accompanying drawings, there are shown preferred embodiments of the invention.
(First Embodiment) FIG. 1 is a diagram to show a first embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 1 is a diagram to show the circuit configuration of a DC amplification circuit 1 including an offset correction circuit 11 of the first embodiment of the invention. In FIG.
1, the DC amplification circuit 1 is made up of the offset correction circuit 11 consisting of an integrator Sll and resistors Rll and R13, DC amplifiers All and A12, and resistors R12 and R14.
. _ The DC amplifier All amplifies a signal input through an input terminal IN11 and outputs the amplified signal to the resistor Rll of the offset correction circuit 11 and the resistor R12.
sThe resistor R12 is connected to output of the DC
amplifier All in series and the resistor R14 is connected to input of the DC amplifier A12 at the stage following the resistor R12 in parallel and is grounded at one end. The resistors R12 and R14 are match resistors for cascading the DC
loamplifiers All and A12. The resistor R12 has a larger impedance than that of the output resistor of the DC amplifier All.
The offset correction circuit 11, which is made up of the integrator Sll and the resistors Rll and R13, corrects an 5offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from an input signal in the DC amplifiers All and A12.
The integrator Sll is connected in parallel with the 20resistor R12 between output of the DC amplifier All and input of the DC amplifier A12. The resistor Rll is connected to input of the integrator Sll in series and the resistor R13 is connected to output of the integrator Sll in series. The integrator Sll, which has predetermined characteristics, z5performs integration-based operation processing according to a separation signal input through the resistor Rll and outputs to the resistor R13 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A11 and A12.
5The DC amplifier A12 amplifies a signal provided by combining a signal from the resistor R12 and the correction signal from the resistor R13 of the offset correction circuit 11 and input through the resistor R14, and outputs the amplified signal to an output terminal O11.
loNext, the operation of the first embodiment is as follows:
A signal input through an input terminal IN11 in FIG.
1 to the DC amplifier A11 is amplified and output to the resistor Rll of the offset correction circuit 11 and the 5resistor R12. The signal input to the resistor R12 is matched and output to the resistor R14 and the DC amplifier A12. In the offset correction circuit 11, a separation signal input through the resistor Rll to the integrator Sll is converted by integration-based operation processing into a correction signal 20for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers All and A12, and the correction signal is output to the resistor R13.
25The correction signal output through the resistor R13 of the offset correction circuit 11 is combined with the signal output through the resistor R12 and the resultant signal is input to the DC amplifier A12 through the resistor R14 of a match resistor. The signal input to the DC amplifier A12 is amplified and output to the output terminal O11.
If the input and output signals of the integrator Sll are of the same sign, a positive feedback path from the resistor R13 via the resistor R12 to the resistor Rll is produced; the impedance of the resistor R12 is large as compared with the impedance of the output resistor of the DC
lo amplifier All, thus the feedback amount does not exceed 1 and output of the DC amplifier All is little affected by the correction signal from the integrator Sll.
As described above, with the offset correction circuit 11 and the DC amplification circuit 1 of the first embodiment, the offset correction circuit 11 containing the integrator Sll is placed between the output of the DC amplifier All and the input of the DC amplifier A12 and the integrator S11 corrects not only an offset error caused by the input signal in the DC
amplifier All, but also an offset error caused by the input signal in the DC amplifier A12. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers All and A12 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect ._ of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Second Embodiment) A second embodiment of the invention will be discussed wherein an offset correction circuit containing an integrator for correcting an offset error in two DC amplifiers cascaded as in the DC amplification circuit l of the first embodiment is lo connected in another circuit configuration.
FIG. 2 is a diagram to show a second embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 2 is a diagram to show the circuit configuration of a DC amplification circuit 2 including an offset correction circuit 21 of the second embodiment of the invention. In FIG.
2, the DC amplification circuit 2 is made up of the offset correction circuit 21 consisting of an integrator S21 and resistors R21 and R23, DC amplifiers A21 and A22, and resistors R22 and R24.
The DC amplifier A21 amplifies a signal input through an input terminal IN21 and outputs the amplified signal to the resistor R22.
The resistor R22 is connected to output of the DC
amplifier A21 in series and the resistor R24 is connected to input of the DC amplifier A22 at the stage following the resistor R22 in parallel and is grounded at one end. The resistors R22 and R24 are match resistors for cascading the DC
amplifiers A21 and A22.
The offset correction circuit 21, which is made up of the integrator S21 and the resistors R21 and R23, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from lo an input signal in the DC amplifiers A21 and A22.
The integrator S21 is connected in parallel with the DC
amplifier A21 and the resistor R22 between input of the DC
amplifier A21 and input of the DC amplifier A22. The resistor R21 is connected to input of the integrator S21 in series and the resistor R23 is connected to output of the integrator S21 in series. The integrator S21, which has predetermined characteristics, performs integration-based operation processing according to a separation signal input through the resistor R21 and outputs to the resistor R23 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A21 and A22.
The DC amplifier A22 amplifies a signal provided by combining a signal from the resistor R22 and the correction signal from the resistor R23 of the offset correction circuit _..
21 and input through the resistor R24, and outputs the amplified signal to an output terminal 021.
Next, the operation of the second embodiment is as follows:
s A signal is input through an input terminal IN21 in FIG. 2 to the DC amplifier A21 and the resistor R21 of the offset correction circuit 21 and the signal input to the DC
amplifier A21 is amplified and output to the resistor R22. The signal input to the resistor R22 is matched and output to the lo resistor R24 and the DC amplifier A22. In the offset correction circuit 21, a separation signal input through the resistor R21 to the integrator S21 is converted by integration-based operation processing into a correction signal for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers A21 and A22, and the correction signal is output to the resistor R23.
The correction signal output through the resistor R23 of the offset correction circuit 21 is combined with the signal output through the resistor R22 and the resultant signal is input to the DC amplifier A22 through the resistor R24 of a match resistor. The signal input to the DC amplifier A22 is amplified and output to the output terminal 021.
As described above, with the offset correction circuit 21 and the DC amplification circuit 2 of the second embodiment, the offset correction circuit 21 containing the integrator S21 is placed between the input of the DC amplifier A21 and the input of the DC amplifier A22 in parallel with the DC amplifier A21 and the resistor R22, and the integrator S21 corrects not only an offset error caused by the input signal in the DC
amplifier A21, but also an offset error caused by the input signal in the DC amplifier A22. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or lo power supply voltage variation rate resulting from the input signal in the DC amplifiers A21 and A22 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Third Embodiment) In the first and second embodiments, the DC
amplification circuit including the offset correction circuit for correcting an offset error in the two DC amplifiers cascaded has been discussed. In a third embodiment of the invention, a DC amplification circuit using three DC amplifiers cascaded will be discussed.
._ FIG. 3 is a diagram to show a third embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 3 is a diagram to show the circuit configuration of a DC amplification circuit 3 including an offset correction circuit 31 of the third embodiment of the invention. In FIG.
3, the DC amplification circuit 3 is made up of the offset correction circuit 31 consisting of an integrator S31 and o resistors R31 and R35, DC amplifiers A31, A32, and A33, and resistors R32, R33, R34, and R36.
The DC amplifier A31 amplifies a signal input through an input terminal IN31 and outputs the amplified signal to the resistor R32 and the resistor R31 of the offset correction circuit 31.
The resistor R32 is connected to output of the DC
amplifier A31 in series and the resistor R33 is connected to input of the DC amplifier A32 at the stage following the resistor R32 in parallel and is grounded at one end. The resistors R32 and R33 are match resistors for cascading the DC
amplifiers A31 and A32.
The DC amplifier A32 amplifies a signal input through the resistor R33 from the resistor R32 and outputs the amplified signal to the resistor R34.
The resistor R34 is connected to output of the DC
amplifier A32 in series and the resistor R36 is connected to input of the DC amplifier A33 at the stage following the resistor R34 in parallel and is grounded at one end. The resistors R34 and R36 are match resistors for cascading the DC
amplifiers A32 and A33.
The offset correction circuit 31, which is made up of the integrator S31 and the resistors R31 and R35, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from lo an input signal in the DC amplifiers A31, A32, and A33.
The integrator S31 is connected in parallel with the resistor R32, the DC amplifier A32, and the resistor R34 between output of the DC amplifier A31 and output of the DC
amplifier A32. The resistor R31 is connected to input of the integrator S31 in series and the resistor R35 is connected to output of the integrator S31 in series. The integrator S31, which has predetermined characteristics, performs integration-based operation processing according to a separation signal input through the resistor R31 and outputs to the resistor R35 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A31, A32, and A33.
The DC amplifier A33 amplifies a signal provided by combining a signal from the resistor R34 and the correction signal from the resistor R35 of the offset correction circuit 31 and input through the resistor R36, and outputs the amplified signal to an output terminal 031.
Next, the operation of the third embodiment is as follows:
A s ignal input through an input terminal IN31 in FIG.
3 to the DC amplifier A31 is amplified and output to the resistors R31 of the offset correction circuit 31 and the resistor R32. The signal input to the resistor R32 is matched and output to the resistor R33 and the DC amplifier A32. The lo signal input from the resistor R32 through the resistor R33 to the DC amplifier A32 is amplified and output to the resistor R34. The signal input to the resistor R34 is matched and output to the resistor R36 and the DC amplifier A33. In the offset correction circuit 31, a separation signal input through the resistor R31 to the integrator S31 is converted by integration-based operation processing into a correction signal for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers A31, A32, and A33, and the correction signal is output to the resistor R35. The correction signal output through the resistor R35 of the offset correction circuit 31 is combined with the signal output through the resistor R34 and the resultant signal is input to the DC amplifier A33 through the resistor R36 of a match resistor. The signal input to the DC amplifier A33 is amplified and output to the output terminal 031.
As described above, with the offset correction circuit 31 and the DC amplification circuit 3 of the third embodiment, the offset correction circuit 31 containing the integrator S31 is placed between the output of the DC amplifier A31 and the output of the DC amplifier A32 in parallel with the resistor R32, the DC amplifier A32, and the resistor R34, and the integrator S31 corrects not only an offset error caused by the lo input signal in the DC amplifier A31, but also an offset error caused by the input signal in the DC amplifiers A32 and A33.
Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC
amplifiers A31, A32, and A33 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Fourth Embodiment) In the first to third embodiments, the offset correction circuit uses the integrator. A DC amplification circuit including an offset correction circuit using an A/D
converter and a processing unit in a fourth embodiment of the invention will be discussed.
FIG. 4 is a diagram to show a fourth embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 4 is a diagram to show the circuit configuration of a DC amplification circuit 4 including an offset correction circuit 41 of the fourth embodiment of the invention. In FIG.
The DC amplifier A31 amplifies a signal input through an input terminal IN31 and outputs the amplified signal to the resistor R32 and the resistor R31 of the offset correction circuit 31.
The resistor R32 is connected to output of the DC
amplifier A31 in series and the resistor R33 is connected to input of the DC amplifier A32 at the stage following the resistor R32 in parallel and is grounded at one end. The resistors R32 and R33 are match resistors for cascading the DC
amplifiers A31 and A32.
The DC amplifier A32 amplifies a signal input through the resistor R33 from the resistor R32 and outputs the amplified signal to the resistor R34.
The resistor R34 is connected to output of the DC
amplifier A32 in series and the resistor R36 is connected to input of the DC amplifier A33 at the stage following the resistor R34 in parallel and is grounded at one end. The resistors R34 and R36 are match resistors for cascading the DC
amplifiers A32 and A33.
The offset correction circuit 31, which is made up of the integrator S31 and the resistors R31 and R35, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from lo an input signal in the DC amplifiers A31, A32, and A33.
The integrator S31 is connected in parallel with the resistor R32, the DC amplifier A32, and the resistor R34 between output of the DC amplifier A31 and output of the DC
amplifier A32. The resistor R31 is connected to input of the integrator S31 in series and the resistor R35 is connected to output of the integrator S31 in series. The integrator S31, which has predetermined characteristics, performs integration-based operation processing according to a separation signal input through the resistor R31 and outputs to the resistor R35 a correction signal for canceling an offset error proportional to the integral value of the input signal strength, caused by an input signal in the DC amplifiers A31, A32, and A33.
The DC amplifier A33 amplifies a signal provided by combining a signal from the resistor R34 and the correction signal from the resistor R35 of the offset correction circuit 31 and input through the resistor R36, and outputs the amplified signal to an output terminal 031.
Next, the operation of the third embodiment is as follows:
A s ignal input through an input terminal IN31 in FIG.
3 to the DC amplifier A31 is amplified and output to the resistors R31 of the offset correction circuit 31 and the resistor R32. The signal input to the resistor R32 is matched and output to the resistor R33 and the DC amplifier A32. The lo signal input from the resistor R32 through the resistor R33 to the DC amplifier A32 is amplified and output to the resistor R34. The signal input to the resistor R34 is matched and output to the resistor R36 and the DC amplifier A33. In the offset correction circuit 31, a separation signal input through the resistor R31 to the integrator S31 is converted by integration-based operation processing into a correction signal for canceling an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifiers A31, A32, and A33, and the correction signal is output to the resistor R35. The correction signal output through the resistor R35 of the offset correction circuit 31 is combined with the signal output through the resistor R34 and the resultant signal is input to the DC amplifier A33 through the resistor R36 of a match resistor. The signal input to the DC amplifier A33 is amplified and output to the output terminal 031.
As described above, with the offset correction circuit 31 and the DC amplification circuit 3 of the third embodiment, the offset correction circuit 31 containing the integrator S31 is placed between the output of the DC amplifier A31 and the output of the DC amplifier A32 in parallel with the resistor R32, the DC amplifier A32, and the resistor R34, and the integrator S31 corrects not only an offset error caused by the lo input signal in the DC amplifier A31, but also an offset error caused by the input signal in the DC amplifiers A32 and A33.
Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC
amplifiers A31, A32, and A33 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit containing the integrator cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
(Fourth Embodiment) In the first to third embodiments, the offset correction circuit uses the integrator. A DC amplification circuit including an offset correction circuit using an A/D
converter and a processing unit in a fourth embodiment of the invention will be discussed.
FIG. 4 is a diagram to show a fourth embodiment of the invention in a DC amplification circuit including an offset correction circuit incorporating the invention.
First, the configuration will be discussed.
FIG. 4 is a diagram to show the circuit configuration of a DC amplification circuit 4 including an offset correction circuit 41 of the fourth embodiment of the invention. In FIG.
4, the DC amplification circuit 4 is made up of a DC amplifier A41 and the offset correction circuit 41 consisting of an A/D
converter AD41 and a processing unit PU41.
The DC amplifier A41 amplifies a signal input through an input terminal IN41 and outputs the signal containing an offset error to the A/D converter AD41 of the offset correction circuit 41. The offset error occurs depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41 and is proportional to the integral value of the input signal strength.
The offset correction circuit 41, which consists of the A/D converter AD41 and the processing unit PU41, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41.
The A/D converter AD41, which is connected to output of the DC amplifier A41, converts the signal containing an offset error input from the DC amplifier A41 into a time series numeric signal and outputs the numeric signal to the processing unit PU41.
The processing unit PU41, which is connected to output of the A/D converter AD41, performs integration-based operation processing with predetermined order and coefficients to generate a time series correction numeric signal from the time lo series numeric signal input from the A/D converter AD41, adds the time series correction numeric signal to the time series numeric signal to generate a time series numeric signal for canceling an offset error, and outputs this time series numeric signal to the output terminal 041.
Next, the operation of the fourth embodiment is as follows:
A signal input through an input terminal IN41 in FIG.
4 to the DC amplifier A41 is amplified and the amplified signal containing an offset error is output to the A/D converter AD41 of the offset correction circuit 41. The signal containing an offset error input to the A/D converter AD41 is converted into a time series numeric signal, which is then output to the processing unit PU41. The time series numeric signal input to the processing unit PU41 is added to a time series correction numeric signal generated by performing integration-based operation processing with predetermined degree and ,. .
coefficients, and the resultant signal is output to the output terminal 041 as a time series numeric signal for canceling the offset error.
As described above, with the offset correction circuit 41 and the DC amplification circuit 4 of the fourth embodiment, the offset correction circuit 41 consisting of the A/D
converter AD41 and the processing unit PU41 is placed at output of the DC amplifier A41 and the A/D converter AD41 and the processing unit PU41 correct an offset error caused by the lo input signal in the DC amplifier A41. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit consisting of the A/D converter and the processing unit cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
In the first to fourth embodiments, in case of cascading the DC amplifiers at multiple stages, the offset correction circuit can also correct an offset error in all the DC amplifiers.
._..
According to the offset correction circuit of the invention, in the DC amplification circuit, the offset correction circuit containing the integrator (or the A/D
converter and the processing unit) can cancel the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal.
According to the DC amplification circuit of the invention, the offset correction circuit containing the lo integrator (or the A/D converter and the processing unit) can cancel the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
converter AD41 and a processing unit PU41.
The DC amplifier A41 amplifies a signal input through an input terminal IN41 and outputs the signal containing an offset error to the A/D converter AD41 of the offset correction circuit 41. The offset error occurs depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41 and is proportional to the integral value of the input signal strength.
The offset correction circuit 41, which consists of the A/D converter AD41 and the processing unit PU41, corrects an offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41.
The A/D converter AD41, which is connected to output of the DC amplifier A41, converts the signal containing an offset error input from the DC amplifier A41 into a time series numeric signal and outputs the numeric signal to the processing unit PU41.
The processing unit PU41, which is connected to output of the A/D converter AD41, performs integration-based operation processing with predetermined order and coefficients to generate a time series correction numeric signal from the time lo series numeric signal input from the A/D converter AD41, adds the time series correction numeric signal to the time series numeric signal to generate a time series numeric signal for canceling an offset error, and outputs this time series numeric signal to the output terminal 041.
Next, the operation of the fourth embodiment is as follows:
A signal input through an input terminal IN41 in FIG.
4 to the DC amplifier A41 is amplified and the amplified signal containing an offset error is output to the A/D converter AD41 of the offset correction circuit 41. The signal containing an offset error input to the A/D converter AD41 is converted into a time series numeric signal, which is then output to the processing unit PU41. The time series numeric signal input to the processing unit PU41 is added to a time series correction numeric signal generated by performing integration-based operation processing with predetermined degree and ,. .
coefficients, and the resultant signal is output to the output terminal 041 as a time series numeric signal for canceling the offset error.
As described above, with the offset correction circuit 41 and the DC amplification circuit 4 of the fourth embodiment, the offset correction circuit 41 consisting of the A/D
converter AD41 and the processing unit PU41 is placed at output of the DC amplifier A41 and the A/D converter AD41 and the processing unit PU41 correct an offset error caused by the lo input signal in the DC amplifier A41. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the DC amplifier A41 can be canceled.
Therefore, in the DC amplification circuit, the offset correction circuit consisting of the A/D converter and the processing unit cancels the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
In the first to fourth embodiments, in case of cascading the DC amplifiers at multiple stages, the offset correction circuit can also correct an offset error in all the DC amplifiers.
._..
According to the offset correction circuit of the invention, in the DC amplification circuit, the offset correction circuit containing the integrator (or the A/D
converter and the processing unit) can cancel the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal.
According to the DC amplification circuit of the invention, the offset correction circuit containing the lo integrator (or the A/D converter and the processing unit) can cancel the effect of the offset error occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal, so that the input signal can be amplified and output with high accuracy.
Claims (14)
1. An offset correction circuit for correcting an offset error occurring in an output signal from a DC
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
2. The offset correction circuit according to claim 1, further comprising two resistors connected respectively to input and output of said integrator in series.
3. An offset correction circuit for correcting an offset error occurring in an output signal from a DC
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
4. The offset correction circuit according to claim 3, further comprising two resistors connected respectively to input and output of said integrator in series.
5. An offset correction circuit for correcting an offset error occurring in an output signal from a DC
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
amplification circuit comprising a plurality of DC amplifiers connected at a plurality of stages and a match resistor connected between output and input stages of the DC amplifiers, said offset correction circuit comprising:
an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein the correction signal output from said integrator is combined with an input signal input from the DC
amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage so that an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to each DC amplifier is corrected.
6. The offset correction circuit according to claim 5, further comprising two resistors connected respectively to input and output of said integrator in series.
7. An offset correction circuit for correcting an offset error occurring in an output signal from a DC
amplification circuit, said offset correction circuit comprising:
an A/D converter for converting an output signal from the DC amplification circuit into a time series numeric signal and outputting the numeric signal, said A/D converter being connected to an output stage of the DC amplification circuit;
and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from said A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, said processing unit being connected to an output stage of said A/D converter, wherein an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to the DC amplification circuit is corrected.
amplification circuit, said offset correction circuit comprising:
an A/D converter for converting an output signal from the DC amplification circuit into a time series numeric signal and outputting the numeric signal, said A/D converter being connected to an output stage of the DC amplification circuit;
and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from said A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, said processing unit being connected to an output stage of said A/D converter, wherein an offset error occurring in an output signal of the DC amplification circuit, caused by the input signal to the DC amplification circuit is corrected.
8. A DC amplification circuit comprising:
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
9. The DC amplification circuit according to claim 8, further comprising two resistors connected respectively to input and output of said integrator in series.
10. A DC amplification circuit comprising:
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an input signal to the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the input stage of the DC amplifier at a following stage, said integrator being connected between the input stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the preceding stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
11. The DC amplification circuit according to claim 10, further comprising two resistors connected respectively to input and output of said integrator in series.
12. A DC amplification circuit comprising:
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
a plurality of DC amplifiers connected at a plurality of stages;
a match resistor connected between output and input stages of the DC amplifiers; and an integrator for performing predetermined integration processing for integrating a separation signal separated from an output signal from the DC amplifier at a preceding stage to generate a correction signal and outputting the correction signal to the output stage of the DC amplifier at an intermediate stage, said integrator being connected between the output stage of the DC amplifier at the preceding stage and the input stage of the DC amplifier at the following stage, wherein an offset error correction function is provided for combining the correction signal output from said integrator with an input signal input from the DC amplifier at the intermediate stage via the match resistor to the DC amplifier at the following stage and correcting an offset error occurring in an output signal, caused by the input signal to each DC
amplifier.
13. The DC amplification circuit according to claim 12, further comprising two resistors connected respectively to input and output of said integrator in series.
14. A DC amplification circuit comprising:
a DC amplifier;
an A/D converter for converting an output signal from said DC amplifier into a time series numeric signal and outputting the numeric signal, said A/D converter being connected to an output stage of said DC amplifier; and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from said A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, said processing unit being connected to an output stage of said A/D converter, wherein an offset error correction function is provided for correcting an offset error occurring in an output signal of said DC amplification circuit, caused by an input signal to said DC amplifier.
a DC amplifier;
an A/D converter for converting an output signal from said DC amplifier into a time series numeric signal and outputting the numeric signal, said A/D converter being connected to an output stage of said DC amplifier; and a processing unit for performing predetermined integration processing for integrating the time series numeric signal output from said A/D converter to generate a time series correction numeric signal, combining the time series correction numeric signal with the time series numeric signal, and outputting the resultant signal, said processing unit being connected to an output stage of said A/D converter, wherein an offset error correction function is provided for correcting an offset error occurring in an output signal of said DC amplification circuit, caused by an input signal to said DC amplifier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25904597A JP3381572B2 (en) | 1997-09-24 | 1997-09-24 | Offset correction circuit and DC amplifier circuit |
| JP9-259045 | 1997-09-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2248337A1 CA2248337A1 (en) | 1999-03-24 |
| CA2248337C true CA2248337C (en) | 2001-09-04 |
Family
ID=17328575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002248337A Expired - Fee Related CA2248337C (en) | 1997-09-24 | 1998-09-22 | Offset correction circuit and dc amplification circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6239643B1 (en) |
| EP (1) | EP0905882A1 (en) |
| JP (1) | JP3381572B2 (en) |
| CA (1) | CA2248337C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7126568B2 (en) * | 2001-10-19 | 2006-10-24 | Clare Micronix Integrated Systems, Inc. | Method and system for precharging OLED/PLED displays with a precharge latency |
| US8903687B1 (en) * | 2007-08-17 | 2014-12-02 | Keithley Instruments, Inc. | Dielectric absorption compensation for a measurement instrument |
| US9054660B1 (en) * | 2014-01-10 | 2015-06-09 | Analog Devices Global | Amplifying system |
| CN120342340B (en) * | 2025-06-17 | 2025-11-18 | 深圳飞骧科技股份有限公司 | Bias circuit and power amplification circuit |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4453132A (en) * | 1982-04-21 | 1984-06-05 | Motorola, Inc. | Active filter |
| JP3164476B2 (en) * | 1994-06-06 | 2001-05-08 | 日本電子株式会社 | Rectangular filter and filter amplifier using the same |
| US5519328A (en) * | 1994-10-28 | 1996-05-21 | Keithley Instruments, Inc. | Compensation for dielectric absorption effect |
| US5659269A (en) * | 1995-03-13 | 1997-08-19 | Harris Corporation | Zero phase error switched-capacitor phase locked loop filter |
| EP0744829B1 (en) * | 1995-05-22 | 2003-01-15 | STMicroelectronics S.r.l. | A high-pass filter, particularly for cancelling out the offset in a chain of amplifiers |
| JP4091671B2 (en) * | 1995-08-08 | 2008-05-28 | 松下電器産業株式会社 | DC offset compensator |
| US5646569A (en) * | 1995-08-30 | 1997-07-08 | Hewlett-Packard Company | Method and apparatus for AC coupling |
| US5663680A (en) * | 1996-04-04 | 1997-09-02 | Nordeng; Arnold E. | Chopper stabilized amplifier having an additional differential amplifier stage for improved noise reduction |
-
1997
- 1997-09-24 JP JP25904597A patent/JP3381572B2/en not_active Expired - Fee Related
-
1998
- 1998-09-17 EP EP98117645A patent/EP0905882A1/en not_active Withdrawn
- 1998-09-22 CA CA002248337A patent/CA2248337C/en not_active Expired - Fee Related
- 1998-09-23 US US09/159,121 patent/US6239643B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1197948A (en) | 1999-04-09 |
| CA2248337A1 (en) | 1999-03-24 |
| EP0905882A1 (en) | 1999-03-31 |
| US6239643B1 (en) | 2001-05-29 |
| JP3381572B2 (en) | 2003-03-04 |
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