CA2235440A1 - Cross-connecting apparatus - Google Patents
Cross-connecting apparatus Download PDFInfo
- Publication number
- CA2235440A1 CA2235440A1 CA 2235440 CA2235440A CA2235440A1 CA 2235440 A1 CA2235440 A1 CA 2235440A1 CA 2235440 CA2235440 CA 2235440 CA 2235440 A CA2235440 A CA 2235440A CA 2235440 A1 CA2235440 A1 CA 2235440A1
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- signals
- channels
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- cross
- storing
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54508—Configuration, initialisation
- H04Q3/54533—Configuration data, translation, passwords, databases
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13103—Memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13106—Microprocessor, CPU
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13292—Time division multiplexing, TDM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1332—Logic circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1334—Configuration within the switch
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Databases & Information Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
A cross-connecting apparatus is disclosed, that comprises a multi-port TSW (time switch) having m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting circuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an output port.
Description
CA 0223~440 1998-04-21 CROSS-CONNECTING APPARATUS
Backgrouncl of the Invention 1. Field of the Invention The present invention relates to a cross-connecting apparatus used in a telephone exchange of an optical communication system and for cross-connecting high speed signals.
Backgrouncl of the Invention 1. Field of the Invention The present invention relates to a cross-connecting apparatus used in a telephone exchange of an optical communication system and for cross-connecting high speed signals.
2. Description of the Related Art ln recent years, a cross-connecting apparatus that multiplexes signals of a predetermined number of channels and output:s the multiplexed signals to a desired port in a transmission system has been used.
E'ig. 3 is a block diagram for explaining a conventional cross-connecting apparatus that cross-connects signals of a channels (where a is any integer larger than 2).
In Fig. 3, reference numeral 10 represents a multiplexing circuit. Reference numeral 20 represents a selecting circuit.
Refere!nce numerals 30 and 40 represent bit storing devices.
Refere!nce numeral 50 represents a selecting circuit. Reference numeral 60 represents a demultiplexing circuit.
Data signals of a channels are sent to the multiplexing circuit 10. The multiplexing circuit 10 multiplexes the signals of a channels to a multiplexed signal of one channel.
The multiplexed signal is sent to the selecting circuit 20 on a writing side. The selecting circuit 20 alternately writes the multiplexed signal to the storing devices 30 and 40.
The selecting circuit 5t) on a reading side changes the order of output signals of the storing devices 30 and 40 corresponding CA 0223~440 1998-04-21 to read addresses thereof. The multiplexed signal selectively read from the storing devices 30 and 40 is sent to the demu:Ltiplexing circuit 60. The demultiplexing circuit 60 demu:Ltiplexes the output signal of the selecting circuit 50 into para:Llel signals of a channels. The parallel signals of a channels of the demultiplexing circuit 60 are sent to respective OUtpllt ports. Thus, by changing read addresses of the storing devices 30 and 40, a signal of a desired channel is output from a desired port.
Although the conventi.onal cross-connecting apparatus is operated as described above, since signals of a channels are multiplexed to a signal of one channel at the multiplexing circuit 10, if the transmission rate of signals of a channels (parallel signals) is kept, the transmission rate of the multiplexed signal should be increased a times the transmission rate of the parallel signals.
Thus, when high speed signals of many channels are cross-connected, a high speed storing device is required.
In other words, a storing device stores a multiplexed signal of which signals of all channels have been multiplexed. Thus, it is difficult to accomplish a high speed storing device that can store and update a multiplexed signal at such a high transmission rate. In the above-described related art reference, two storing devices are used. The frequencies of signals should be converted into a frequency at which these storing devices operate. In this case, when high speed signals of many channels are cross-connected, a high speed storing device is required. Thus, the power consumption becomes large.
CA 0223~440 1998-04-21 Summary of the Invention The present invention i.s made from the above-descried point of view. An object of the present invention is to provide a cross--connecting apparatus that allows signals of many channels to be cross-connected at high speed and low power consumption without need to use a high speed storing device.
A first aspect of the present invention is a cross-connecting apparatus for cross-connecting signals of many channels, comprising a multi-port TSW (time switch) having m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting ci:rcuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an ou.tput port.
P. second aspect of the present invention is a cross-connecting apparatus for cross-connecting signals of many channe!ls (a channels), comprising m multiplexing circuits for converting a signal of a channels into m signals of n channels, a mult.i-port TSW (time switch) having m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting CA 0223~440 1998-04-21 circuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an output port, and m demu]tiplexing circuits for demultiplexing the multiplexed signals of n channels received from the output port of the multi-port TSW to signals of a channels.
Further, the multi-port TSW is composed of a multi-port RAM.
Furthermore, the multi-port RAM is composed of a custom LSI.
Thus, the cross-connecting apparatus according to the present invention can cross-connect signals of many channels at high speed.
These and other objects, features and advantages of the prese!nt invention will bec:ome more apparent in light of the follc,wing detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
Brief Description of Drawings Fig. 1 is a block diagram showing the structure of a cross-connecting apparatus according to an embodiment of the present invention;
Fig. 2 is a block diagram showing the structure of a cross-connecting apparatus according to another embodiment of the present invention; and Fig. 3 is a block diagram for explaining the structure of a conventional cross-connecting apparatus.
CA 0223~440 1998-04-21 Description of Preferred Embodiments An embodiment of the present invention will be described with reference to the accompanying drawings.
E~ig. 1 is a block diagram showing the structure of a cross-connec:ting apparatus according to an embodiment of the presentinvent;ion. Referring to Fig. 1, signals of a channels are cross-connec:ted.
~ n Fig. 1, reference numeral 1 represents m multiplexing circuits that multiplex signals of a channels to signals of m channels (where a > m). Reference numeral 2 represents m separaLting circuits (serial-parallel converting circuits) that separa,tes signals received from the m multiplexing circuits 1 to signals of a channels. Reference numeral 3 represents a storing circuits that store the signals of a channels. Reference numeral 4 represents m selecting circuits that select signals of a channels corresponding to read addresses of the a storing circuits 3 and multiplex the signals of a channels to signals of m channels. Reference numeral 5 represents m demultiplexing circuits that convert the multiplexed signals of m channels to signals of a channels.
A circuit block composecl of the m separating circuits 2, the a storing circuits 3, and the m selecting circuits 4 is referred to as TSW (time switch) portion 100.
Next, the operation of the cross-connecting apparatus :25 according to the embodiment will be described.
Each of the m multiplexing circuits 1 multiplexes signals of n channels of signals of a channels to signals (where a > n).
CA 0223~440 1998-04-21 Thus, the m multiplexing circuits 1 convert signals of a channels signals of a channels into signals of m channels. The m separating circuits 2 convert the multiplexed signals of m channels into signals of a channels. The a storing circuits 3 store the signals of a channels. The m selecting circuits 4 on the output side select the signals of a channels corresponding to read addresses of the a storing circuits 3 on time division basis, multiplex the signals of a channels to multiplexed signals of n channels (each of the m selecting circuits 4 multiplexes signals of n channels to a multiplexed signal), and outputs the multiplexed signals of n channels to the m demultiplexing circuits 5. When the multiplexed signals of n channels are read from the a selecting circuits 4, these signals are cross-connected corresponding to a control signal received from a controlling circuit 6 controlled by a CPU 7 corresponding to a comma,nd received from an operation panel 8. The m demultiplexing circuits 5 convert the multiplexed signals of m channels into signals of a channels.
In other words, according to the present invention, each of the m multiplexing circuits multiplexes signals of n channels of signals of a channels to a multiplexed signal. In total, the m multiplexing circuits multiplex signals of a channels to signals of m channels. Thus, high speed signals of many channels can be processed at high speed. Each of the m separating circuits separates a multiplexed signal to signals of n channels. The resultant signals of a channels are stored in a storing devices.
Thus, even if the storing speeds of the storing circuits are not CA 0223~440 1998-04-21 very high, the signals can be stored on real time basis. In addition, since the reading side has the same structure as the writing side, high speed signals of many channels can be cross-connected.
5Fig. 2 is a block diagram showing the structure of a cross-connecting apparatus according to another embodiment of the present invention. Referring to Fig. 2, the cross-connecting apparatus cross-connects siqnals of 256 channels.
][n Fig. 2, reference numeral 1 represents 64 multiplexing 10circuits. Each of the 64 multiplexing circuits 1 multiplexes signa]Ls of four channels to a signal of one channel. Thus, the 64 muLtiplexing circuits 1 multiplex signals of 256 channels to signa]s of 64 signals. Reference numeral 2 represents 64 separating circuits (serial-parallel converting circuits). Each 15of the 64 separating circuits 2 is composed of an eight-bit shift regist:er. In other words, t:he 64 separating circuits 2 perform a process for 256 channels x 2 bits. The 64 separating circuits 2 separates the signals of 64 signals to signals of 256 channels.
~eference numeral 3 represents 256 storing circuits. Each 20of the 256 storing circuits 3 is composed of a register.
Refere!nce numeral 4 represents 64 selecting circuits. Each of the 64 selecting circuits 4 selects signals stored in the 256 storing circuit 3 corresponding to read addresses thereof, reads these signals, and converts these signals to signals of four 25channels. Thus, the 64 selecting circuit 4 convert signals of 256 channels into signals of 64 channels. Reference numeral 5 represents 64 demultiplexing circuits that convert signals of 64 channels received from the 64 selecting circuits 4 into signals CA 0223~440 1998-04-21 of 256 channels. Reference numeral 6 represents a CPU
controlling circuit. The CPU controlling circuit 6 outputs a control signal to the 64 selecting circuits. Reference numeral 7 represents an operation panel with which a command is sent to the (PU controlling circuit 6.
A circuit block composed of the 64 separating circuits (eight-bit shift registers) 2 the 256 storing circuits (registers) 3 and the 64 selecting circuits is referred to as TSW (time switch) portion 100.
10Next the operation of the cross-connecting apparatus according to the embodiment shown in Fig. 2 will be described.
The 64 multiplexing circuits 1 multiplex signals of 256 chann,els to signals of 64 channels and send the resultant signals to the 64 eight-bit shift registers 2 of the TSW portion 100.
15The 64 eight-bit shift registers 2 convert the signals of 64 channels into signals of 256 channels. The signals of 256 channels are stored in the 256 bit-registers 3.
The 64 selecting circuits 4 on the output side select signals of 256 channels from the 256 bit-registers 3 on time division basis corresponding to read addresses of the 256 bit-registers 3 read these signals multiplex the signals of 256 channels to signals of 64 channels and send the resultant signals to the 64 demultiplexing circuits 5. When the 64 selecting circuits 4 read signals from the 256 registers 3 these signals are cross-connected. The 64 demultiplexing circuits 5 convert signals of 64 channels into signals of 256 channels.
rhe TSW (time switch) portion 100 may be composed of a multi-port RAM. Although a commercially available multi-port RAM
CA 0223~440 1998-04-21 may be used, the TSW portion 100 is preferably composed of a custom LSI from a view poin.t of the selection of the number of ports.
i~s described above, in the cross-connecting apparatus according to the present invention, since the transmission rate of mu:ltiplexed signals that are input to the storing devices is decreased, high speed sign~lls of many channels can be cross-connected at low power consumption.
~lthough the present invention has been shown and described with respect to a best mod.e embodiment thereof, it should be understood by those skilled. in the art that the foregoing and various other changes, omissions, and additions in the form and detai.L thereof may be made therein without departing from the spirit: and scope of the present invention.
E'ig. 3 is a block diagram for explaining a conventional cross-connecting apparatus that cross-connects signals of a channels (where a is any integer larger than 2).
In Fig. 3, reference numeral 10 represents a multiplexing circuit. Reference numeral 20 represents a selecting circuit.
Refere!nce numerals 30 and 40 represent bit storing devices.
Refere!nce numeral 50 represents a selecting circuit. Reference numeral 60 represents a demultiplexing circuit.
Data signals of a channels are sent to the multiplexing circuit 10. The multiplexing circuit 10 multiplexes the signals of a channels to a multiplexed signal of one channel.
The multiplexed signal is sent to the selecting circuit 20 on a writing side. The selecting circuit 20 alternately writes the multiplexed signal to the storing devices 30 and 40.
The selecting circuit 5t) on a reading side changes the order of output signals of the storing devices 30 and 40 corresponding CA 0223~440 1998-04-21 to read addresses thereof. The multiplexed signal selectively read from the storing devices 30 and 40 is sent to the demu:Ltiplexing circuit 60. The demultiplexing circuit 60 demu:Ltiplexes the output signal of the selecting circuit 50 into para:Llel signals of a channels. The parallel signals of a channels of the demultiplexing circuit 60 are sent to respective OUtpllt ports. Thus, by changing read addresses of the storing devices 30 and 40, a signal of a desired channel is output from a desired port.
Although the conventi.onal cross-connecting apparatus is operated as described above, since signals of a channels are multiplexed to a signal of one channel at the multiplexing circuit 10, if the transmission rate of signals of a channels (parallel signals) is kept, the transmission rate of the multiplexed signal should be increased a times the transmission rate of the parallel signals.
Thus, when high speed signals of many channels are cross-connected, a high speed storing device is required.
In other words, a storing device stores a multiplexed signal of which signals of all channels have been multiplexed. Thus, it is difficult to accomplish a high speed storing device that can store and update a multiplexed signal at such a high transmission rate. In the above-described related art reference, two storing devices are used. The frequencies of signals should be converted into a frequency at which these storing devices operate. In this case, when high speed signals of many channels are cross-connected, a high speed storing device is required. Thus, the power consumption becomes large.
CA 0223~440 1998-04-21 Summary of the Invention The present invention i.s made from the above-descried point of view. An object of the present invention is to provide a cross--connecting apparatus that allows signals of many channels to be cross-connected at high speed and low power consumption without need to use a high speed storing device.
A first aspect of the present invention is a cross-connecting apparatus for cross-connecting signals of many channels, comprising a multi-port TSW (time switch) having m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting ci:rcuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an ou.tput port.
P. second aspect of the present invention is a cross-connecting apparatus for cross-connecting signals of many channe!ls (a channels), comprising m multiplexing circuits for converting a signal of a channels into m signals of n channels, a mult.i-port TSW (time switch) having m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting CA 0223~440 1998-04-21 circuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an output port, and m demu]tiplexing circuits for demultiplexing the multiplexed signals of n channels received from the output port of the multi-port TSW to signals of a channels.
Further, the multi-port TSW is composed of a multi-port RAM.
Furthermore, the multi-port RAM is composed of a custom LSI.
Thus, the cross-connecting apparatus according to the present invention can cross-connect signals of many channels at high speed.
These and other objects, features and advantages of the prese!nt invention will bec:ome more apparent in light of the follc,wing detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
Brief Description of Drawings Fig. 1 is a block diagram showing the structure of a cross-connecting apparatus according to an embodiment of the present invention;
Fig. 2 is a block diagram showing the structure of a cross-connecting apparatus according to another embodiment of the present invention; and Fig. 3 is a block diagram for explaining the structure of a conventional cross-connecting apparatus.
CA 0223~440 1998-04-21 Description of Preferred Embodiments An embodiment of the present invention will be described with reference to the accompanying drawings.
E~ig. 1 is a block diagram showing the structure of a cross-connec:ting apparatus according to an embodiment of the presentinvent;ion. Referring to Fig. 1, signals of a channels are cross-connec:ted.
~ n Fig. 1, reference numeral 1 represents m multiplexing circuits that multiplex signals of a channels to signals of m channels (where a > m). Reference numeral 2 represents m separaLting circuits (serial-parallel converting circuits) that separa,tes signals received from the m multiplexing circuits 1 to signals of a channels. Reference numeral 3 represents a storing circuits that store the signals of a channels. Reference numeral 4 represents m selecting circuits that select signals of a channels corresponding to read addresses of the a storing circuits 3 and multiplex the signals of a channels to signals of m channels. Reference numeral 5 represents m demultiplexing circuits that convert the multiplexed signals of m channels to signals of a channels.
A circuit block composecl of the m separating circuits 2, the a storing circuits 3, and the m selecting circuits 4 is referred to as TSW (time switch) portion 100.
Next, the operation of the cross-connecting apparatus :25 according to the embodiment will be described.
Each of the m multiplexing circuits 1 multiplexes signals of n channels of signals of a channels to signals (where a > n).
CA 0223~440 1998-04-21 Thus, the m multiplexing circuits 1 convert signals of a channels signals of a channels into signals of m channels. The m separating circuits 2 convert the multiplexed signals of m channels into signals of a channels. The a storing circuits 3 store the signals of a channels. The m selecting circuits 4 on the output side select the signals of a channels corresponding to read addresses of the a storing circuits 3 on time division basis, multiplex the signals of a channels to multiplexed signals of n channels (each of the m selecting circuits 4 multiplexes signals of n channels to a multiplexed signal), and outputs the multiplexed signals of n channels to the m demultiplexing circuits 5. When the multiplexed signals of n channels are read from the a selecting circuits 4, these signals are cross-connected corresponding to a control signal received from a controlling circuit 6 controlled by a CPU 7 corresponding to a comma,nd received from an operation panel 8. The m demultiplexing circuits 5 convert the multiplexed signals of m channels into signals of a channels.
In other words, according to the present invention, each of the m multiplexing circuits multiplexes signals of n channels of signals of a channels to a multiplexed signal. In total, the m multiplexing circuits multiplex signals of a channels to signals of m channels. Thus, high speed signals of many channels can be processed at high speed. Each of the m separating circuits separates a multiplexed signal to signals of n channels. The resultant signals of a channels are stored in a storing devices.
Thus, even if the storing speeds of the storing circuits are not CA 0223~440 1998-04-21 very high, the signals can be stored on real time basis. In addition, since the reading side has the same structure as the writing side, high speed signals of many channels can be cross-connected.
5Fig. 2 is a block diagram showing the structure of a cross-connecting apparatus according to another embodiment of the present invention. Referring to Fig. 2, the cross-connecting apparatus cross-connects siqnals of 256 channels.
][n Fig. 2, reference numeral 1 represents 64 multiplexing 10circuits. Each of the 64 multiplexing circuits 1 multiplexes signa]Ls of four channels to a signal of one channel. Thus, the 64 muLtiplexing circuits 1 multiplex signals of 256 channels to signa]s of 64 signals. Reference numeral 2 represents 64 separating circuits (serial-parallel converting circuits). Each 15of the 64 separating circuits 2 is composed of an eight-bit shift regist:er. In other words, t:he 64 separating circuits 2 perform a process for 256 channels x 2 bits. The 64 separating circuits 2 separates the signals of 64 signals to signals of 256 channels.
~eference numeral 3 represents 256 storing circuits. Each 20of the 256 storing circuits 3 is composed of a register.
Refere!nce numeral 4 represents 64 selecting circuits. Each of the 64 selecting circuits 4 selects signals stored in the 256 storing circuit 3 corresponding to read addresses thereof, reads these signals, and converts these signals to signals of four 25channels. Thus, the 64 selecting circuit 4 convert signals of 256 channels into signals of 64 channels. Reference numeral 5 represents 64 demultiplexing circuits that convert signals of 64 channels received from the 64 selecting circuits 4 into signals CA 0223~440 1998-04-21 of 256 channels. Reference numeral 6 represents a CPU
controlling circuit. The CPU controlling circuit 6 outputs a control signal to the 64 selecting circuits. Reference numeral 7 represents an operation panel with which a command is sent to the (PU controlling circuit 6.
A circuit block composed of the 64 separating circuits (eight-bit shift registers) 2 the 256 storing circuits (registers) 3 and the 64 selecting circuits is referred to as TSW (time switch) portion 100.
10Next the operation of the cross-connecting apparatus according to the embodiment shown in Fig. 2 will be described.
The 64 multiplexing circuits 1 multiplex signals of 256 chann,els to signals of 64 channels and send the resultant signals to the 64 eight-bit shift registers 2 of the TSW portion 100.
15The 64 eight-bit shift registers 2 convert the signals of 64 channels into signals of 256 channels. The signals of 256 channels are stored in the 256 bit-registers 3.
The 64 selecting circuits 4 on the output side select signals of 256 channels from the 256 bit-registers 3 on time division basis corresponding to read addresses of the 256 bit-registers 3 read these signals multiplex the signals of 256 channels to signals of 64 channels and send the resultant signals to the 64 demultiplexing circuits 5. When the 64 selecting circuits 4 read signals from the 256 registers 3 these signals are cross-connected. The 64 demultiplexing circuits 5 convert signals of 64 channels into signals of 256 channels.
rhe TSW (time switch) portion 100 may be composed of a multi-port RAM. Although a commercially available multi-port RAM
CA 0223~440 1998-04-21 may be used, the TSW portion 100 is preferably composed of a custom LSI from a view poin.t of the selection of the number of ports.
i~s described above, in the cross-connecting apparatus according to the present invention, since the transmission rate of mu:ltiplexed signals that are input to the storing devices is decreased, high speed sign~lls of many channels can be cross-connected at low power consumption.
~lthough the present invention has been shown and described with respect to a best mod.e embodiment thereof, it should be understood by those skilled. in the art that the foregoing and various other changes, omissions, and additions in the form and detai.L thereof may be made therein without departing from the spirit: and scope of the present invention.
Claims (8)
1. A cross-connecting apparatus for cross-connecting signals of many channels having a multi-port TSW (time switch), the multi-port TSW comprising:
m separating circuits for separating a multiplexed signal of n channels to n parallel signals;
(n x m) storing circuits for storing n signals of m channels received from said m separating circuits; and m selecting circuits for selecting the n signals of m channels stored in said (n x m) storing circuits on time division basis corresponding to read addresses of said (n x m) storing circuits, reading the n signals of m channels, multiplexing the n siqnals of m channels, and outputting the multiplexed signals to an output port.
m separating circuits for separating a multiplexed signal of n channels to n parallel signals;
(n x m) storing circuits for storing n signals of m channels received from said m separating circuits; and m selecting circuits for selecting the n signals of m channels stored in said (n x m) storing circuits on time division basis corresponding to read addresses of said (n x m) storing circuits, reading the n signals of m channels, multiplexing the n siqnals of m channels, and outputting the multiplexed signals to an output port.
2. The cross-connecting apparatus as set forth in claim 1, wherein said multi-port TSW is composed of a multi-port RAM.
3. The cross-connecting apparatus as set forth in claim 2, wherein said multi-port RAM is composed of a custom LSI.
4. The cross-connecting apparatus as set forth in claim 1, wherein the m signals of n channels received from said (n x m) storing circuits in said multi-port TSW are input to each of said m selecting circuits and output as m selection signals of n channels corresponding to a command received from an operation panel.
5. A cross-connecting apparatus for cross-connecting signals of many channels (a channels), comprising:
m multiplexing circuits for converting a signal of a channels into m signals of n channels;
a multi-port TSW (time switch) having:
m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting circuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an output port; and m demultiplexing circuits for demultiplexing the multiplexed signals of n channels received from the output port of said multi-port TSW to signals of a channels.
m multiplexing circuits for converting a signal of a channels into m signals of n channels;
a multi-port TSW (time switch) having:
m separating circuits for separating a multiplexed signal of n channels to n parallel signals, (n x m) storing circuits for storing n signals of m channels received from the m separating circuits, and m selecting circuits for selecting the n signals of m channels stored in the (n x m) storing circuits on time division basis corresponding to read addresses of the (n x m) storing circuits, reading the n signals of m channels, multiplexing the n signals of m channels, and outputting the multiplexed signals to an output port; and m demultiplexing circuits for demultiplexing the multiplexed signals of n channels received from the output port of said multi-port TSW to signals of a channels.
6. The cross-connecting apparatus as set forth in claim 5, wherein said multi-port TSW is composed of a multi-port RAM.
7. The cross-connecting apparatus as set forth in claim 6, wherein said multi-port RAM is composed of a custom LSI.
8. The cross-connecting apparatus as set forth in claim 5, wherein the m signals of n channels received from said (n x m) storing circuits in said multi-port TSW are input to each of said m selecting circuits and output as m selection signals of n channels corresponding to a command received from an operation panel.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP121503/1997 | 1997-04-25 | ||
| JP12150397A JPH10304408A (en) | 1997-04-25 | 1997-04-25 | Cross-connect device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2235440A1 true CA2235440A1 (en) | 1998-10-25 |
Family
ID=14812810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2235440 Abandoned CA2235440A1 (en) | 1997-04-25 | 1998-04-21 | Cross-connecting apparatus |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH10304408A (en) |
| CA (1) | CA2235440A1 (en) |
| DE (1) | DE19818500A1 (en) |
| FR (1) | FR2762745A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU756112B2 (en) * | 1998-12-14 | 2003-01-02 | Lucent Technologies Inc. | Multi-port RAM based cross-connect system |
-
1997
- 1997-04-25 JP JP12150397A patent/JPH10304408A/en active Pending
-
1998
- 1998-04-21 CA CA 2235440 patent/CA2235440A1/en not_active Abandoned
- 1998-04-24 DE DE1998118500 patent/DE19818500A1/en not_active Ceased
- 1998-04-24 FR FR9805185A patent/FR2762745A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU756112B2 (en) * | 1998-12-14 | 2003-01-02 | Lucent Technologies Inc. | Multi-port RAM based cross-connect system |
| US6650637B1 (en) | 1998-12-14 | 2003-11-18 | Lucent Technologies Inc. | Multi-port RAM based cross-connect system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10304408A (en) | 1998-11-13 |
| FR2762745A1 (en) | 1998-10-30 |
| DE19818500A1 (en) | 1999-01-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |