CA2199902A1 - Interface circuit and method for transmitting binary logic signals with reduced power dissipation - Google Patents

Interface circuit and method for transmitting binary logic signals with reduced power dissipation

Info

Publication number
CA2199902A1
CA2199902A1 CA002199902A CA2199902A CA2199902A1 CA 2199902 A1 CA2199902 A1 CA 2199902A1 CA 002199902 A CA002199902 A CA 002199902A CA 2199902 A CA2199902 A CA 2199902A CA 2199902 A1 CA2199902 A1 CA 2199902A1
Authority
CA
Canada
Prior art keywords
potential
pulse
binary logic
interface circuit
power dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002199902A
Other languages
French (fr)
Other versions
CA2199902C (en
Inventor
Takashi Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of CA2199902A1 publication Critical patent/CA2199902A1/en
Application granted granted Critical
Publication of CA2199902C publication Critical patent/CA2199902C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/029—Provision of high-impedance states
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching

Abstract

An interface circuit transmits a binary logic signal by transmitting a pulse at a first potential at each falling transition of the binary logic signal, and a pulse at a second potential at each rising transition of the binary logic signal. At other times, the output terminal of the driver circuit is placed in the high-impedance state. The receiver circuit outputs a first logic level upon receiving a pulse at the first potential, and outputs a second logic level upon receiving a pulse at the second potential.
Output of these logic levels is maintained until the next pulse is received. The transmission line is preferably terminated at a potential intermediate between the first and second potentials.
CA002199902A 1996-09-19 1997-03-13 Interface circuit and method for transmitting binary logic signals with reduced power dissipation Expired - Fee Related CA2199902C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP247320/96 1996-09-19
JP24732096A JP3487723B2 (en) 1996-09-19 1996-09-19 Interface circuit and signal transmission method

Publications (2)

Publication Number Publication Date
CA2199902A1 true CA2199902A1 (en) 1998-03-19
CA2199902C CA2199902C (en) 2002-11-12

Family

ID=17161650

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002199902A Expired - Fee Related CA2199902C (en) 1996-09-19 1997-03-13 Interface circuit and method for transmitting binary logic signals with reduced power dissipation

Country Status (8)

Country Link
US (1) US5936429A (en)
JP (1) JP3487723B2 (en)
KR (1) KR100356074B1 (en)
CN (1) CN1094613C (en)
CA (1) CA2199902C (en)
DE (1) DE19712840B4 (en)
GB (1) GB2317515B (en)
TW (1) TW316959B (en)

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TW381385B (en) * 1997-08-20 2000-02-01 Advantest Corp Signal transmission circuit, CMOS semiconductor device and circuit board
DE19882882B4 (en) * 1997-12-08 2008-05-29 SRMOS, Inc., Seattle Method and circuit for the detection of a state of a primary switch in isolated DC-DC converters
US6064226A (en) * 1998-03-17 2000-05-16 Vanguard International Semiconductor Corporation Multiple input/output level interface input receiver
JP3246443B2 (en) * 1998-05-28 2002-01-15 日本電気株式会社 Synchronous buffer circuit and data transmission circuit using the same
US6127849A (en) * 1998-08-11 2000-10-03 Texas Instruments Incorporated Simultaneous bi-directional input/output (I/O) circuit
US6184717B1 (en) * 1998-12-09 2001-02-06 Nortel Networks Limited Digital signal transmitter and receiver using source based reference logic levels
US6438636B2 (en) 1998-12-23 2002-08-20 Intel Corporation Updating termination for a bus
US6351136B1 (en) * 1999-12-08 2002-02-26 Intel Corporation Passive voltage limiter
US6369605B1 (en) * 2000-09-18 2002-04-09 Intel Corporation Self-terminated driver to prevent signal reflections of transmissions between electronic devices
DE10103052C1 (en) * 2001-01-24 2002-09-12 Infineon Technologies Ag Circuit for generating an asynchronous signal pulse
US6711717B2 (en) * 2001-10-11 2004-03-23 California Institute Of Technology Method and system for compiling circuit designs
JP2004254155A (en) * 2003-02-21 2004-09-09 Kanji Otsuka Signal transmitter and wiring structure
US7113001B2 (en) * 2003-12-08 2006-09-26 Infineon Technologies Ag Chip to chip interface
US7668244B2 (en) * 2005-06-29 2010-02-23 Apple Inc. Method and apparatus for increasing data transfer rates through a communication channel
US7567094B2 (en) * 2006-06-14 2009-07-28 Lightwire Inc. Tri-stated driver for bandwidth-limited load
US7692565B2 (en) * 2007-04-18 2010-04-06 Qualcomm Incorporated Systems and methods for performing off-chip data communications at a high data rate
JP2011146101A (en) * 2010-01-15 2011-07-28 Elpida Memory Inc Semiconductor device, data transmission system, and method of controlling semiconductor device
US9071243B2 (en) * 2011-06-30 2015-06-30 Silicon Image, Inc. Single ended configurable multi-mode driver
US20130076424A1 (en) 2011-09-23 2013-03-28 Qualcomm Incorporated System and method for reducing cross coupling effects
US9124266B1 (en) * 2012-08-31 2015-09-01 Marvell Israel (M.I.S.L) Ltd. Increasing switching speed of logic circuits
US8648640B1 (en) * 2012-10-22 2014-02-11 Realtek Semiconductor Corp. Method and apparatus for clock transmission
DE102013100551A1 (en) * 2013-01-21 2014-07-24 Hella Kgaa Hueck & Co. Method for reducing linear distortion in a power interface for a motor vehicle
CN105306100B (en) * 2014-07-22 2017-10-20 财团法人成大研究发展基金会 Double binary voltages mode transmitters
CN105891651B (en) * 2015-01-16 2019-12-10 恩智浦美国有限公司 Low power open circuit detection system
US10177147B2 (en) 2015-05-15 2019-01-08 Mediatek Inc. Semiconductor device and structure
US10215589B2 (en) * 2015-08-12 2019-02-26 Infineon Technologies Ag IO matching current modulated output for sensors
US10861848B2 (en) * 2018-08-23 2020-12-08 Xilinx, Inc. Single event latch-up (SEL) mitigation techniques
CN111427820B (en) * 2019-01-10 2021-06-08 中芯国际集成电路制造(北京)有限公司 IO circuit and access control signal generation circuit for IO circuit
CN110677021B (en) * 2019-09-23 2021-01-08 北京时代民芯科技有限公司 Output drive circuit of anti ground bounce noise
US11264989B1 (en) 2020-08-07 2022-03-01 Kabushiki Kaisha Toshiba Semiconductor device

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US3479597A (en) * 1964-12-17 1969-11-18 Xerox Corp Dicode decoder
US4027152A (en) * 1975-11-28 1977-05-31 Hewlett-Packard Company Apparatus and method for transmitting binary-coded information
US4585958A (en) * 1983-12-30 1986-04-29 At&T Bell Laboratories IC chip with noise suppression circuit
JPS6220362A (en) * 1985-07-19 1987-01-28 Hitachi Ltd Signal transmission circuit for laminated electric circuit
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US5023488A (en) * 1990-03-30 1991-06-11 Xerox Corporation Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines
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JPH06104936A (en) * 1992-09-18 1994-04-15 Hitachi Ltd Method and circuit for signal transmission
US5384808A (en) * 1992-12-31 1995-01-24 Apple Computer, Inc. Method and apparatus for transmitting NRZ data signals across an isolation barrier disposed in an interface between adjacent devices on a bus
JPH07221624A (en) * 1994-02-04 1995-08-18 Hitachi Ltd Input/output interface circuit device
JPH09238095A (en) * 1995-12-25 1997-09-09 Hitachi Ltd Simultaneous two-way transmission circuit

Also Published As

Publication number Publication date
GB2317515B (en) 2000-07-19
US5936429A (en) 1999-08-10
KR19980024058A (en) 1998-07-06
JPH1093414A (en) 1998-04-10
DE19712840B4 (en) 2005-03-03
CA2199902C (en) 2002-11-12
JP3487723B2 (en) 2004-01-19
GB2317515A (en) 1998-03-25
DE19712840A1 (en) 1998-03-26
KR100356074B1 (en) 2003-03-15
CN1094613C (en) 2002-11-20
CN1178945A (en) 1998-04-15
GB9705360D0 (en) 1997-04-30
TW316959B (en) 1997-10-01

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