CA2194026A1 - Methode et appareil de transfert de paquets de donnees entre des reseaux utilisant une architecture multibus qui minimise les interventions de l'unite centrale - Google Patents
Methode et appareil de transfert de paquets de donnees entre des reseaux utilisant une architecture multibus qui minimise les interventions de l'unite centraleInfo
- Publication number
- CA2194026A1 CA2194026A1 CA002194026A CA2194026A CA2194026A1 CA 2194026 A1 CA2194026 A1 CA 2194026A1 CA 002194026 A CA002194026 A CA 002194026A CA 2194026 A CA2194026 A CA 2194026A CA 2194026 A1 CA2194026 A1 CA 2194026A1
- Authority
- CA
- Canada
- Prior art keywords
- interventions
- networks
- data packets
- cpu
- bus architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Multi Processors (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002194026A CA2194026C (fr) | 1996-12-24 | 1996-12-24 | Methode et appareil de transfert de paquets de donnees entre des reseaux utilisant une architecture multibus qui minimise les interventions de l'unite centrale |
US08/995,660 US6061748A (en) | 1996-12-24 | 1997-12-22 | Method and apparatus for moving data packets between networks while minimizing CPU intervention using a multi-bus architecture having DMA bus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002194026A CA2194026C (fr) | 1996-12-24 | 1996-12-24 | Methode et appareil de transfert de paquets de donnees entre des reseaux utilisant une architecture multibus qui minimise les interventions de l'unite centrale |
US08/995,660 US6061748A (en) | 1996-12-24 | 1997-12-22 | Method and apparatus for moving data packets between networks while minimizing CPU intervention using a multi-bus architecture having DMA bus |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2194026A1 true CA2194026A1 (fr) | 1998-06-24 |
CA2194026C CA2194026C (fr) | 2001-05-01 |
Family
ID=25678951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002194026A Expired - Fee Related CA2194026C (fr) | 1996-12-24 | 1996-12-24 | Methode et appareil de transfert de paquets de donnees entre des reseaux utilisant une architecture multibus qui minimise les interventions de l'unite centrale |
Country Status (2)
Country | Link |
---|---|
US (1) | US6061748A (fr) |
CA (1) | CA2194026C (fr) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6449656B1 (en) * | 1999-07-30 | 2002-09-10 | Intel Corporation | Storing a frame header |
US7058728B1 (en) * | 1999-10-29 | 2006-06-06 | Nokia Corporation | Method and apparatus for initiating compression of headers of packets and refreshing the context related to the packets |
US6675200B1 (en) * | 2000-05-10 | 2004-01-06 | Cisco Technology, Inc. | Protocol-independent support of remote DMA |
US6636939B1 (en) * | 2000-06-29 | 2003-10-21 | Intel Corporation | Method and apparatus for processor bypass path to system memory |
US6658520B1 (en) * | 2000-09-26 | 2003-12-02 | Intel Corporation | Method and system for keeping two independent busses coherent following a direct memory access |
KR100387704B1 (ko) * | 2001-05-15 | 2003-06-18 | 엘지전자 주식회사 | 메모리 버스를 이용한 네트워크 인터페이스 장치 |
GB2377139A (en) * | 2001-06-29 | 2002-12-31 | Zarlink Semiconductor Ltd | Network gateway utilising DMA controller to transfer data between buffers |
US6829660B2 (en) * | 2001-12-12 | 2004-12-07 | Emulex Design & Manufacturing Corporation | Supercharge message exchanger |
US7093038B2 (en) * | 2002-05-06 | 2006-08-15 | Ivivity, Inc. | Application program interface-access to hardware services for storage management applications |
US7389364B2 (en) * | 2003-07-22 | 2008-06-17 | Micron Technology, Inc. | Apparatus and method for direct memory access in a hub-based memory system |
JP2007299237A (ja) * | 2006-04-28 | 2007-11-15 | Toshiba Corp | 情報転送装置及び情報転送方法 |
DE102016203307A1 (de) * | 2016-03-01 | 2017-09-07 | Robert Bosch Gmbh | Speicherdirektzugriffssteuereinrichtung für eine einen Arbeitsspeicher aufweisende Recheneinheit |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5410652A (en) * | 1990-09-28 | 1995-04-25 | Texas Instruments, Incorporated | Data communication control by arbitrating for a data transfer control token with facilities for halting a data transfer by maintaining possession of the token |
US5655151A (en) * | 1994-01-28 | 1997-08-05 | Apple Computer, Inc. | DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer |
US5907864A (en) * | 1995-06-07 | 1999-05-25 | Texas Instruments Incorporated | Data processing device with time-multiplexed memory bus |
US5623494A (en) * | 1995-06-07 | 1997-04-22 | Lsi Logic Corporation | Asynchronous transfer mode (ATM) interconnection system for multiple hosts including advanced programmable interrupt controller (APIC) |
US5745684A (en) * | 1995-11-06 | 1998-04-28 | Sun Microsystems, Inc. | Apparatus and method for providing a generic interface between a host system and an asynchronous transfer mode core functional block |
US5889480A (en) * | 1996-10-18 | 1999-03-30 | Samsung Electronics Co., Ltd. | Full duplex serial codec interface with DMA |
-
1996
- 1996-12-24 CA CA002194026A patent/CA2194026C/fr not_active Expired - Fee Related
-
1997
- 1997-12-22 US US08/995,660 patent/US6061748A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2194026C (fr) | 2001-05-01 |
US6061748A (en) | 2000-05-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |