CA2173225A1 - Virtual address translation hardware assist circuit and method - Google Patents

Virtual address translation hardware assist circuit and method

Info

Publication number
CA2173225A1
CA2173225A1 CA002173225A CA2173225A CA2173225A1 CA 2173225 A1 CA2173225 A1 CA 2173225A1 CA 002173225 A CA002173225 A CA 002173225A CA 2173225 A CA2173225 A CA 2173225A CA 2173225 A1 CA2173225 A1 CA 2173225A1
Authority
CA
Canada
Prior art keywords
content
address
register
ste
zte
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002173225A
Other languages
French (fr)
Other versions
CA2173225C (en
Inventor
Stephen W. Olson
James B. Macdonald
Richard W. Lones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Stephen W. Olson
James B. Macdonald
Richard W. Lones
Wang Laboratories, Inc.
Lg Semicon Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/135,037 external-priority patent/US5479628A/en
Application filed by Stephen W. Olson, James B. Macdonald, Richard W. Lones, Wang Laboratories, Inc., Lg Semicon Co., Ltd. filed Critical Stephen W. Olson
Publication of CA2173225A1 publication Critical patent/CA2173225A1/en
Application granted granted Critical
Publication of CA2173225C publication Critical patent/CA2173225C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Abstract

A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining the content of the first register with a content of the ZTE, while simultaneoysly testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining the content of the first register with a content of the STE, while simultaneously testing the STE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the PTE with the formed address and selectively combines the content of the STE with the content of the PTE and outputs the combination as a translation buffer entry, while simultaneously testing the PTE for a Page fault.
CA002173225A 1993-10-12 1994-03-24 Virtual address translation hardware assist circuit and method Expired - Fee Related CA2173225C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US135,037 1993-10-12
US08/135,037 US5479628A (en) 1993-10-12 1993-10-12 Virtual address translation hardware assist circuit and method
PCT/US1994/003241 WO1995010808A1 (en) 1993-10-12 1994-03-24 Virtual address translation hardware assist circuit and method

Publications (2)

Publication Number Publication Date
CA2173225A1 true CA2173225A1 (en) 1995-04-20
CA2173225C CA2173225C (en) 2006-07-18

Family

ID=36694010

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002173225A Expired - Fee Related CA2173225C (en) 1993-10-12 1994-03-24 Virtual address translation hardware assist circuit and method

Country Status (1)

Country Link
CA (1) CA2173225C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178759B (en) * 2006-11-09 2010-04-21 国际商业机器公司 Trusted device integrate circuit and virtualization method for memory device in the same
CN112596790A (en) * 2020-12-10 2021-04-02 海光信息技术股份有限公司 Method and device for executing access micro instruction

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178759B (en) * 2006-11-09 2010-04-21 国际商业机器公司 Trusted device integrate circuit and virtualization method for memory device in the same
CN112596790A (en) * 2020-12-10 2021-04-02 海光信息技术股份有限公司 Method and device for executing access micro instruction
CN112596790B (en) * 2020-12-10 2022-11-22 海光信息技术股份有限公司 Method and device for executing access micro instruction

Also Published As

Publication number Publication date
CA2173225C (en) 2006-07-18

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