CA2158784A1 - Electronic thick film component termination and method of making the same - Google Patents
Electronic thick film component termination and method of making the sameInfo
- Publication number
- CA2158784A1 CA2158784A1 CA 2158784 CA2158784A CA2158784A1 CA 2158784 A1 CA2158784 A1 CA 2158784A1 CA 2158784 CA2158784 CA 2158784 CA 2158784 A CA2158784 A CA 2158784A CA 2158784 A1 CA2158784 A1 CA 2158784A1
- Authority
- CA
- Canada
- Prior art keywords
- laminated
- subassemblies
- sheet
- ferrite
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004020 conductor Substances 0.000 claims abstract description 95
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 91
- 238000005520 cutting process Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 description 12
- 239000000945 filler Substances 0.000 description 8
- 229920002799 BoPET Polymers 0.000 description 6
- 239000005041 Mylar™ Substances 0.000 description 6
- 239000011231 conductive filler Substances 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 238000010304 firing Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000004372 Polyvinyl alcohol Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229920002451 polyvinyl alcohol Polymers 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 241000518994 Conta Species 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
- H01F41/046—Printed circuit coils structurally combined with ferromagnetic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Coils Or Transformers For Communication (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
Abstract
A monolithic multilayer chip component (10) comprises a plurality of subassemblies (20, 30, 44, 58) stacked one above the other. At least one of the subassemblies includes a ferrite layer (22) having a conductor (24) printed on its surface. One end (26) of the conductor is exposed adjacent the edge (14) of the chip so that the conductor (24) can be connected to a terminal. A plurality of the chip components are manufactured at the same time by arranging the components on single sheets. The layers including the conductors are arranged such that the ends of the conductor that are adjacent the end of the chip, are adjacent to each other so that when the chips are separated the conductors are cut along with the chip.
Description
21587g4 -TITLE: ELECTRONIC THICK FILM COMPONENT TERMINATION AND
METHOD OF MAKING TH~ SAME
R"''}~.ROUND OF T~IE INVENTION
The present invention relates to a method of connecting the inner conductors and the outer terminals of monolithic chip inductors, transformers, and all other electronic thick film components.
Monolithic multilayer chip components exist in the prior art, but there is a need for such components which can be easily manufactured in large quantities, and which provide an improved reliability in operation.
Therefore, a primary object of the present invention is the provision of an improved monolithic multilayer chip component and method for making the same.
A further object of the present invention i5 the provision of an improved monolithic multilayer chip component having a plurality of conductor layers stacked above one another and sandwiched between ferrite layers, and having end cap terminals at opposite edges thereof.
A further object of the present invention is the provision of an improved monolithic multilayer chip component which can be manufactured in large quantities as a single sheet of material, later to be cut apart into individual components.
A further object of the present invention is the provision of an improved monolithic multilayer chip component and method for making the same which is simple in construction, easy to manufacture, and efficient and reliable in operation.
A further object of the present invention is the provision of an improved monolithic multilayer chip component and method of making the same which eliminates extra silver, reduces capacitance, reduces eddy currents, reduces deliminations between layers, increases the self-resonant frequency, and increases the maximum allowable variation of the cut position when cutting individual parts from wafers.
SU~QIARY OF THE INVENTION
A monolithic multilayer chip component of the present invention could be an inductor, transformer, or any other electronic thick film component. A preferred embodiment of the present invention, a chip inductor, will hereinafter be described. It is not intended that the present invention be limited to the preferred embodiment, on the contrary, it is meant to include all other embodiments within the scope and spirit of the present invention.
The monolithic multilayer chip inductor of the present invention includes a plurality of subassemblies stacked upon one another. At the bottom is a bottom subassembly including a bottom ferrite layer and a bottom coil inductor printed on the bottom ferrite layer. The bottom coil conductor includes a first end adjacent the front edge of the bottom ferrite layer and a gecond end located spaced inwardly from the first edge of the bottom ferrite layer. Additional subassemblies may be printed above the bottom subassemblies. Each of these additional subassemblies includes a ferrite layer having a via opening extending therethrough and having a coil conductor printed on the top surface thereof. Each coil conductor includes a fir6t end registered with a via opening in the ferrite layer below it and a second end registered with a via opening in the ferrite layer above it.
The ends of the coils are interconnected through the via openings by means of conductors within the via openings. The preferred conductor is a silver filler material which is printed over each via opening in order to fill up the via opening and provide electrical connection between the two coils above and below the via opening.
A top subassembly is printed at the very top of the stack of subassemblies, and includes a top ferrite layer having a via opening extending therethrough and a top coil conductor above the top ferrite layer. The top coil 21587~4 conductor has a first end registered with the via opening and connected to the coil there below by means of a conductive filler within the via opening. The top coil also has a second end located adjacent one of the edges of the top subassembly and adjacent and above a second edge of the bottom ferrite layer of the bottom subassembly. This arrangement permits a pair of end caps or terminals to be provided over the inductor, with one of the end caps being in electrical contact with the first end of the bottom coil conductor and with the other of the terminals being in contact with the second end of the top coil conductor. A top cap ferrite layer is printed in covering relation over the top subassembly.
The present invention can be constructed in multiples by the method of the present invention. Initially, a sheet of material made of mylar or another material having a low coefficient of adhesion is covered with a ferrite bottom layer. Next, a plurality of first conductor coils are printed on top of the ferrite bottom layer. The conductor coils are printed on top of the ferrite bottom layer in such a way that one end of the conductor is adjacent to the edge of one side of the ferrite layer. These conductor ends will make contact with terminal end caps after construction of each inductor is complete. The plurality of conductor coils are arranged on the ferrite bottom layer in such a way that the ends of the conductors that are adjacent the ends of the ferrite layer are also adjacent to each other. In the next step, a second ferrite layer is printed over the first conductor coils and includes a plurality of via openings therein each registered with the output ends of a first coil conductor. These via openings are then filled with a silver filler, and a group of second conductor coils are printed over the second ferrite layer, with one end of each of the second conductor coil being located in registered alignment with one of the via openings in the second ferrite layer.
Additional groups of subassemblies are printed over one another in the same fashion as described above until a top 21~878~
set of coil conductors are printed over a top ferrite layer.
The top set of coil conductors have one end that is adjacent to one edge of the top ferrite layer. Like the conductor coils on the ferrite bottom layer, the top set of coil conductors are arranged on the top ferrite layer such that the conductor ends adjacent to the ferrite edges are also adjacent to each other. Finally, a ferrite top cap iB
printed over all of the top coil conductors. A separate screen ContAi ni ng cutting lines is printed on the ferrite top cap with a marking ink.
The entire assembly is then peeled off the mylar material and cut into individual parts using a razor blade.
The parts are separated and placed on an alumina carrier for sintering. No two pieces should be touching each other during firing. Sintering occurs at approximately 900 centigrade in a furnace for approximately two hours with careful attention being given to the burn out of the organic binders within the component so as to prevent blisters and cracks. Following the firing process, the assembly or wafer is removed from the alumina carrier.
After completion of cutting the assembly into individual inductor assemblies or wafers and firing, the bottom termination of the bottom coil conductor and the top termination of the top coil conductor are the only two conductor features exposed at the edges of the completed inductor assembly. All of the rest of the conductor coils are completely encased within the laminations of ferrite.
Furthermore, the coils are centered with respect to the ferrite layers as viewed in plan view.
Since the conductor coils are arranged such that the ends that are adjacent the edges of the ferrite layers are all adjacent to each other, the cut passes between the two conductor ends. In prior art methods, when the wafers were cut, some of the conductor material was left behind on the part adjacent to the one cut. This left over material created potential shorting problems as well as added capacitance and lowered the self-resonant frequency. Also, with the present invention, the cutting tolerance area is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade.
Terminations are then attached to different edges of the completed inductor (preferably opposite edges), with one of the terminations in electrical contact with the output end of the top coil conductor and with the other of the terminations in electrical contact with the input end of the bottom coil conductor.
BRIEF D -~PTPTION OF THE DRAWINGS
Figure 1 is an exploded perspective view of the inductor of the monolithic multilayer chip inductor of the present invention.
Figure 2 is a perspective view of the assembled monolithic multilayer chip inductor showing the terminations in exploded view.
Figure 3 is a side elevation view taken along line 3-3 of Figure 2.
Figures 4-15 are views showing the various printing stages of the process for making the present invention.
Figure 16 shows an enlarged view of Figure 14.
Figure 17 shows an enlarged view along line 18-18 of Figure 16 of the layout for the conductive layers as arranged in the prior art.
Figure 18 shows an enlarged view along line 18-18 of Figure 16 of the layout of the conductive layers in the preferred embodiment of the present invention.
DE~TT~n DESCRIPTION OF THE ~r~Kk~ EHBODIMENT
The preferred embodiment of the present invention will be described as it applies to a chip inductor. It is not intended that the present invention be limited to the described embodiment. On the contrary, it is intended that the invention cover all alternatives, modifications and 21587~4 equivalences which may be included within the spirit and scope of the invention.
Referring to the drawings, the numeral 10 generally designates the monolithic multilayer chip inductor of the present invention. Inductor 10 comprises a plurality of subassemblies stacked upon one another. A bottom subassembly 20 includes a ferrite bottom layer 22 and a bottom coil conductor 24 printed over ferrite layer 22 and having an outer end 26 and an inner end 28. Bottom ferrite layer 22 includes a front edge 14, a rear edge 16, and a pair of opposite side edges 18. End 26 of the coil conductor 24 is positioned flush with the front edge 14 of bottom ferrite layer 22. This causes the outer end 26 of coil conductor 24 to be exposed when the assembly 10 is cut apart. The remainder of bottom coil 24 is located inwardly from the opposite edges 18 and the rear edge 16 of bottom ferrite layer 22.
Printed over the bottom subassembly 20 is a first intermediate subassembly 30. Subassembly 30 includes a first intermediate ferrite layer 32 having a via hole 34 ext~ing therethrough. Via hole 34 is registered immediately above the inner end 28 of bottom conductor coil 24.
Printed over the upper surface of first intermediate ferrite layer 32 is a first intermediate coil conductor 36 having an inner end 38 registered over via hole 34 and having an outer end 40. Outer end 40 is spaced inwardly from the front edge 14 of subassembly 20 in contrast to the outer end 26 of bottom coil conductor 24.
Each ferrite layer in the present invention is preferably printed in several multiple prints until the total dry thicknesæ of each ferrite layer is approximately 25 microns thick. Other thicknesses may be used without detracting from the invention. However, the thickness of each ferrite layer requires that the via hole 34 be filled with a conductive filler 42 which provides electrical connection between the inner end 38 of first intermediate coil 36 and the inner end 28 of bottom coil 24.
~, .
Printed above first intermediate subassembly 30 is a second intermediate subassembly 44 having a second ferrite layer 46 formed with a via hole 48, and having a second intermediate coil conductor 50 printed on the second intermediate ferrite layer 46. Second intermediate coil conductor 50 has an outer end 52 registered above via hole 48. Via hole 48 is filled with a conductive filler 56, and is registered above the outer coil end 40 of first intermediate coil 36. Thus, the filler 56 provides electrical connection between the outer coil end 40 of first intermediate coil 36 and the outer coil end 52 of second intermediate coil 50. Second intermediate coil 50 also includes an inner end 54. The entire second intermediate coil 50 is positioned inwardly from the parametric edges of second intermediate ferrite layer 46.
Printed above second intermediate subassembly 44 is a top subassembly 58 which comprises a top ferrite layer 60 having a via hole 62 extending therethrough and a top coil conductor 64 printed over the upper surface of top ferrite layer 60. Top coil conductor 64 includes a top inner coil end 66 which is registered above the via hole 62 and includes a top outer coil end 68 which extends flush with the rear parametric edge of top ferrite layer 60 and which is also registered above the rear edge 16 of bottom ferrite layer 22.
A conductive filler 69 is within via hole 62 and provides electrical connection between the top inner coil end 66 and the inner coil end 54 of second intermediate coil conductor 50.
A ferrite top cap layer 70 is printed over the top subassembly 58 and covers the top subassembly 58. However, the outer coil end 68 of top conductive coil 64 is exposed between the edges of top ferrite layer 60 and the top cap 70.
When the assembly is completed, a continuous electrical path is provided commencing with the outer end 26 of bottom coil conductor 24 and passing through the inner end 28 thereof, through first filler 42 to the inner coil end 38 of first intermediate coil conductor 36. The electrical path ~ 21S8784 continues to outer coil end 40 through second filler 56, outer coil end 52, inner coil end 54, third filler 69, inner coil end 66, and outer coil end 68. It should be noted that the electrical path continues in the same rotational direction (clockwise as shown in Figure 1) from the bottom coil conductor 24 upwardly through the top coil conductor 64.
Any desired number of intermediate coil subassemblies 30, 44 may be printed, or the inductor can be made with only the top subassembly 58 and the bottom subassembly 20, depending upon the particular values of inductance which are required.
Referring to Figure 2, a pair of end terminals 72, 74 are mounted or printed over the front and rear edges of 14, 16 of assembly 10. Terminals 72, 74 can be metallic end caps, or they can be printed conductive material which is printed over the front and rear edges of the inductor 10.
Terminal 72 is in electrical contact with the outer end 68 of top coil conductor 64, and terminal 74 is in electrical contact with the outer end 26 of bottom coil conductor 24.
While the resulting monolithic multilayer chip inductor 10 is shown in Figure 1-3, a method for producing a plurality of inductors 10 is shown in Figures 4-18. In these figures, numerals are used which correspond to the numerals used for similar parts in Figures 1-3. Referring to Figure 4, using a suitable adhesive for microelectronics, a thick mylar sheet of material, 2 inches by 2 inches by 0.010 inches thick (not shown) is attached to the upper surface of a soda lime glass substrate (not shown). Other than mylar, polyethylene, plastic, or any other material having a low coefficient of adhesion may be used. The top surface of this mylar substrate is painted with polyvinyl alcohol or the like, as a release agent. The polyvinyl alcohol is permitted to dry.
The ferrite base or bottom cap 22 shown in Figure 4 is then printed over the polyvinyl alcohol.
After the ferrite bottom cap 22 is printed, a plurality of conductor coils 24 (Figure 5) are printed over bottom cap 22. The outer ends 26 of coils 24 are wider than the remainder of the coils 24, and the plurality of printed coils ~ 21587~4 24 are centered over bottom cap 22. Figures 16, 17 and 18 show a close up view of the plurality of conductor coils 64 of the top ferrite layer as shown in Figure 14. The arrangement of the bottom conductor coils 24 are arranged in a way analogous to the arrangement of the top conductor coils 64 which will be discussed in detail below. Figure 17 shows the conductor coil layout of the prior art. The dotted lines in Figure 17 and 18 show where the ferrite layer with conductor coils will be cut. It can be seen that after the layers are cut, in the prior art a small portion of the conductive coils 24 are left on the adjacent part near the rear edge 14 of assembly 10. This leftover conductive material creates potential shorting problems as well as adding capacitance, and lowers the self-resonant frequency of the device. These problems are solved in the present invention by rotating alternating parts 10 within a column by 180. This is illustrated by analogy in Figures 16 and 18.
The region of the element 10 that makes connection to the outside terminal 74 or 72 is connected to the same region of the element located either directly above or below the part.
In other words, pairs of parts 10 in a column are electrically shorted together until the cutting process separates them. Another advantage of this is that the cutting area tolerance is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade. Also, a pair of silver crosses 75 are printed over ferrite layer 22.
Following the printing of the coils 24, a first intermediate ferrite layer 32 is printed over the coils 24 and includes a plurality of via holes 34 which are in registered alignment over the inner ends 28 of coils 24.
Crosses 75 are aligned with the pair of open cross windows 76 in first intermediate ferrite layer 32 so as to permit proper registration of layer 32 with respect to coils 24.
Next, a plurality of first fillers 42 are printed over the ferrite layer 32 and are in registered alignment with and fit within the via holes 34 so as to completely fill them.
215~784 Crosses 78 are printed over crosses 75 which are registered with cross windows 76.
Next, a plurality of first intermediate coil conductors 36 are printed over first intermediate ferrite layer 32 and are properly aligned so that the inner ends 38 fit over via openings 34 and are in electrical contact with first fillers 42. At the same time four crosses 79 are printed on the four corners of ferrite layer 32.
Additional intermediate suba~semblies may be assembled as desired, and Figures 9-11 illustrate a second intermediate subassembly 44. A second intermediate ferrite layer 46 (Figure 9~ is printed over subassembly 30 and includes via holes 48, and cross windows 82 registered over crosseæ 79.
In Figure 10 conductive fillers 56 are printed over via openings 48 and crosses 84 are printed over windows 82. In Figure 11 coil conductors 50 and four crosses 86 are printed over ferrite layer 46.
The final subassembly or top subassembly 58 is shown in Figures 12 through 14 and includes the top ferrite layer 60 having via holes 62 therein. The ferrite layer 60 is provided with cross windows 83 which are aligned with two of the crosses 86. In Figure 13 conductive fillers 69 and crosses 85 are printed over ferrite layer 60. In Figure 14 conductive coils 64 and four crosses 88 are added. The top coil conductors 64 have outer ends 68 which are of enlarged width and which are positioned adjacent the rear edges of the individual inductors 10 to be formed. Coil conductors 64 also have inner ends 66. The top coil conductors 64 are arranged in the same manner as the bottom coil conductors as discussed above. Figures 16, 17 and 18 show a close up view of the plurality of conductor coils 64 of the top ferrite layer as shown in Figure 14. Figure 17 shows the conductor coil layout of the prior art. The dotted lines in Figures 17 and 18 show where the ferrite layer with conductor coils will be cut. It can be seen that after the layers are cut, in the prior art a small portion 100 of the conductive coils 64 are left on the adjacent part near the rear edge of assembly 10.
This leftover conductive material creates potential shorting problems as well as adding capacitance, and lowers the self-resonant frequency of the device. These problems are solved in the present invention by rotating alternating parts 10 within a column by 180. This is illustrated in Figures 16 and 18. The region of the element 10 that makes connection to the outside terminal 74 or 72 is connected to the same region of the element located either directly above or below the part. In other words, pairs of parts 10 in a column are electrically shorted together until the cutting process separates them. Another advantage of this is that the cutting area tolerance is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade. The alignment of the various layers in Figures 5-14 is accomplished by means of cross windows 76, 82, 83 and aligning crosses 75, 78, 79, 84, 85, 86 and 88 respectively.
The final ferrite top cap 70 is shown in Figure 15.
Preferably, the top cap 70 is a solid sheet with no openings.
A separate screen contA;n;ng only cutting lines 92 is printed on the top cap with a marking ink.
Alternatively, as shown in Figure 14, a plurality of cutting lines 90 are printed around the periphery of the group of top coils 64 so as to permit the alignment of the final ferrite top cap 70 which has a plurality of cutting line windows in place of cutting lines 92. The windows are registered with the cutting lines 90 so as to provide proper registration of the top cap 70 with respect to the remainder of the assembly, and so as to expose the cutting lines 90 after the assembly is complete.
In the preferred method, after drying, the assembly i8 peeled off of the mylar substrate and sliced into individual parts with a razor blade. The blade is aligned with the cutting lines 92 so that the cuts occur between the thickened portions 68 of coils 64 and between the thickened ends 26 of bottom coils 24. This is the only portion of any of the coil conductors which is exposed by the diamond cuts through the ; 21~87~
assembly. All other portions of bottom and top coils 24, 64, and all of the intermediate coils 36, 50 are completely enclosed by the laminated ferrite layers. If properly aligned before the cutting process, each coil is centered with respect to a plan view of the resulting inductor 10.
The parts are then placed on an alumina substrate (not shown) for sintering. The sintering occurs at 900 centigrade in a box furnace for two hours with careful attention being given to the burnout of the organic binders and the prevention of blisters and cracks.
Alternatively, before cutting the assembly apart, the entire assembly can be fired. Following the firing process, the wafer is mounted onto a wafer holder and then is diced into individual chip inductors with a precision diamond blade dicing saw commonly used in the semiconductor IC industry.
After inspection of each of the individual coils 10, the end terminals 72, 74 are attached. These end terminals are preferably a multilayer structure including a silver termination, a nickel-plate end cap, and a tin lead plating over the end cap.
The present invention provides a simple, efficient, and reliable method of production of the monolithic multilayer chip inductors 10.
The preferred embodiment of the present invention has been set forth in the drawings and specification, and although specific terms are employed, these are used in a generic or descriptive sense only and are not used for purposes of limitation. Also, this invention applies to any other electronic thick film components requiring a connection between the inner conductors and the outer terminals of the component. Changes in the form and proportion of parts as well as in the substitution of equivalents are contemplated as circumstances may suggest or render expedient without departing from the spirit or scope of the invention as further defined in the following claims.
METHOD OF MAKING TH~ SAME
R"''}~.ROUND OF T~IE INVENTION
The present invention relates to a method of connecting the inner conductors and the outer terminals of monolithic chip inductors, transformers, and all other electronic thick film components.
Monolithic multilayer chip components exist in the prior art, but there is a need for such components which can be easily manufactured in large quantities, and which provide an improved reliability in operation.
Therefore, a primary object of the present invention is the provision of an improved monolithic multilayer chip component and method for making the same.
A further object of the present invention i5 the provision of an improved monolithic multilayer chip component having a plurality of conductor layers stacked above one another and sandwiched between ferrite layers, and having end cap terminals at opposite edges thereof.
A further object of the present invention is the provision of an improved monolithic multilayer chip component which can be manufactured in large quantities as a single sheet of material, later to be cut apart into individual components.
A further object of the present invention is the provision of an improved monolithic multilayer chip component and method for making the same which is simple in construction, easy to manufacture, and efficient and reliable in operation.
A further object of the present invention is the provision of an improved monolithic multilayer chip component and method of making the same which eliminates extra silver, reduces capacitance, reduces eddy currents, reduces deliminations between layers, increases the self-resonant frequency, and increases the maximum allowable variation of the cut position when cutting individual parts from wafers.
SU~QIARY OF THE INVENTION
A monolithic multilayer chip component of the present invention could be an inductor, transformer, or any other electronic thick film component. A preferred embodiment of the present invention, a chip inductor, will hereinafter be described. It is not intended that the present invention be limited to the preferred embodiment, on the contrary, it is meant to include all other embodiments within the scope and spirit of the present invention.
The monolithic multilayer chip inductor of the present invention includes a plurality of subassemblies stacked upon one another. At the bottom is a bottom subassembly including a bottom ferrite layer and a bottom coil inductor printed on the bottom ferrite layer. The bottom coil conductor includes a first end adjacent the front edge of the bottom ferrite layer and a gecond end located spaced inwardly from the first edge of the bottom ferrite layer. Additional subassemblies may be printed above the bottom subassemblies. Each of these additional subassemblies includes a ferrite layer having a via opening extending therethrough and having a coil conductor printed on the top surface thereof. Each coil conductor includes a fir6t end registered with a via opening in the ferrite layer below it and a second end registered with a via opening in the ferrite layer above it.
The ends of the coils are interconnected through the via openings by means of conductors within the via openings. The preferred conductor is a silver filler material which is printed over each via opening in order to fill up the via opening and provide electrical connection between the two coils above and below the via opening.
A top subassembly is printed at the very top of the stack of subassemblies, and includes a top ferrite layer having a via opening extending therethrough and a top coil conductor above the top ferrite layer. The top coil 21587~4 conductor has a first end registered with the via opening and connected to the coil there below by means of a conductive filler within the via opening. The top coil also has a second end located adjacent one of the edges of the top subassembly and adjacent and above a second edge of the bottom ferrite layer of the bottom subassembly. This arrangement permits a pair of end caps or terminals to be provided over the inductor, with one of the end caps being in electrical contact with the first end of the bottom coil conductor and with the other of the terminals being in contact with the second end of the top coil conductor. A top cap ferrite layer is printed in covering relation over the top subassembly.
The present invention can be constructed in multiples by the method of the present invention. Initially, a sheet of material made of mylar or another material having a low coefficient of adhesion is covered with a ferrite bottom layer. Next, a plurality of first conductor coils are printed on top of the ferrite bottom layer. The conductor coils are printed on top of the ferrite bottom layer in such a way that one end of the conductor is adjacent to the edge of one side of the ferrite layer. These conductor ends will make contact with terminal end caps after construction of each inductor is complete. The plurality of conductor coils are arranged on the ferrite bottom layer in such a way that the ends of the conductors that are adjacent the ends of the ferrite layer are also adjacent to each other. In the next step, a second ferrite layer is printed over the first conductor coils and includes a plurality of via openings therein each registered with the output ends of a first coil conductor. These via openings are then filled with a silver filler, and a group of second conductor coils are printed over the second ferrite layer, with one end of each of the second conductor coil being located in registered alignment with one of the via openings in the second ferrite layer.
Additional groups of subassemblies are printed over one another in the same fashion as described above until a top 21~878~
set of coil conductors are printed over a top ferrite layer.
The top set of coil conductors have one end that is adjacent to one edge of the top ferrite layer. Like the conductor coils on the ferrite bottom layer, the top set of coil conductors are arranged on the top ferrite layer such that the conductor ends adjacent to the ferrite edges are also adjacent to each other. Finally, a ferrite top cap iB
printed over all of the top coil conductors. A separate screen ContAi ni ng cutting lines is printed on the ferrite top cap with a marking ink.
The entire assembly is then peeled off the mylar material and cut into individual parts using a razor blade.
The parts are separated and placed on an alumina carrier for sintering. No two pieces should be touching each other during firing. Sintering occurs at approximately 900 centigrade in a furnace for approximately two hours with careful attention being given to the burn out of the organic binders within the component so as to prevent blisters and cracks. Following the firing process, the assembly or wafer is removed from the alumina carrier.
After completion of cutting the assembly into individual inductor assemblies or wafers and firing, the bottom termination of the bottom coil conductor and the top termination of the top coil conductor are the only two conductor features exposed at the edges of the completed inductor assembly. All of the rest of the conductor coils are completely encased within the laminations of ferrite.
Furthermore, the coils are centered with respect to the ferrite layers as viewed in plan view.
Since the conductor coils are arranged such that the ends that are adjacent the edges of the ferrite layers are all adjacent to each other, the cut passes between the two conductor ends. In prior art methods, when the wafers were cut, some of the conductor material was left behind on the part adjacent to the one cut. This left over material created potential shorting problems as well as added capacitance and lowered the self-resonant frequency. Also, with the present invention, the cutting tolerance area is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade.
Terminations are then attached to different edges of the completed inductor (preferably opposite edges), with one of the terminations in electrical contact with the output end of the top coil conductor and with the other of the terminations in electrical contact with the input end of the bottom coil conductor.
BRIEF D -~PTPTION OF THE DRAWINGS
Figure 1 is an exploded perspective view of the inductor of the monolithic multilayer chip inductor of the present invention.
Figure 2 is a perspective view of the assembled monolithic multilayer chip inductor showing the terminations in exploded view.
Figure 3 is a side elevation view taken along line 3-3 of Figure 2.
Figures 4-15 are views showing the various printing stages of the process for making the present invention.
Figure 16 shows an enlarged view of Figure 14.
Figure 17 shows an enlarged view along line 18-18 of Figure 16 of the layout for the conductive layers as arranged in the prior art.
Figure 18 shows an enlarged view along line 18-18 of Figure 16 of the layout of the conductive layers in the preferred embodiment of the present invention.
DE~TT~n DESCRIPTION OF THE ~r~Kk~ EHBODIMENT
The preferred embodiment of the present invention will be described as it applies to a chip inductor. It is not intended that the present invention be limited to the described embodiment. On the contrary, it is intended that the invention cover all alternatives, modifications and 21587~4 equivalences which may be included within the spirit and scope of the invention.
Referring to the drawings, the numeral 10 generally designates the monolithic multilayer chip inductor of the present invention. Inductor 10 comprises a plurality of subassemblies stacked upon one another. A bottom subassembly 20 includes a ferrite bottom layer 22 and a bottom coil conductor 24 printed over ferrite layer 22 and having an outer end 26 and an inner end 28. Bottom ferrite layer 22 includes a front edge 14, a rear edge 16, and a pair of opposite side edges 18. End 26 of the coil conductor 24 is positioned flush with the front edge 14 of bottom ferrite layer 22. This causes the outer end 26 of coil conductor 24 to be exposed when the assembly 10 is cut apart. The remainder of bottom coil 24 is located inwardly from the opposite edges 18 and the rear edge 16 of bottom ferrite layer 22.
Printed over the bottom subassembly 20 is a first intermediate subassembly 30. Subassembly 30 includes a first intermediate ferrite layer 32 having a via hole 34 ext~ing therethrough. Via hole 34 is registered immediately above the inner end 28 of bottom conductor coil 24.
Printed over the upper surface of first intermediate ferrite layer 32 is a first intermediate coil conductor 36 having an inner end 38 registered over via hole 34 and having an outer end 40. Outer end 40 is spaced inwardly from the front edge 14 of subassembly 20 in contrast to the outer end 26 of bottom coil conductor 24.
Each ferrite layer in the present invention is preferably printed in several multiple prints until the total dry thicknesæ of each ferrite layer is approximately 25 microns thick. Other thicknesses may be used without detracting from the invention. However, the thickness of each ferrite layer requires that the via hole 34 be filled with a conductive filler 42 which provides electrical connection between the inner end 38 of first intermediate coil 36 and the inner end 28 of bottom coil 24.
~, .
Printed above first intermediate subassembly 30 is a second intermediate subassembly 44 having a second ferrite layer 46 formed with a via hole 48, and having a second intermediate coil conductor 50 printed on the second intermediate ferrite layer 46. Second intermediate coil conductor 50 has an outer end 52 registered above via hole 48. Via hole 48 is filled with a conductive filler 56, and is registered above the outer coil end 40 of first intermediate coil 36. Thus, the filler 56 provides electrical connection between the outer coil end 40 of first intermediate coil 36 and the outer coil end 52 of second intermediate coil 50. Second intermediate coil 50 also includes an inner end 54. The entire second intermediate coil 50 is positioned inwardly from the parametric edges of second intermediate ferrite layer 46.
Printed above second intermediate subassembly 44 is a top subassembly 58 which comprises a top ferrite layer 60 having a via hole 62 extending therethrough and a top coil conductor 64 printed over the upper surface of top ferrite layer 60. Top coil conductor 64 includes a top inner coil end 66 which is registered above the via hole 62 and includes a top outer coil end 68 which extends flush with the rear parametric edge of top ferrite layer 60 and which is also registered above the rear edge 16 of bottom ferrite layer 22.
A conductive filler 69 is within via hole 62 and provides electrical connection between the top inner coil end 66 and the inner coil end 54 of second intermediate coil conductor 50.
A ferrite top cap layer 70 is printed over the top subassembly 58 and covers the top subassembly 58. However, the outer coil end 68 of top conductive coil 64 is exposed between the edges of top ferrite layer 60 and the top cap 70.
When the assembly is completed, a continuous electrical path is provided commencing with the outer end 26 of bottom coil conductor 24 and passing through the inner end 28 thereof, through first filler 42 to the inner coil end 38 of first intermediate coil conductor 36. The electrical path ~ 21S8784 continues to outer coil end 40 through second filler 56, outer coil end 52, inner coil end 54, third filler 69, inner coil end 66, and outer coil end 68. It should be noted that the electrical path continues in the same rotational direction (clockwise as shown in Figure 1) from the bottom coil conductor 24 upwardly through the top coil conductor 64.
Any desired number of intermediate coil subassemblies 30, 44 may be printed, or the inductor can be made with only the top subassembly 58 and the bottom subassembly 20, depending upon the particular values of inductance which are required.
Referring to Figure 2, a pair of end terminals 72, 74 are mounted or printed over the front and rear edges of 14, 16 of assembly 10. Terminals 72, 74 can be metallic end caps, or they can be printed conductive material which is printed over the front and rear edges of the inductor 10.
Terminal 72 is in electrical contact with the outer end 68 of top coil conductor 64, and terminal 74 is in electrical contact with the outer end 26 of bottom coil conductor 24.
While the resulting monolithic multilayer chip inductor 10 is shown in Figure 1-3, a method for producing a plurality of inductors 10 is shown in Figures 4-18. In these figures, numerals are used which correspond to the numerals used for similar parts in Figures 1-3. Referring to Figure 4, using a suitable adhesive for microelectronics, a thick mylar sheet of material, 2 inches by 2 inches by 0.010 inches thick (not shown) is attached to the upper surface of a soda lime glass substrate (not shown). Other than mylar, polyethylene, plastic, or any other material having a low coefficient of adhesion may be used. The top surface of this mylar substrate is painted with polyvinyl alcohol or the like, as a release agent. The polyvinyl alcohol is permitted to dry.
The ferrite base or bottom cap 22 shown in Figure 4 is then printed over the polyvinyl alcohol.
After the ferrite bottom cap 22 is printed, a plurality of conductor coils 24 (Figure 5) are printed over bottom cap 22. The outer ends 26 of coils 24 are wider than the remainder of the coils 24, and the plurality of printed coils ~ 21587~4 24 are centered over bottom cap 22. Figures 16, 17 and 18 show a close up view of the plurality of conductor coils 64 of the top ferrite layer as shown in Figure 14. The arrangement of the bottom conductor coils 24 are arranged in a way analogous to the arrangement of the top conductor coils 64 which will be discussed in detail below. Figure 17 shows the conductor coil layout of the prior art. The dotted lines in Figure 17 and 18 show where the ferrite layer with conductor coils will be cut. It can be seen that after the layers are cut, in the prior art a small portion of the conductive coils 24 are left on the adjacent part near the rear edge 14 of assembly 10. This leftover conductive material creates potential shorting problems as well as adding capacitance, and lowers the self-resonant frequency of the device. These problems are solved in the present invention by rotating alternating parts 10 within a column by 180. This is illustrated by analogy in Figures 16 and 18.
The region of the element 10 that makes connection to the outside terminal 74 or 72 is connected to the same region of the element located either directly above or below the part.
In other words, pairs of parts 10 in a column are electrically shorted together until the cutting process separates them. Another advantage of this is that the cutting area tolerance is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade. Also, a pair of silver crosses 75 are printed over ferrite layer 22.
Following the printing of the coils 24, a first intermediate ferrite layer 32 is printed over the coils 24 and includes a plurality of via holes 34 which are in registered alignment over the inner ends 28 of coils 24.
Crosses 75 are aligned with the pair of open cross windows 76 in first intermediate ferrite layer 32 so as to permit proper registration of layer 32 with respect to coils 24.
Next, a plurality of first fillers 42 are printed over the ferrite layer 32 and are in registered alignment with and fit within the via holes 34 so as to completely fill them.
215~784 Crosses 78 are printed over crosses 75 which are registered with cross windows 76.
Next, a plurality of first intermediate coil conductors 36 are printed over first intermediate ferrite layer 32 and are properly aligned so that the inner ends 38 fit over via openings 34 and are in electrical contact with first fillers 42. At the same time four crosses 79 are printed on the four corners of ferrite layer 32.
Additional intermediate suba~semblies may be assembled as desired, and Figures 9-11 illustrate a second intermediate subassembly 44. A second intermediate ferrite layer 46 (Figure 9~ is printed over subassembly 30 and includes via holes 48, and cross windows 82 registered over crosseæ 79.
In Figure 10 conductive fillers 56 are printed over via openings 48 and crosses 84 are printed over windows 82. In Figure 11 coil conductors 50 and four crosses 86 are printed over ferrite layer 46.
The final subassembly or top subassembly 58 is shown in Figures 12 through 14 and includes the top ferrite layer 60 having via holes 62 therein. The ferrite layer 60 is provided with cross windows 83 which are aligned with two of the crosses 86. In Figure 13 conductive fillers 69 and crosses 85 are printed over ferrite layer 60. In Figure 14 conductive coils 64 and four crosses 88 are added. The top coil conductors 64 have outer ends 68 which are of enlarged width and which are positioned adjacent the rear edges of the individual inductors 10 to be formed. Coil conductors 64 also have inner ends 66. The top coil conductors 64 are arranged in the same manner as the bottom coil conductors as discussed above. Figures 16, 17 and 18 show a close up view of the plurality of conductor coils 64 of the top ferrite layer as shown in Figure 14. Figure 17 shows the conductor coil layout of the prior art. The dotted lines in Figures 17 and 18 show where the ferrite layer with conductor coils will be cut. It can be seen that after the layers are cut, in the prior art a small portion 100 of the conductive coils 64 are left on the adjacent part near the rear edge of assembly 10.
This leftover conductive material creates potential shorting problems as well as adding capacitance, and lowers the self-resonant frequency of the device. These problems are solved in the present invention by rotating alternating parts 10 within a column by 180. This is illustrated in Figures 16 and 18. The region of the element 10 that makes connection to the outside terminal 74 or 72 is connected to the same region of the element located either directly above or below the part. In other words, pairs of parts 10 in a column are electrically shorted together until the cutting process separates them. Another advantage of this is that the cutting area tolerance is almost twice as large as in the prior art, making it virtually impossible to miss the conductor material with the blade. The alignment of the various layers in Figures 5-14 is accomplished by means of cross windows 76, 82, 83 and aligning crosses 75, 78, 79, 84, 85, 86 and 88 respectively.
The final ferrite top cap 70 is shown in Figure 15.
Preferably, the top cap 70 is a solid sheet with no openings.
A separate screen contA;n;ng only cutting lines 92 is printed on the top cap with a marking ink.
Alternatively, as shown in Figure 14, a plurality of cutting lines 90 are printed around the periphery of the group of top coils 64 so as to permit the alignment of the final ferrite top cap 70 which has a plurality of cutting line windows in place of cutting lines 92. The windows are registered with the cutting lines 90 so as to provide proper registration of the top cap 70 with respect to the remainder of the assembly, and so as to expose the cutting lines 90 after the assembly is complete.
In the preferred method, after drying, the assembly i8 peeled off of the mylar substrate and sliced into individual parts with a razor blade. The blade is aligned with the cutting lines 92 so that the cuts occur between the thickened portions 68 of coils 64 and between the thickened ends 26 of bottom coils 24. This is the only portion of any of the coil conductors which is exposed by the diamond cuts through the ; 21~87~
assembly. All other portions of bottom and top coils 24, 64, and all of the intermediate coils 36, 50 are completely enclosed by the laminated ferrite layers. If properly aligned before the cutting process, each coil is centered with respect to a plan view of the resulting inductor 10.
The parts are then placed on an alumina substrate (not shown) for sintering. The sintering occurs at 900 centigrade in a box furnace for two hours with careful attention being given to the burnout of the organic binders and the prevention of blisters and cracks.
Alternatively, before cutting the assembly apart, the entire assembly can be fired. Following the firing process, the wafer is mounted onto a wafer holder and then is diced into individual chip inductors with a precision diamond blade dicing saw commonly used in the semiconductor IC industry.
After inspection of each of the individual coils 10, the end terminals 72, 74 are attached. These end terminals are preferably a multilayer structure including a silver termination, a nickel-plate end cap, and a tin lead plating over the end cap.
The present invention provides a simple, efficient, and reliable method of production of the monolithic multilayer chip inductors 10.
The preferred embodiment of the present invention has been set forth in the drawings and specification, and although specific terms are employed, these are used in a generic or descriptive sense only and are not used for purposes of limitation. Also, this invention applies to any other electronic thick film components requiring a connection between the inner conductors and the outer terminals of the component. Changes in the form and proportion of parts as well as in the substitution of equivalents are contemplated as circumstances may suggest or render expedient without departing from the spirit or scope of the invention as further defined in the following claims.
Claims (9)
1. A method of making a monolithic multilayer chip component comprising: constructing a first laminated sheet comprising a plurality of first laminated subassemblies, said first laminated subassemblies arranged adjacent each other on said first sheet, each of said first subassemblies comprising a first ferrite layer having a first edge and a first conductor on said first ferrite layer, each of said first conductors having a first end proximate said first edge of said first ferrite layer, wherein said plurality of first laminated subassemblies are arranged such that said first edge of at least two of said plurality of first ferrite layers are adjacent each other on said first sheet;
constructing a second laminated sheet disposed above said first sheet, said second laminated sheet comprising a plurality of second laminated subassemblies, said second subassemblies arranged adjacent each other on said second sheet, said second subassemblies each comprising a second ferrite layer, each of said second subassemblies corresponding to one of said first subassemblies; cutting said laminated first sheet and said laminated second sheet such that each of said first laminated subassemblies and its corresponding said second laminated subassemblies form an independent structure; and connecting a terminal to said first end of said first conductor, whereby said terminal makes electrical contact with said first end of said first conductor.
constructing a second laminated sheet disposed above said first sheet, said second laminated sheet comprising a plurality of second laminated subassemblies, said second subassemblies arranged adjacent each other on said second sheet, said second subassemblies each comprising a second ferrite layer, each of said second subassemblies corresponding to one of said first subassemblies; cutting said laminated first sheet and said laminated second sheet such that each of said first laminated subassemblies and its corresponding said second laminated subassemblies form an independent structure; and connecting a terminal to said first end of said first conductor, whereby said terminal makes electrical contact with said first end of said first conductor.
2. A method of connecting inner conductors to outer terminals of a monolithic chip component comprising the steps of: constructing a plurality of laminated sheets, said plurality of laminated sheets disposed proximate each other in a stacked, generally parallel relation, each of said laminated sheets comprising a plurality of laminated subassemblies, said laminated subassemblies arranged proximate each other on said laminated sheets, each of said laminated subassemblies corresponding to a laminated subassembly on each of other said plurality of laminated sheets forming a plurality of sets of corresponding laminated subassemblies, said laminated subassemblies each comprising a ferrite layer having a first edge, at least one of said plurality of laminated sheets including a conductor element disposed on each of said ferrite layers, each of said conductor elements having a first end proximate said first edge of said ferrite layer wherein said plurality of laminated subassemblies are arranged such that said first edges of at least two of said ferrite layers containing conductive elements are adjacent each other on said laminated sheet; cutting said plurality laminated sheets such that each set of said corresponding laminated subassemblies forms an independent structure; and connecting a terminal to said first end of each of said conductors.
3. A method of making a plurality of monolithic multilayer chip components comprising: constructing a plurality of laminated sheets, said laminated sheets disposed proximate each other in a stacked, generally parallel relation, each of said laminated sheets comprising a plurality of laminated subassemblies arranged proximate each other on said laminated sheet, said laminated subassemblies each comprising a ferrite layer having a first edge, each of said laminated subassemblies corresponds to another of said laminated subassemblies on each of said other laminated sheets forming a plurality of sets of corresponding laminated subassemblies;
constructing a plurality of conductive elements on at least one of said laminated sheets, each of said conductive elements having a first end, each of said conductive elements disposed on one of said ferrite layers such that said first end is proximate said first edge of said ferrite layer, said laminated subassemblies arranged on said sheet such that said first edge of at least two of said ferrite layers are adjacent each other; cutting said plurality of laminated sheets such that each of said set of corresponding laminated subassemblies forms an independent structure; and connecting a terminal to said first end of each of said conductors.
constructing a plurality of conductive elements on at least one of said laminated sheets, each of said conductive elements having a first end, each of said conductive elements disposed on one of said ferrite layers such that said first end is proximate said first edge of said ferrite layer, said laminated subassemblies arranged on said sheet such that said first edge of at least two of said ferrite layers are adjacent each other; cutting said plurality of laminated sheets such that each of said set of corresponding laminated subassemblies forms an independent structure; and connecting a terminal to said first end of each of said conductors.
4. The method of claim 1 wherein said component is an inductor.
5. The method of claim 1 further comprising at least one intermediate laminated sheet sandwiched between said first laminated sheet and said second laminated sheet, said intermediate laminated sheet comprising a plurality of intermediate laminated subassemblies, said intermediate laminated subassemblies arranged adjacent each other on said intermediate laminated sheet, each of said intermediate subassemblies comprising an intermediate ferrite layer having a first edge.
6. The method of claim 5 wherein each of said intermediate laminated subassemblies includes an intermediate conductor on each of said intermediate ferrite layers.
7. The method of claim 6 wherein each of said intermediate conductors includes a first end proximate said first edge of said intermediate ferrite layer, said plurality of intermediate laminated subassemblies are arranged such that said first edge of at least two of said plurality of intermediate ferrite layers are adjacent each other on said intermediate sheet.
8. The method of claim 1 wherein said second laminated sheet includes a second conductor on each of said second ferrite layers.
9. The method of claim 8 wherein each of said second ferrite layers includes a second edge, each of said second conductors incudes a second end proximate said second edge, said plurality of second laminated subassemblies are arranged such that said second edge of at least two of said plurality of second ferrite layers are adjacent each other on said second sheet.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US33649194A | 1994-11-09 | 1994-11-09 | |
| US08/336,491 | 1994-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2158784A1 true CA2158784A1 (en) | 1996-05-10 |
Family
ID=23316338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2158784 Abandoned CA2158784A1 (en) | 1994-11-09 | 1995-09-21 | Electronic thick film component termination and method of making the same |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0712141A1 (en) |
| JP (1) | JP2660965B2 (en) |
| CA (1) | CA2158784A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986533A (en) * | 1996-06-18 | 1999-11-16 | Dale Electronics, Inc. | Monolithic thick film inductor |
| US5880662A (en) * | 1997-08-21 | 1999-03-09 | Dale Electronics, Inc. | High self resonant frequency multilayer inductor and method for making same |
| MY122218A (en) * | 1998-02-02 | 2006-03-31 | Taiyo Yuden Kk | Multilayer electronic component and manufacturing method therefor |
| KR100318498B1 (en) * | 1999-09-07 | 2001-12-22 | 김춘호 | Jig for side printing of a chip element |
| DE102007043887A1 (en) | 2007-09-14 | 2009-04-16 | Fct Electronic Gmbh | Connector with integrated circuit board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62118505A (en) * | 1985-11-18 | 1987-05-29 | Fujitsu Ltd | Manufacture of laminated chip inductor |
| JPH04329607A (en) * | 1991-04-30 | 1992-11-18 | Murata Mfg Co Ltd | Laminar chip transformer |
| US5302932A (en) * | 1992-05-12 | 1994-04-12 | Dale Electronics, Inc. | Monolythic multilayer chip inductor and method for making same |
-
1995
- 1995-09-21 CA CA 2158784 patent/CA2158784A1/en not_active Abandoned
- 1995-09-22 EP EP95306718A patent/EP0712141A1/en not_active Withdrawn
- 1995-10-12 JP JP7290490A patent/JP2660965B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08227821A (en) | 1996-09-03 |
| JP2660965B2 (en) | 1997-10-08 |
| EP0712141A1 (en) | 1996-05-15 |
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