CA2082408A1 - System and method for preserving source instruction atomicity in translated program code - Google Patents

System and method for preserving source instruction atomicity in translated program code

Info

Publication number
CA2082408A1
CA2082408A1 CA2082408A CA2082408A CA2082408A1 CA 2082408 A1 CA2082408 A1 CA 2082408A1 CA 2082408 A CA2082408 A CA 2082408A CA 2082408 A CA2082408 A CA 2082408A CA 2082408 A1 CA2082408 A1 CA 2082408A1
Authority
CA
Canada
Prior art keywords
code
program code
instruction
instructions
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2082408A
Other languages
French (fr)
Other versions
CA2082408C (en
Inventor
Scott G. Robinson
Richard L. Sites
Richard T. Witek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2082408A1 publication Critical patent/CA2082408A1/en
Application granted granted Critical
Publication of CA2082408C publication Critical patent/CA2082408C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Debugging And Monitoring (AREA)
  • Noodles (AREA)
  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
  • Luminescent Compositions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Retry When Errors Occur (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

A system or method is provided for translating a first program code to a second program code and for executing the second program code wile preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set. A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions. The second code instructions for each first code instruction are organized in a granular instruction sequence. A second computer system is adapted with the second architecture to execute the second program code. During the second code execution, means are provided for determining the occurrence of each asynchronous event during second code execution, and the occurrence of each conflicting write to the memory by another processor, if one is coupled to the memory. In the above mentioned situations, if necessary, first code instruction atomicity and granularity are preserved by: completely or partially aborting the second code instruction sequence, for a retry; or, delaying processing of an asynchronous event interrupt until after the execution of the second code instruction sequence is complete.
CA002082408A 1991-03-07 1992-03-03 System and method for preserving source instruction atomicity in translated program code Expired - Fee Related CA2082408C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66607191A 1991-03-07 1991-03-07
US666,071 1996-06-21

Publications (2)

Publication Number Publication Date
CA2082408A1 true CA2082408A1 (en) 1992-09-08
CA2082408C CA2082408C (en) 1998-11-17

Family

ID=24672704

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002082408A Expired - Fee Related CA2082408C (en) 1991-03-07 1992-03-03 System and method for preserving source instruction atomicity in translated program code

Country Status (15)

Country Link
US (1) US5636366A (en)
EP (1) EP0537309B1 (en)
JP (1) JPH0638234B2 (en)
KR (1) KR950006616B1 (en)
AT (1) ATE180908T1 (en)
CA (1) CA2082408C (en)
DE (1) DE69229319T2 (en)
FI (1) FI925057A0 (en)
IE (1) IE920739A1 (en)
IL (1) IL100991A (en)
MX (1) MX9200936A (en)
NO (1) NO303419B1 (en)
PT (1) PT100205A (en)
TW (1) TW197505B (en)
WO (1) WO1992015946A1 (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3590075B2 (en) * 1992-01-20 2004-11-17 株式会社東芝 Virtual storage data processing apparatus and method
US6091897A (en) 1996-01-29 2000-07-18 Digital Equipment Corporation Fast translation and execution of a computer program on a non-native architecture by use of background translator
US6535903B2 (en) 1996-01-29 2003-03-18 Compaq Information Technologies Group, L.P. Method and apparatus for maintaining translated routine stack in a binary translation environment
US5778211A (en) * 1996-02-15 1998-07-07 Sun Microsystems, Inc. Emulating a delayed exception on a digital computer having a corresponding precise exception mechanism
US5875318A (en) * 1996-04-12 1999-02-23 International Business Machines Corporation Apparatus and method of minimizing performance degradation of an instruction set translator due to self-modifying code
US5764962A (en) * 1996-07-31 1998-06-09 Hewlett-Packard Company Emulation of asynchronous signals using a branch mechanism
US6052530A (en) * 1996-10-09 2000-04-18 Hewlett-Packard Co. Dynamic translation system and method for optimally translating computer code
US5828897A (en) * 1996-12-19 1998-10-27 Raytheon Company Hybrid processor and method for executing incrementally upgraded software
US6567910B2 (en) * 1998-02-13 2003-05-20 Texas Instruments Incorporated Digital signal processing unit with emulation circuitry and debug interrupt enable register indicating serviceable time-critical interrupts during real-time emulation mode
US8631066B2 (en) * 1998-09-10 2014-01-14 Vmware, Inc. Mechanism for providing virtual machines for use by multiple users
US7516453B1 (en) * 1998-10-26 2009-04-07 Vmware, Inc. Binary translator with precise exception synchronization mechanism
US6763452B1 (en) 1999-01-28 2004-07-13 Ati International Srl Modifying program execution based on profiling
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8065504B2 (en) * 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US7761857B1 (en) * 1999-10-13 2010-07-20 Robert Bedichek Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US6594821B1 (en) 2000-03-30 2003-07-15 Transmeta Corporation Translation consistency checking for modified target instructions by comparing to original copy
US6615300B1 (en) 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
GB2367653B (en) * 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
US6829630B1 (en) * 2000-11-24 2004-12-07 Xerox Corporation Mechanisms for web-object event/state-driven communication between networked devices
US20030120899A1 (en) * 2001-12-20 2003-06-26 Stotzer Eric J. Apparatus and method for processing an interrupt in a software pipeline loop procedure in a digital signal processor
US6895460B2 (en) 2002-07-19 2005-05-17 Hewlett-Packard Development Company, L.P. Synchronization of asynchronous emulated interrupts
JP3900485B2 (en) * 2002-07-29 2007-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Optimization device, compiler program, optimization method, and recording medium
US7310723B1 (en) 2003-04-02 2007-12-18 Transmeta Corporation Methods and systems employing a flag for deferring exception handling to a commit or rollback point
US8413162B1 (en) 2005-06-28 2013-04-02 Guillermo J. Rozas Multi-threading based on rollback
US8726248B2 (en) * 2008-06-12 2014-05-13 Oracle America, Inc. Method and apparatus for enregistering memory locations
US8438558B1 (en) 2009-03-27 2013-05-07 Google Inc. System and method of updating programs and data
US9824039B2 (en) * 2013-09-09 2017-11-21 International Business Machines Corporation Signal interrupts in a transactional memory system
US11061685B2 (en) 2019-02-27 2021-07-13 International Business Machines Corporation Extended asynchronous data mover functions compatibility indication
US10698854B1 (en) * 2019-02-27 2020-06-30 International Business Machines Corporation Secure and efficient application data processing
US11449367B2 (en) 2019-02-27 2022-09-20 International Business Machines Corporation Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4674038A (en) * 1984-12-28 1987-06-16 International Business Machines Corporation Recovery of guest virtual machines after failure of a host real machine
US5218712A (en) * 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
US5193167A (en) * 1990-06-29 1993-03-09 Digital Equipment Corporation Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system

Also Published As

Publication number Publication date
EP0537309B1 (en) 1999-06-02
KR950006616B1 (en) 1995-06-19
PT100205A (en) 1994-04-29
JPH0638234B2 (en) 1994-05-18
NO924260L (en) 1993-01-06
DE69229319D1 (en) 1999-07-08
WO1992015946A1 (en) 1992-09-17
NO303419B1 (en) 1998-07-06
DE69229319T2 (en) 2000-01-27
JPH05505693A (en) 1993-08-19
ATE180908T1 (en) 1999-06-15
FI925057A (en) 1992-11-06
CA2082408C (en) 1998-11-17
EP0537309A1 (en) 1993-04-21
IL100991A (en) 1996-09-12
AU654707B2 (en) 1994-11-17
NO924260D0 (en) 1992-11-05
TW197505B (en) 1993-01-01
FI925057A0 (en) 1992-11-06
US5636366A (en) 1997-06-03
IE920739A1 (en) 1992-09-09
MX9200936A (en) 1993-04-01
AU1571492A (en) 1992-10-06

Similar Documents

Publication Publication Date Title
CA2082408A1 (en) System and method for preserving source instruction atomicity in translated program code
WO1987000316A3 (en) Fault tolerant data processing system
US4412303A (en) Array processor architecture
EP0380850A3 (en) Multiple instruction preprocessing
EP0377990A3 (en) Data processing systems
EP0335515A3 (en) Method and apparatus for executing instructions for a vector processing system
US4972317A (en) Microprocessor implemented data processing system capable of emulating execution of special instructions not within the established microprocessor instruction set by switching access from a main store portion of a memory
CA2062771A1 (en) Information processing system emulation apparatus and method
CA2123448A1 (en) Blackout Logic for Dual Execution Unit Processor
US5757685A (en) Data processing system capable of processing long word data
EP0240606B1 (en) Pipe-line processing system and microprocessor using the system
US4455604A (en) Digital data processing system having addressing means for translating operands into descriptors identifying data, plural multilevel microcode control means, and ability to execute a plurality of internal language dialects
KR0136111B1 (en) Apparatus and method for synhcronization of access to main memory signal groups in a multiprocessor data processing
US6032249A (en) Method and system for executing a serializing instruction while bypassing a floating point unit pipeline
JPH0552539B2 (en)
EP0333365A3 (en) Method and apparatus for handling asynchronous memory management exceptions by a vector processor
JPS60195661A (en) Data processing system
JP2510691B2 (en) Arithmetic processing method
JPS54158831A (en) Data processor
JPS6259829B2 (en)
Giering III et al. Ada 9X asynchronous transfer of control: Applications and implementation
JPS6236576B2 (en)
JPS5955546A (en) Firmware processor
EP0278263A3 (en) Multiple bus dma controller
JP2692865B2 (en) Sequencer differential instruction processing method

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed