CA2050828A1 - Architecture de registre et d'antememoire et machine a super-acteurs - Google Patents

Architecture de registre et d'antememoire et machine a super-acteurs

Info

Publication number
CA2050828A1
CA2050828A1 CA 2050828 CA2050828A CA2050828A1 CA 2050828 A1 CA2050828 A1 CA 2050828A1 CA 2050828 CA2050828 CA 2050828 CA 2050828 A CA2050828 A CA 2050828A CA 2050828 A1 CA2050828 A1 CA 2050828A1
Authority
CA
Canada
Prior art keywords
super
actor
cache
actors
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2050828
Other languages
English (en)
Inventor
Herbert H.J. Hum
Guang R. Gao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
McGill University
Centre de Recherche Informatique de Montreal CRIM
Original Assignee
Herbert H.J. Hum
Guang R. Gao
Mcgill University
Centre De Recherche Informatique De Montreal/ Computer Research Institut E Of Montreal
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Herbert H.J. Hum, Guang R. Gao, Mcgill University, Centre De Recherche Informatique De Montreal/ Computer Research Institut E Of Montreal filed Critical Herbert H.J. Hum
Publication of CA2050828A1 publication Critical patent/CA2050828A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA 2050828 1991-05-28 1991-09-06 Architecture de registre et d'antememoire et machine a super-acteurs Abandoned CA2050828A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70658991A 1991-05-28 1991-05-28
US07/706,589 1991-05-28

Publications (1)

Publication Number Publication Date
CA2050828A1 true CA2050828A1 (fr) 1992-11-29

Family

ID=24838253

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2050828 Abandoned CA2050828A1 (fr) 1991-05-28 1991-09-06 Architecture de registre et d'antememoire et machine a super-acteurs

Country Status (1)

Country Link
CA (1) CA2050828A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860138A (en) * 1995-10-02 1999-01-12 International Business Machines Corporation Processor with compiler-allocated, variable length intermediate storage
US6088788A (en) * 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US6205519B1 (en) 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860138A (en) * 1995-10-02 1999-01-12 International Business Machines Corporation Processor with compiler-allocated, variable length intermediate storage
US6088788A (en) * 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US6205519B1 (en) 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor

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Legal Events

Date Code Title Description
EEER Examination request
FZDE Dead