CA2050755A1 - Method and apparatus for organizing and analyzing timing information - Google Patents

Method and apparatus for organizing and analyzing timing information

Info

Publication number
CA2050755A1
CA2050755A1 CA002050755A CA2050755A CA2050755A1 CA 2050755 A1 CA2050755 A1 CA 2050755A1 CA 002050755 A CA002050755 A CA 002050755A CA 2050755 A CA2050755 A CA 2050755A CA 2050755 A1 CA2050755 A1 CA 2050755A1
Authority
CA
Canada
Prior art keywords
dependence
state
signal
specifications
dependences
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002050755A
Other languages
English (en)
French (fr)
Inventor
Steven K. Sherman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2050755A1 publication Critical patent/CA2050755A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
CA002050755A 1990-09-06 1991-09-05 Method and apparatus for organizing and analyzing timing information Abandoned CA2050755A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/578,723 1990-09-06
US07/578,723 US5353433A (en) 1990-09-06 1990-09-06 Method and apparatus for organizing and analyzing timing information

Publications (1)

Publication Number Publication Date
CA2050755A1 true CA2050755A1 (en) 1992-03-07

Family

ID=24314036

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002050755A Abandoned CA2050755A1 (en) 1990-09-06 1991-09-05 Method and apparatus for organizing and analyzing timing information

Country Status (6)

Country Link
US (1) US5353433A (enExample)
EP (1) EP0474359B1 (enExample)
JP (1) JPH04246776A (enExample)
AU (1) AU654479B2 (enExample)
CA (1) CA2050755A1 (enExample)
DE (1) DE69127798T2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367469A (en) * 1990-12-13 1994-11-22 Vlsi Technology, Inc. Predictive capacitance layout method for integrated circuits
US5475607A (en) * 1994-04-12 1995-12-12 International Business Machines Corporation Method of target generation for multilevel hierarchical circuit designs
US5640328A (en) * 1994-04-25 1997-06-17 Lam; Jimmy Kwok-Ching Method for electric leaf cell circuit placement and timing determination
US5475605A (en) * 1994-05-26 1995-12-12 Cadence Design Systems, Inc. Timing analysis for logic optimization using target library delay values
US5675502A (en) * 1995-08-22 1997-10-07 Quicklogic Corporation Estimating propagation delays in a programmable device
JP2874628B2 (ja) * 1996-01-30 1999-03-24 日本電気株式会社 論理回路の最適化装置及びその方法
US5978929A (en) * 1997-03-20 1999-11-02 International Business Machines Corporation Computer unit responsive to difference between external clock period and circuit characteristic period
JP3445476B2 (ja) * 1997-10-02 2003-09-08 株式会社東芝 半導体メモリシステム
US6675310B1 (en) * 2000-05-04 2004-01-06 Xilinx, Inc. Combined waveform and data entry apparatus and method for facilitating fast behavorial verification of digital hardware designs
US6961931B2 (en) * 2001-01-10 2005-11-01 International Business Machines Corporation Dependency specification using target patterns
US6993695B2 (en) * 2001-06-06 2006-01-31 Agilent Technologies, Inc. Method and apparatus for testing digital devices using transition timestamps
US8082140B2 (en) 2008-04-16 2011-12-20 GM Global Technology Operations LLC Parametric analysis of real time response guarantees on interacting software components
EP2746474B1 (de) 2012-12-21 2020-04-22 Geberit International AG Spülvorrichtung mit Geruchsabsaugung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527249A (en) * 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
US4763289A (en) * 1985-12-31 1988-08-09 International Business Machines Corporation Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
US5126966A (en) * 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4965758A (en) * 1988-03-01 1990-10-23 Digital Equipment Corporation Aiding the design of an operation having timing interactions by operating a computer system
US5212783A (en) * 1988-06-13 1993-05-18 Digital Equipment Corporation System which directionally sums signals for identifying and resolving timing inconsistencies
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits

Also Published As

Publication number Publication date
DE69127798T2 (de) 1998-04-30
JPH04246776A (ja) 1992-09-02
DE69127798D1 (de) 1997-11-06
US5353433A (en) 1994-10-04
EP0474359A3 (enExample) 1994-01-05
EP0474359B1 (en) 1997-10-01
AU654479B2 (en) 1994-11-10
AU7501891A (en) 1992-03-12
EP0474359A2 (en) 1992-03-11

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Legal Events

Date Code Title Description
FZDE Discontinued