CA2050632C - Digital beam-forming technique using temporary noise injection - Google Patents
Digital beam-forming technique using temporary noise injectionInfo
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- CA2050632C CA2050632C CA002050632A CA2050632A CA2050632C CA 2050632 C CA2050632 C CA 2050632C CA 002050632 A CA002050632 A CA 002050632A CA 2050632 A CA2050632 A CA 2050632A CA 2050632 C CA2050632 C CA 2050632C
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- input signal
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Radar Systems Or Details Thereof (AREA)
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
An efficient digital beam-forming network (100) utilizing a relatively few small-scale A/D converters is disclosed herein. The inventive beam-forming network (100) is disposed to generate an output beam B in response to a set of N input signals. The set of input signals is provided by an antenna array (110) having N
elements, upon which is incident an electromagnetic wavefront of a first carrier frequency. The present invention includes an orthogonal encoder circuit (170) for generating a set of N orthogonal voltage waveforms.
A set of biphase modulators (162-168) modulates the phase of each of the input signals in response to one of the orthogonal voltage waveforms, thereby generating a set of N phase modulated input signals. The N phase modulated input signals are combined within an adder (180) to form a composite input signal. The inventive network (100) further includes a downconverting mixer (184) for generating an IF input signal in response to the composite input signal. The IF input signal is then separated into baseband in-phase and quadrature-phase components by an I/Q split network 192. A pair of A/D
converters (198, 200) then sample the in-phase and quadrature-phase components of the input signal. A
decoder (202), coupled to the orthogonal encoder circuit (170), provides decoded digital in-phase signals and decoded digital quadrature phase signals in response to the digital in-phase and quadrature-phase signals. The present invention further includes a digital beam-former (130) for generating the output beam B by utilizing the decoded in-phase and quadrature-phase signals.
elements, upon which is incident an electromagnetic wavefront of a first carrier frequency. The present invention includes an orthogonal encoder circuit (170) for generating a set of N orthogonal voltage waveforms.
A set of biphase modulators (162-168) modulates the phase of each of the input signals in response to one of the orthogonal voltage waveforms, thereby generating a set of N phase modulated input signals. The N phase modulated input signals are combined within an adder (180) to form a composite input signal. The inventive network (100) further includes a downconverting mixer (184) for generating an IF input signal in response to the composite input signal. The IF input signal is then separated into baseband in-phase and quadrature-phase components by an I/Q split network 192. A pair of A/D
converters (198, 200) then sample the in-phase and quadrature-phase components of the input signal. A
decoder (202), coupled to the orthogonal encoder circuit (170), provides decoded digital in-phase signals and decoded digital quadrature phase signals in response to the digital in-phase and quadrature-phase signals. The present invention further includes a digital beam-former (130) for generating the output beam B by utilizing the decoded in-phase and quadrature-phase signals.
Description
~ / 20~0632 DIGITAL BEAM--~ORMING SYSTEM WITII DYNAMIC RANGE LIMITING
BACK~KUUNL OF THE INVENTION
~ S~ the Invention:
This invention relates to beam-forming networks used in conjunction with antenna arrays. More specifically, this invention relates to digital beam-forming networks.
While the present invention is described herein with 15 reference to a particular embodiment, it is understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional embodiments within the scope thereof.
DescriPtion of the Related Art:
Prior to advances in digital technology, beam-forming in response to a wavefront incident on a radar or 25 communications antenna array was performed in the analog domain. In analog beam-forming systems, signals are manipulated in radio frequency (RF) microwave networks or at an intermediate frequency (IF) in the receiver.
Efficient analog beam-forming schemes utilized a Butler 30 or a Bliss network. While offering improvements over earlier analog beam-formers, the performance of these more efficient analog networks were nonetheless plagued by resistive losses, critical tolerances, and lack of multiplexing capability. In light of these limitations, 35 efforts have been made to develop digital approaches.
BACK~KUUNL OF THE INVENTION
~ S~ the Invention:
This invention relates to beam-forming networks used in conjunction with antenna arrays. More specifically, this invention relates to digital beam-forming networks.
While the present invention is described herein with 15 reference to a particular embodiment, it is understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional embodiments within the scope thereof.
DescriPtion of the Related Art:
Prior to advances in digital technology, beam-forming in response to a wavefront incident on a radar or 25 communications antenna array was performed in the analog domain. In analog beam-forming systems, signals are manipulated in radio frequency (RF) microwave networks or at an intermediate frequency (IF) in the receiver.
Efficient analog beam-forming schemes utilized a Butler 30 or a Bliss network. While offering improvements over earlier analog beam-formers, the performance of these more efficient analog networks were nonetheless plagued by resistive losses, critical tolerances, and lack of multiplexing capability. In light of these limitations, 35 efforts have been made to develop digital approaches.
In digital beam-f orming systems, operations are performed on digitized baseband in-phase (I) and quadrature-phase (Q) signals within special-purpose digital processors in order to form the beams. Certain 5 radar and communications antennas using digital beam-forming techniques require beam-forming networks with a wide dynamic range in order to maintain accuracy in the face of signal clutter or intentional jamming. This minimum dynamic range requirement currently necessitates 10 the utilization of analog-to-digital (A/D) converters typically having at least seven bits of resolution.
Moreover, many conventional digital beam-forming systems employ separate A~D converters to process the I and Q
signals associated with each element in the receive 15 array.
Such large-scale use of A/D converters increases the power requirements, weight and complexity of the net~rork. For satellite applications, reductions in the magnitude of each of these parameters is tantamount to an 20 optimal design. ~ence, a need exists in the art for a digital beam-forming network employing a minimal number of A/D converters, ideally with each converter being of a minimal bit size.
SUMN~RY OF T}~E INVENTION
The need in the art for a more ef~ficient digital 30 beam-forming apparatus utilizing few, small-scale, A/D
converters is addressed by the improved digital beam-forming network of the present invention. The inventive network is disposed to generate an output beam in response to a set of N input signals. The set of input 35 signals is provided by an antenna array having N
Moreover, many conventional digital beam-forming systems employ separate A~D converters to process the I and Q
signals associated with each element in the receive 15 array.
Such large-scale use of A/D converters increases the power requirements, weight and complexity of the net~rork. For satellite applications, reductions in the magnitude of each of these parameters is tantamount to an 20 optimal design. ~ence, a need exists in the art for a digital beam-forming network employing a minimal number of A/D converters, ideally with each converter being of a minimal bit size.
SUMN~RY OF T}~E INVENTION
The need in the art for a more ef~ficient digital 30 beam-forming apparatus utilizing few, small-scale, A/D
converters is addressed by the improved digital beam-forming network of the present invention. The inventive network is disposed to generate an output beam in response to a set of N input signals. The set of input 35 signals is provided by an antenna array having N
element3, upon which i3 incident an electromagnetic wavefront of a fir3t carrier frequency. In a mo3t general 3enae, the invention includes circuitry for limiting the dynamic range of the input signals. The range limited input 3ignala are then digitized and used to form an output beam in a convPnt;r-n~l manner.
In a specific embodiment, the pre3ent invention ;nf~ 1P~ an orthogonal encoder circuit for generating a 8et of N orthogonal voltage waveform3. A 3et of biphase modulator3 ---A~ tPI~ the pha3e of each of the input signals in re8ponse to one of the orthogonal voltage waveforms, thereby generating a 3et of N phase modulated input 3ignals. The N phase modulated input 3ignal3 are combined within an adder to form a compo3ite input 3ignal. The inventive network further include3 a downconverting mixer for generating an IF input 3ignal in respon3e to the compo3ite input signal.
The IF input 3ignal is then 3eparated into ba3eband in-pha3e and guadrature-pha3e .:, . nt~ by an I/Q 3plit network. A pair of A/D converters then sample the in-phase and quadrature-phase cl _ ~nPntFl o~ the input 3ignals. A decoder, coupled to the orthogonal encoder circuit, provides decoded digital in-phase 3ignal3 and decoded digital quadrature phase signals in response to the digital in-phase and quadrature-phase signals. The present invention further ;n~l~]~ a digital beam-former for generating the output beam by llt;1;7;ng the decoded in-phase and guadrature-phase signals.
Other aspects of this invention are as follow3:
A method of generating an output beam in response to a set of N input signal3, said set of input 3ignals being provided by an antenna array having N element3 upon which is incident an electromagnetic wavef ront of a first carrier ~requency, said method including the 3tep3 of:
-3a- 20~632 a) limiting the dynamic range of said input signal~;
b) digitizing the range limited input signals;
and c) îorming an output beam based on the digitized range limited input signals.
A digital beam forming network for generating an output beam in response to a set of N input signals, said set of input signals being provided by an antenna array having N ~1., t~: upon which is incident an electromagnetic wavefront of a first carrier requency, comprising:
an encoder for generating a set of N orthogonal voltage waveforms;
a biphase modulator f or modulating the phase o each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
an adder f or combining said ~ phase modulated input signals to ~orm a composite input signal;
a downconverter for generating an IF input signal in re3ponse to said composite input signal;
a converter or converting said IF input signal into baseband in-phase and quadrature-phase components;
a digital converter f or converting said in-phase and quadrature-phase components to digital in-phase and digital quadrature-phase signals;
a decoder, coupled to said orthogonal encoder, for providing N decoded digital in-phase signals and N
D
3b 20~0632 decoded digital ~uadrature phase signals in response to said digital in-phase and ~lUCld~ UL~, phase 6ignals; and a dig$tal beam former for generating said output beam by utilizing said decoded in-phase and quadL~lLu~e phase signals .
A tD~hn;~lD for forming an output beam in ~e:~y~
to a set of N input signals, said set of input signals being provided by an antenna array having N elements upon which is ~n~ ~dDnt an eleeL. _ ~ic wavefront of a first carrier fre~uency, comprising the steps of:
a) generating an set of N C1~ A1 voltage waveforms:
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into bsl__h~nS
in-phase and quadrature-phase - A -ts;
f) sampling said in-phase and quadL~.Lul. phase L~ to create N digital in-phase and N digital quacl.~Lu~. yl~ase signals;
g) multiplying each of said or~hoj~AnAl voltage w~ve~r~ with one of said N digital in-phase signals and one of said N digital quad~.lLu~a pllase signals in order to provide N decoded digital in-phase signals and N
decoded digital ~ulld~ u-~ phase signals; and h) generating said output beam by utilizing said decoded in-phase and quad...Lu.- phase signals.
A digital beam forming c,uL--et ~ for driving a digital beam former in re"y~ ..t,e to a set of N input ~iignals, said set of input signal5 being provided by N
elements of an antenna array upon which is incident an 3c 2~50632 ele~LL. ~lletic wavefront of a Pirst carrier frequency, comprising:
orth~qonAl encoder means for generating a set of N
orthogonal voltage waveform5;
biphase modulator mean# for modulating the phase of each of said input signals in r~ u~,Jc to one of said orthf~gonAl voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals to form a composite input signal;
d. ..l~aUIl~:L LeL means for generating an IF input signal in res~ c to said composite input signal;
means for converting said IF input signal into bA~hAnrl in-phase and quadrature-phase _ ,-n~nts;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quad.cl~uLe phc.se signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadL~LuL~ phase signals to said digital beam former in response to sald dlgltal ln-phase and qUalL-lLUL~ phase signals.
A t~rhnique for driving a digital beam former in respûnse to a set Or N input slgnals, said set of input signals being provided by N elements of an antenna array upon which is lncldent an ele. Ll- gnetlc wavefront of a first carrier rrequency, comprisinq the steps of:
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in r~u~ e to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
3d 2050632 e) converting said IF input signal into hAc~.hAn~
in-phase and quadLa~uL~ phase ~ _ ts;
r) - l; n'J said in-phase and quadrature-phase ~ to create digital in-phase and digital ~u- 1L~ILUL~ ase signals: and g) multiplying each of said ~Ll ~'O~ IA1 voltage waveforms with one of said digital in-phase signals and one of said digital qualL~uL~ phase signals in order to provide decoded digital in-phase signals and decoded digital quadrature phase signals to said beam former, A digital beam forming subnetwork for driving a digital beam former in response to a set of N input signals, said set of input signals being provided by N
elements of an antenna array upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising:
orthogonal encoder means for generating a set of N
orthogonal voltage waveforms;
oiphase modulator means for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals to form a composite input signal;
downconverter means f or generating an IF input signal in response to said composite input signal;
means for converting said IF input ~ignal into b~C~h~n~l in-phase and quadrature-phase c -~ts;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadrature-phase signals to said digital beam former in response to said digital in-phase and quadrature-phase siynals.
- 3e - 2~0~32 BRIEF D~S~c~ ON OF THE DRAWINGS
Fig. 1 is a block diagrammatic representation of a simplified ~mho~iir-~lt of the digital beam-forming network ~ 205~632 of the present invention.
Fig. 2 is a block diagrammatic representation of a preferred emoodiment of the digital beam-forming network of the present invention.
rr~Trrn DESCRIPTION OF T}iE INVENTION
Fig. l is a block diagrammatic representation of a simplified embodiment of the digital beam-forming network 10 of the present invention. The beam-forming network 10 accepts a set of M input signals on N input signal lines 12 from a receive antenna array 14 having N elements 16.
1~ The input signals on the lines 12 are generated by electromagnetic wavefronts incident on the receive array 14 and share a common high frequency carrier (e.g.
microwave). The inventive network 10 is disposed to generate one or more electromagnetic beams B in response 20 to the high frequency input signals impressed on the lines 12. The beam B may then be routed to, for example, a digital processing network (not shown).
As noted in the Background of the Invention, A/D
converters employed in conventional beam-forming networXs 25 require a relatively large number of bits as a result of _he dynamic range of the signals processed thereby. The necessary dynamic range is de~m;nr~d on the basis of the power level difference between the strongest anticipated communication or ~amming signal and the thermal noise 30 floor. Speci~ically, a 40 ds dynamic range requires an A/D converter having approximately 7 to 8 bits. As discussed more fully below, the inventive beam-forming network 10 is operative to inject band-limited noise into the ~igh frequency input signals originating within the 35 array 14 in order to raise the noise floor and thus 5 ~5~163~
decrease the dynamic range neces6ary in the analog to digital conversion process. This engineerea decrease in dynamic range enables A/D converters within the network 10 to func~ion using fewer bits, which reduces power requirements, cost, and complexity. ~n certain instances the inventive beam-forming network 10 may require A/D
converters having as few as one to three bits. The injected noise is substantially precluded from b~-nm;n~
aliased into the signal band during the analog-to-digital conversion process by sampling at a sufficiently high rate .
The digital beam-forming network 10 includes a set of M low-noise amplifiers 18, with each amplifier 18 being coupled to an array element 16 by a signal line 12.
The amplifiers 18 each have ps~ h~n~ centered about the carrier frequency of the input signals present on the lines 12. The amplified high frequency input signals are then transmitted over a set of M amplifier output lines 20 to a set of M summation networks 22.
Each summation network 22 is addressed by an amplifier output line 20 and by one of a set of M noise sources 24. The noise sources 24 each contain a noise generator 26 and a bandpass filter 28. The passband of each filter 28 is ad~usted in response to the degree to which it is desired to raise the noise floor, or equivalently, to the degree to which it is desired to reduce the apparent dynamic range spanned by the amplified input signals present on the lines 20. The summation networks 22 thus launch the amplified input signals and band-limited noise onto downconverter input lines 30.
A set of M downconverting mixers 32, each coupled to one of the lines 30, convert the set of ~ high frequency input signals to a set of signals centered about an 35 intermediate frequency (IF) . A set of M local - ~ 20S~163~
oscillators 34 provide re~erence ~requencies for the mixers 32. The IF signals are impressed on mixer output lines 36 ana transmitted to a set of N conversion modules 38. Each module 38 includes circuitry for converting the IF signals into in-phase (I) and quadrature-phase (Q) baseband components. A pair of A/D converters within each conversion module 38 then digitize the I and Q
components by sampling each at a pr~ pt~rm;n~d rate. To prevent Nyquist-type ~1 iacin~ of the injected noise into the digital frequency spectra occupied by the sampled I
and Q components, the sampling rate is chosen to be at least twice the magnitude of the bandwidth of the injected noise. For example, a bandpass filter 28 defining a ~ z noise bandwidth would require an A/D
converter executing approximately 2 Mega samples/second in order to prevent aliasing.
The sampled I and Q components are provided to a digital beam-former 40 via a pair of conversion module output lines 42 and 44. The beam-former 40 typically includes a special purpose digital processor for arithmetically manipulating the sampled I and Q
components. As is well known, during each processor clock period the sampled I and Q components are processed to form one or more beams B. The beam-former 40 may also include digital band rejection filters having stopbands coincident with the p~qb~n~q of the filters 28. These band rej ection f ilters may be employed to prevent infiltration of injected noise into the beam B
notwithstanding sampling in excess of the Nyquist rate.
In this manner the inventive beam-forming network 10 is operative to temporarily inject band-limited noise into signals originating in elements of a receive array, thereby reducing the number of bits required in the A/D
conversion process.
Fig. 2 is a block diagrammatic representation of a 7 zoSQ63~
preferred embodiment of the digital beam-forming network 100 of the present invention. The network 100 is addressed by signals originating within a receive antenna array 110 under illumination by an electromagnetic wavefront. The receive array llo includes N antenna elements. Fig. 2 explicitly shows the first, second, third and fourth elements 112, 114, 116, 118 as well as the next to last and last elements N-l, N. The first four elements 112-118 are coupled to a first beam-forming subnetwork 120. In the embodiment of Fig. 2 the inventive beam-forming network loO includes N/4 subnetworks which together feed a digital beam-former 130. It is emphasized that the teachings of the present invention extend to subnetworks coupled to substantially any number of receiver array elements and that a subnetwork lZ0 having only four r h:: nnr~l S was selected for purposes of clarity.
The subnetwork 120 accepts first, second, third and fourth input signals generated by the first, second, third and fourth array elements 112-118 on first, second, third and fourth input signal lines 132-138. Again, the frequency of each of the input signals is centered about a high frequency carrier (e.g. microwave) equivalent to that of the wavefront incident on the array 110. The subnetwork 120 is operative to deliver sampled in-phase (I) and quadrature-phase (Q) components associated with the first, second, third and fourth input signals to the beam-former 130. The beam-former 130 generally includes a special-purpose digital processor and is driven by sampled I/Q signals from each of the N/4 subnetworks within the inventive network 100. The beam-former conventionally synthesizes one or more beams B in response to the I/Q signals supplied thereto. The information associated with each beam may then be routed to a separate processor (not shown) for further digital ~ 20S063~
processing .
As is discussed more fully below, the principle of utilizing noise injection as a means of reducing the required A/D converter dynamic range is also implemented in the preferred embodiment of Fig. 2. ~owever, auxiliary band-limited noise sources such as those described with reference to Fig. 1 will generally not be needed in the inventive network 100 of Fig. 2. Rather, reductions in the requisite A/D dynamic range are effectuated within each subnetwork by code-division multiplexing of the four channels thereof such that the noise floor of each channel is raised by the signals present on the re-~;n1n~ three ~-hAnn~1 c As shown in Fig. 2, the first, second, third and fourth input signals drive first, second, third and fourth low-noise amplifiers (LNA's) 142, 144, 146, 148.
~he LNA's 142-148 typically have substantially identical frequency passbands centered about the high-frequency carrier and are disposed to impress first, second, third and fourth amplified input signals on first, second, third and fourth amplifier output lines 152-158. The fre~uency spectra of each of the ampli~ied input signals may be further limited by coupling a hAn~rAc:c filter (not shown) to each of the LNA ' s .
The amplifier output lines 152-158 each feed a first port of f irst, second, third and fourth biphase modulators 162, 164, 166, 168. A second port of each of the biphase modulators 162-168 is coupled to a code-division multiplexing encoder 170 via first, second, third and fourth phase control lines 172-178. The encoder 170 is operative to supply a set of four orthogonal voltage waveforms to the biphase modulators 162-168 via the four phase control lines 172--178. ~he encoder 170 is operative at a known ciock rate and, during each clock cycle, impresses either a normalized ~' 20~0632 voltage of +l or -1 on each of the lines to the modulators 172-178. For example, the following set of orthogonal voltage square waves may be sent to the biphase modulators 162-168 over a particular four clock 5 cycle interval:
First waveform to f irst modulator: 1 1 1 -1 second waveform to second moaulator: 1 1 -1 Third waveform to third modulator: 1 -1 1 1 Fourth waveform to fourth modulator: -1 1 1 A normalized voltage of +1 present on a line 172-178 induces the modulator 162-168 coupled thereto to leave intact the phase of the amplified input signal present on the associated line 152-158. Alternatively, during clock cycles of the encoder 170 wherein a -1 normalized voltage is impressed on one of the lines 172-178, the modulator 162-168 coupled thereto inverts the phase of the amplified signal present on the associated line 152-158. In this manner, the biphase modulators 162-168 impress first, second, third and fourth orthogonally phase modulated signals on biphase modulator output lines 182', 184', 186' and 188'.
The encoder 170 includes a TTL square wave circuit for generating the set of orthogonal voltage waveforms transmitted by the lines 172-178. The clock rate of the encoder 170 is chosen to be at least large as the magnitude of the sum of the frequency bandwidths of the amplified input signals present on the lines 152-158.
For example, if the bandwidth of each the four LNA's 142-148 (or bandpass filters coupled thereto) is lMHz, then the minimum acceptable clock rate of the encoder 170 is 4MHz. The encoder 170 may be purchased off-the-shelf as a code generator.
The first, second, third and fourth orthogonally lo ~5063~
phase modulated slgnals are summed within a 4 :1 combiner 180. The combiner 180 impresses a composite phase modulated input signal on a combiner output line 182 coupled thereto. The composite input signal is then fed 5 to a first port of a downconverting mixer 184 coupled to the output line 182. A local oscillator 186 is connected to a second port of of the mixer 184. Since the carrier frequency of the composite input signal is known, the frequency of the local oscillator 186 is chosen such that 10 the carrier of the composite input signal is converted to a desired int~ te frequency (IF~. This composite IF
signal is then sent through a bandpass filter l90 via a mixer output line 188. The r~ccb~n~ of the filter 190 is centered about the IF fre~uency.
The bandpass filter 190 is coupled to an I/Q split network 192 through a filter output line 194. The I/Q
split network 192 includes a pair of synchronous baseband mixers for conventionally converting the composite IF
signal into in-phase (I) and quadrature-phase (Q) 20 components. The network 192 impresses the in-phase components on a first A/D input line 194, and impresses the quadrature-phase components on a second A/D input line 196. First and second A/D converters 198, 200 connected to the lines 194, 196 then sample the I and Q
25 components at a known sampling rate and launch the sampled I components on a first A/D output line 199 and launch the sampled Q components on a second A/D output line 201. It is observed that the subnetwork 120 included within the present invention re~uires only two 30 A/D converters, whereas conventional digital beam-forming networks generally utilize a pair of A/D converters for each antenna array element.
The minimum A/D sampling rate is determined by considering the baseband signal from which the I and Q
35 components are derived to be a set of four code-11 ZO5~6~
multiplexed signals, each having a noise bandwidthequivalent to the sum of the bandwidths of the input signals present on thQ lines 152-158 For example, if each LNA 142-148 has a bandwidth of approximately 1 MHz 5 then each code-multiplexed baseband signal may be treated as having a bandwidth of approximately 4 MHz.
Accordingly, to prevent Nyquist-type al i~c;n~ the minimum theoretically acceptable sampling rate would be 8 MHz -although in actual operation a slightly higher rate o~ 10 10 ~IHz would generally be utilized. The inventive network 100 is thus operative to reduce the requisite dynamic range of each of the A/D converters 198 and 200 by using three of the input signals to raise the noise ~loor accompanying the r ~;nin~ input signal. In this manner, 15 no external noise sources need be utilized, as in the case of the simplified embodiment of Fig. 1, in order to reduce the necessary A/D converter dynamic range.
In the embodiment of Fig. 2 the multiplexed baseband I and Q components are separated by a decoder 202 20 following analog to digital conversion. The decoder 202 is a finite impulse response filter used as a correlator.
The decoder 202 may be implemented with a digital signal processing chip available from Analog Devices, Texas Instruments Inc., and other manufacturers. In the 25 illustrative embodiment, the decoder 202 includes eight conventional finite impulse response (FIR~ matched ~ilters (not shown), each of which is driven by one of the orthogonal waveforms from the encoder 170. In particular, the encoder 170 impresses identical voltage 30 waveforms on the line 172 and on a first decoder line 204, on the line 174 and on a second decoder line 206, on the line 176 and on a third decoder line 208, and on the line 178 and on a fourth decoder line 210. Each decoder line 204-210 is coupled to one of a first set of four 35 matched filters and to one of a second set of four - 12 205C~6;~
matched filters deployed in the decoder 202.
Alternatively, the decoder 202 may digitally generate a set of orthogonal waveforms to substitute for the waveforms present on the lines 204, 206, 208 and 210.
The first A/D output line 199 is coupled to each filter within the first set of matched filters, while the second A/D output line 201 is connected to each filter within the second set of matched filters. In this manner, the sampled I components are processed by each filter within the first set of matched filters, and the sampled Q components are processed by each f ilter within the second set of matched filters. The matched filters coupled to the first decoder line 204 are disposed to extract the sampled I and Q components associated with the first input signal ~generated by the first array element 112 ) by mixing therewith the f irst voltage waveform. Similarly, the matched filters coupled to the lines 206-210 respectively extract the sampled I and Q
components associated with the input signals from the array elements 114-118. As shown in Fig. 2, the sampled I components derived from the first, second, third and fourth input signals are impressed on first, second, third, and fourth decoder output lines 212, 214, 216, and 218. Similarly, the sampled Q components derived from the first, second, third and fourth input signals are impressed oii fifth, sixth, seventh, and eighth decoder output lines 220, 222, 224, and 226.
The decoder output lines 212-226 from the first subnetwork 120, along with decoder output lines from decoders included within the remaining subnetworks (not shown) of the network loO, supply the beam-former 130 with quantized baseband I and Q components of the input signals originating within the array 110. Again, the beam-former 130 includes a digital computer or special purpose processor for utilizing the sampled I and Q
components supplied thereto to generate one or more beams B.
As mentioned above, the clock rate of the encoder 170 is chosen to be at least large as the magnitude of 5 the sum of the fre~uency bandwidths of the amplif ied input signals present on the lines 152-158. The noise floor seen by the A/D converters 198, 200 may be further raised by increasing the clock rate of the encoder 170, as this has the effect of augmenting the effective noise 10 bandwidth. Accordingly, in operational environments wherein strong signals (jammers) are present, the encoder clock rate may be increased to dynamically raise the noise floor - thereby reducing the n.ot~C~:~ry A/D dynamic range. Reciprocal reductions in the clocX rate of the 15 encoder 170 would be appropriate in relatively jammer-free environments.
Similarly, the operational environment influences the degradation in signal-to-noise ratio (SNR) arising from reductions in the number of bits utilized in the 20 analog to digital conversion process. For example, in an environment dominated by Gaussian noise a one bit A/D
converter will generally induce approximately a 2 . 8 dB
reduction in the SNR resulting from utilization of a six bit A/D converter. In this instance the A/D sampling 25 rate could be correspondingly increased to maintain a constant SNR.
Thus the present invention has been described with reference to a particular em~odiment in connection with a particular application. Those having ordinary skill in 30 the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. For example, the invention is not limited to subnetworks addressed by any particular number of antenna array elements. The 35 invention is further not limited to the specific mode of 14 .X05~63~:
orthogonally coaing the phase of the input signals.
Those skilled in the art may be aware of other t~rhniq~Pc for orthogonally coding the set of input signals such that each signal may serve as a noise source for adj acent 5 channels, and yet be separated therefrom by a decoding net~rork. Iqoreover, the scope of the present invention is not constrained by the particular scheme disclosed herein for converting the set of input signals into sampled I
and Q se~uences. It is therefore contemplated by the 10 appended claims to cover any and all such modifications.
.
In a specific embodiment, the pre3ent invention ;nf~ 1P~ an orthogonal encoder circuit for generating a 8et of N orthogonal voltage waveform3. A 3et of biphase modulator3 ---A~ tPI~ the pha3e of each of the input signals in re8ponse to one of the orthogonal voltage waveforms, thereby generating a 3et of N phase modulated input 3ignals. The N phase modulated input 3ignal3 are combined within an adder to form a compo3ite input 3ignal. The inventive network further include3 a downconverting mixer for generating an IF input 3ignal in respon3e to the compo3ite input signal.
The IF input 3ignal is then 3eparated into ba3eband in-pha3e and guadrature-pha3e .:, . nt~ by an I/Q 3plit network. A pair of A/D converters then sample the in-phase and quadrature-phase cl _ ~nPntFl o~ the input 3ignals. A decoder, coupled to the orthogonal encoder circuit, provides decoded digital in-phase 3ignal3 and decoded digital quadrature phase signals in response to the digital in-phase and quadrature-phase signals. The present invention further ;n~l~]~ a digital beam-former for generating the output beam by llt;1;7;ng the decoded in-phase and guadrature-phase signals.
Other aspects of this invention are as follow3:
A method of generating an output beam in response to a set of N input signal3, said set of input 3ignals being provided by an antenna array having N element3 upon which is incident an electromagnetic wavef ront of a first carrier ~requency, said method including the 3tep3 of:
-3a- 20~632 a) limiting the dynamic range of said input signal~;
b) digitizing the range limited input signals;
and c) îorming an output beam based on the digitized range limited input signals.
A digital beam forming network for generating an output beam in response to a set of N input signals, said set of input signals being provided by an antenna array having N ~1., t~: upon which is incident an electromagnetic wavefront of a first carrier requency, comprising:
an encoder for generating a set of N orthogonal voltage waveforms;
a biphase modulator f or modulating the phase o each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
an adder f or combining said ~ phase modulated input signals to ~orm a composite input signal;
a downconverter for generating an IF input signal in re3ponse to said composite input signal;
a converter or converting said IF input signal into baseband in-phase and quadrature-phase components;
a digital converter f or converting said in-phase and quadrature-phase components to digital in-phase and digital quadrature-phase signals;
a decoder, coupled to said orthogonal encoder, for providing N decoded digital in-phase signals and N
D
3b 20~0632 decoded digital ~uadrature phase signals in response to said digital in-phase and ~lUCld~ UL~, phase 6ignals; and a dig$tal beam former for generating said output beam by utilizing said decoded in-phase and quadL~lLu~e phase signals .
A tD~hn;~lD for forming an output beam in ~e:~y~
to a set of N input signals, said set of input signals being provided by an antenna array having N elements upon which is ~n~ ~dDnt an eleeL. _ ~ic wavefront of a first carrier fre~uency, comprising the steps of:
a) generating an set of N C1~ A1 voltage waveforms:
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into bsl__h~nS
in-phase and quadrature-phase - A -ts;
f) sampling said in-phase and quadL~.Lul. phase L~ to create N digital in-phase and N digital quacl.~Lu~. yl~ase signals;
g) multiplying each of said or~hoj~AnAl voltage w~ve~r~ with one of said N digital in-phase signals and one of said N digital quad~.lLu~a pllase signals in order to provide N decoded digital in-phase signals and N
decoded digital ~ulld~ u-~ phase signals; and h) generating said output beam by utilizing said decoded in-phase and quad...Lu.- phase signals.
A digital beam forming c,uL--et ~ for driving a digital beam former in re"y~ ..t,e to a set of N input ~iignals, said set of input signal5 being provided by N
elements of an antenna array upon which is incident an 3c 2~50632 ele~LL. ~lletic wavefront of a Pirst carrier frequency, comprising:
orth~qonAl encoder means for generating a set of N
orthogonal voltage waveform5;
biphase modulator mean# for modulating the phase of each of said input signals in r~ u~,Jc to one of said orthf~gonAl voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals to form a composite input signal;
d. ..l~aUIl~:L LeL means for generating an IF input signal in res~ c to said composite input signal;
means for converting said IF input signal into bA~hAnrl in-phase and quadrature-phase _ ,-n~nts;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quad.cl~uLe phc.se signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadL~LuL~ phase signals to said digital beam former in response to sald dlgltal ln-phase and qUalL-lLUL~ phase signals.
A t~rhnique for driving a digital beam former in respûnse to a set Or N input slgnals, said set of input signals being provided by N elements of an antenna array upon which is lncldent an ele. Ll- gnetlc wavefront of a first carrier rrequency, comprisinq the steps of:
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in r~u~ e to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
3d 2050632 e) converting said IF input signal into hAc~.hAn~
in-phase and quadLa~uL~ phase ~ _ ts;
r) - l; n'J said in-phase and quadrature-phase ~ to create digital in-phase and digital ~u- 1L~ILUL~ ase signals: and g) multiplying each of said ~Ll ~'O~ IA1 voltage waveforms with one of said digital in-phase signals and one of said digital qualL~uL~ phase signals in order to provide decoded digital in-phase signals and decoded digital quadrature phase signals to said beam former, A digital beam forming subnetwork for driving a digital beam former in response to a set of N input signals, said set of input signals being provided by N
elements of an antenna array upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising:
orthogonal encoder means for generating a set of N
orthogonal voltage waveforms;
oiphase modulator means for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals to form a composite input signal;
downconverter means f or generating an IF input signal in response to said composite input signal;
means for converting said IF input ~ignal into b~C~h~n~l in-phase and quadrature-phase c -~ts;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadrature-phase signals to said digital beam former in response to said digital in-phase and quadrature-phase siynals.
- 3e - 2~0~32 BRIEF D~S~c~ ON OF THE DRAWINGS
Fig. 1 is a block diagrammatic representation of a simplified ~mho~iir-~lt of the digital beam-forming network ~ 205~632 of the present invention.
Fig. 2 is a block diagrammatic representation of a preferred emoodiment of the digital beam-forming network of the present invention.
rr~Trrn DESCRIPTION OF T}iE INVENTION
Fig. l is a block diagrammatic representation of a simplified embodiment of the digital beam-forming network 10 of the present invention. The beam-forming network 10 accepts a set of M input signals on N input signal lines 12 from a receive antenna array 14 having N elements 16.
1~ The input signals on the lines 12 are generated by electromagnetic wavefronts incident on the receive array 14 and share a common high frequency carrier (e.g.
microwave). The inventive network 10 is disposed to generate one or more electromagnetic beams B in response 20 to the high frequency input signals impressed on the lines 12. The beam B may then be routed to, for example, a digital processing network (not shown).
As noted in the Background of the Invention, A/D
converters employed in conventional beam-forming networXs 25 require a relatively large number of bits as a result of _he dynamic range of the signals processed thereby. The necessary dynamic range is de~m;nr~d on the basis of the power level difference between the strongest anticipated communication or ~amming signal and the thermal noise 30 floor. Speci~ically, a 40 ds dynamic range requires an A/D converter having approximately 7 to 8 bits. As discussed more fully below, the inventive beam-forming network 10 is operative to inject band-limited noise into the ~igh frequency input signals originating within the 35 array 14 in order to raise the noise floor and thus 5 ~5~163~
decrease the dynamic range neces6ary in the analog to digital conversion process. This engineerea decrease in dynamic range enables A/D converters within the network 10 to func~ion using fewer bits, which reduces power requirements, cost, and complexity. ~n certain instances the inventive beam-forming network 10 may require A/D
converters having as few as one to three bits. The injected noise is substantially precluded from b~-nm;n~
aliased into the signal band during the analog-to-digital conversion process by sampling at a sufficiently high rate .
The digital beam-forming network 10 includes a set of M low-noise amplifiers 18, with each amplifier 18 being coupled to an array element 16 by a signal line 12.
The amplifiers 18 each have ps~ h~n~ centered about the carrier frequency of the input signals present on the lines 12. The amplified high frequency input signals are then transmitted over a set of M amplifier output lines 20 to a set of M summation networks 22.
Each summation network 22 is addressed by an amplifier output line 20 and by one of a set of M noise sources 24. The noise sources 24 each contain a noise generator 26 and a bandpass filter 28. The passband of each filter 28 is ad~usted in response to the degree to which it is desired to raise the noise floor, or equivalently, to the degree to which it is desired to reduce the apparent dynamic range spanned by the amplified input signals present on the lines 20. The summation networks 22 thus launch the amplified input signals and band-limited noise onto downconverter input lines 30.
A set of M downconverting mixers 32, each coupled to one of the lines 30, convert the set of ~ high frequency input signals to a set of signals centered about an 35 intermediate frequency (IF) . A set of M local - ~ 20S~163~
oscillators 34 provide re~erence ~requencies for the mixers 32. The IF signals are impressed on mixer output lines 36 ana transmitted to a set of N conversion modules 38. Each module 38 includes circuitry for converting the IF signals into in-phase (I) and quadrature-phase (Q) baseband components. A pair of A/D converters within each conversion module 38 then digitize the I and Q
components by sampling each at a pr~ pt~rm;n~d rate. To prevent Nyquist-type ~1 iacin~ of the injected noise into the digital frequency spectra occupied by the sampled I
and Q components, the sampling rate is chosen to be at least twice the magnitude of the bandwidth of the injected noise. For example, a bandpass filter 28 defining a ~ z noise bandwidth would require an A/D
converter executing approximately 2 Mega samples/second in order to prevent aliasing.
The sampled I and Q components are provided to a digital beam-former 40 via a pair of conversion module output lines 42 and 44. The beam-former 40 typically includes a special purpose digital processor for arithmetically manipulating the sampled I and Q
components. As is well known, during each processor clock period the sampled I and Q components are processed to form one or more beams B. The beam-former 40 may also include digital band rejection filters having stopbands coincident with the p~qb~n~q of the filters 28. These band rej ection f ilters may be employed to prevent infiltration of injected noise into the beam B
notwithstanding sampling in excess of the Nyquist rate.
In this manner the inventive beam-forming network 10 is operative to temporarily inject band-limited noise into signals originating in elements of a receive array, thereby reducing the number of bits required in the A/D
conversion process.
Fig. 2 is a block diagrammatic representation of a 7 zoSQ63~
preferred embodiment of the digital beam-forming network 100 of the present invention. The network 100 is addressed by signals originating within a receive antenna array 110 under illumination by an electromagnetic wavefront. The receive array llo includes N antenna elements. Fig. 2 explicitly shows the first, second, third and fourth elements 112, 114, 116, 118 as well as the next to last and last elements N-l, N. The first four elements 112-118 are coupled to a first beam-forming subnetwork 120. In the embodiment of Fig. 2 the inventive beam-forming network loO includes N/4 subnetworks which together feed a digital beam-former 130. It is emphasized that the teachings of the present invention extend to subnetworks coupled to substantially any number of receiver array elements and that a subnetwork lZ0 having only four r h:: nnr~l S was selected for purposes of clarity.
The subnetwork 120 accepts first, second, third and fourth input signals generated by the first, second, third and fourth array elements 112-118 on first, second, third and fourth input signal lines 132-138. Again, the frequency of each of the input signals is centered about a high frequency carrier (e.g. microwave) equivalent to that of the wavefront incident on the array 110. The subnetwork 120 is operative to deliver sampled in-phase (I) and quadrature-phase (Q) components associated with the first, second, third and fourth input signals to the beam-former 130. The beam-former 130 generally includes a special-purpose digital processor and is driven by sampled I/Q signals from each of the N/4 subnetworks within the inventive network 100. The beam-former conventionally synthesizes one or more beams B in response to the I/Q signals supplied thereto. The information associated with each beam may then be routed to a separate processor (not shown) for further digital ~ 20S063~
processing .
As is discussed more fully below, the principle of utilizing noise injection as a means of reducing the required A/D converter dynamic range is also implemented in the preferred embodiment of Fig. 2. ~owever, auxiliary band-limited noise sources such as those described with reference to Fig. 1 will generally not be needed in the inventive network 100 of Fig. 2. Rather, reductions in the requisite A/D dynamic range are effectuated within each subnetwork by code-division multiplexing of the four channels thereof such that the noise floor of each channel is raised by the signals present on the re-~;n1n~ three ~-hAnn~1 c As shown in Fig. 2, the first, second, third and fourth input signals drive first, second, third and fourth low-noise amplifiers (LNA's) 142, 144, 146, 148.
~he LNA's 142-148 typically have substantially identical frequency passbands centered about the high-frequency carrier and are disposed to impress first, second, third and fourth amplified input signals on first, second, third and fourth amplifier output lines 152-158. The fre~uency spectra of each of the ampli~ied input signals may be further limited by coupling a hAn~rAc:c filter (not shown) to each of the LNA ' s .
The amplifier output lines 152-158 each feed a first port of f irst, second, third and fourth biphase modulators 162, 164, 166, 168. A second port of each of the biphase modulators 162-168 is coupled to a code-division multiplexing encoder 170 via first, second, third and fourth phase control lines 172-178. The encoder 170 is operative to supply a set of four orthogonal voltage waveforms to the biphase modulators 162-168 via the four phase control lines 172--178. ~he encoder 170 is operative at a known ciock rate and, during each clock cycle, impresses either a normalized ~' 20~0632 voltage of +l or -1 on each of the lines to the modulators 172-178. For example, the following set of orthogonal voltage square waves may be sent to the biphase modulators 162-168 over a particular four clock 5 cycle interval:
First waveform to f irst modulator: 1 1 1 -1 second waveform to second moaulator: 1 1 -1 Third waveform to third modulator: 1 -1 1 1 Fourth waveform to fourth modulator: -1 1 1 A normalized voltage of +1 present on a line 172-178 induces the modulator 162-168 coupled thereto to leave intact the phase of the amplified input signal present on the associated line 152-158. Alternatively, during clock cycles of the encoder 170 wherein a -1 normalized voltage is impressed on one of the lines 172-178, the modulator 162-168 coupled thereto inverts the phase of the amplified signal present on the associated line 152-158. In this manner, the biphase modulators 162-168 impress first, second, third and fourth orthogonally phase modulated signals on biphase modulator output lines 182', 184', 186' and 188'.
The encoder 170 includes a TTL square wave circuit for generating the set of orthogonal voltage waveforms transmitted by the lines 172-178. The clock rate of the encoder 170 is chosen to be at least large as the magnitude of the sum of the frequency bandwidths of the amplified input signals present on the lines 152-158.
For example, if the bandwidth of each the four LNA's 142-148 (or bandpass filters coupled thereto) is lMHz, then the minimum acceptable clock rate of the encoder 170 is 4MHz. The encoder 170 may be purchased off-the-shelf as a code generator.
The first, second, third and fourth orthogonally lo ~5063~
phase modulated slgnals are summed within a 4 :1 combiner 180. The combiner 180 impresses a composite phase modulated input signal on a combiner output line 182 coupled thereto. The composite input signal is then fed 5 to a first port of a downconverting mixer 184 coupled to the output line 182. A local oscillator 186 is connected to a second port of of the mixer 184. Since the carrier frequency of the composite input signal is known, the frequency of the local oscillator 186 is chosen such that 10 the carrier of the composite input signal is converted to a desired int~ te frequency (IF~. This composite IF
signal is then sent through a bandpass filter l90 via a mixer output line 188. The r~ccb~n~ of the filter 190 is centered about the IF fre~uency.
The bandpass filter 190 is coupled to an I/Q split network 192 through a filter output line 194. The I/Q
split network 192 includes a pair of synchronous baseband mixers for conventionally converting the composite IF
signal into in-phase (I) and quadrature-phase (Q) 20 components. The network 192 impresses the in-phase components on a first A/D input line 194, and impresses the quadrature-phase components on a second A/D input line 196. First and second A/D converters 198, 200 connected to the lines 194, 196 then sample the I and Q
25 components at a known sampling rate and launch the sampled I components on a first A/D output line 199 and launch the sampled Q components on a second A/D output line 201. It is observed that the subnetwork 120 included within the present invention re~uires only two 30 A/D converters, whereas conventional digital beam-forming networks generally utilize a pair of A/D converters for each antenna array element.
The minimum A/D sampling rate is determined by considering the baseband signal from which the I and Q
35 components are derived to be a set of four code-11 ZO5~6~
multiplexed signals, each having a noise bandwidthequivalent to the sum of the bandwidths of the input signals present on thQ lines 152-158 For example, if each LNA 142-148 has a bandwidth of approximately 1 MHz 5 then each code-multiplexed baseband signal may be treated as having a bandwidth of approximately 4 MHz.
Accordingly, to prevent Nyquist-type al i~c;n~ the minimum theoretically acceptable sampling rate would be 8 MHz -although in actual operation a slightly higher rate o~ 10 10 ~IHz would generally be utilized. The inventive network 100 is thus operative to reduce the requisite dynamic range of each of the A/D converters 198 and 200 by using three of the input signals to raise the noise ~loor accompanying the r ~;nin~ input signal. In this manner, 15 no external noise sources need be utilized, as in the case of the simplified embodiment of Fig. 1, in order to reduce the necessary A/D converter dynamic range.
In the embodiment of Fig. 2 the multiplexed baseband I and Q components are separated by a decoder 202 20 following analog to digital conversion. The decoder 202 is a finite impulse response filter used as a correlator.
The decoder 202 may be implemented with a digital signal processing chip available from Analog Devices, Texas Instruments Inc., and other manufacturers. In the 25 illustrative embodiment, the decoder 202 includes eight conventional finite impulse response (FIR~ matched ~ilters (not shown), each of which is driven by one of the orthogonal waveforms from the encoder 170. In particular, the encoder 170 impresses identical voltage 30 waveforms on the line 172 and on a first decoder line 204, on the line 174 and on a second decoder line 206, on the line 176 and on a third decoder line 208, and on the line 178 and on a fourth decoder line 210. Each decoder line 204-210 is coupled to one of a first set of four 35 matched filters and to one of a second set of four - 12 205C~6;~
matched filters deployed in the decoder 202.
Alternatively, the decoder 202 may digitally generate a set of orthogonal waveforms to substitute for the waveforms present on the lines 204, 206, 208 and 210.
The first A/D output line 199 is coupled to each filter within the first set of matched filters, while the second A/D output line 201 is connected to each filter within the second set of matched filters. In this manner, the sampled I components are processed by each filter within the first set of matched filters, and the sampled Q components are processed by each f ilter within the second set of matched filters. The matched filters coupled to the first decoder line 204 are disposed to extract the sampled I and Q components associated with the first input signal ~generated by the first array element 112 ) by mixing therewith the f irst voltage waveform. Similarly, the matched filters coupled to the lines 206-210 respectively extract the sampled I and Q
components associated with the input signals from the array elements 114-118. As shown in Fig. 2, the sampled I components derived from the first, second, third and fourth input signals are impressed on first, second, third, and fourth decoder output lines 212, 214, 216, and 218. Similarly, the sampled Q components derived from the first, second, third and fourth input signals are impressed oii fifth, sixth, seventh, and eighth decoder output lines 220, 222, 224, and 226.
The decoder output lines 212-226 from the first subnetwork 120, along with decoder output lines from decoders included within the remaining subnetworks (not shown) of the network loO, supply the beam-former 130 with quantized baseband I and Q components of the input signals originating within the array 110. Again, the beam-former 130 includes a digital computer or special purpose processor for utilizing the sampled I and Q
components supplied thereto to generate one or more beams B.
As mentioned above, the clock rate of the encoder 170 is chosen to be at least large as the magnitude of 5 the sum of the fre~uency bandwidths of the amplif ied input signals present on the lines 152-158. The noise floor seen by the A/D converters 198, 200 may be further raised by increasing the clock rate of the encoder 170, as this has the effect of augmenting the effective noise 10 bandwidth. Accordingly, in operational environments wherein strong signals (jammers) are present, the encoder clock rate may be increased to dynamically raise the noise floor - thereby reducing the n.ot~C~:~ry A/D dynamic range. Reciprocal reductions in the clocX rate of the 15 encoder 170 would be appropriate in relatively jammer-free environments.
Similarly, the operational environment influences the degradation in signal-to-noise ratio (SNR) arising from reductions in the number of bits utilized in the 20 analog to digital conversion process. For example, in an environment dominated by Gaussian noise a one bit A/D
converter will generally induce approximately a 2 . 8 dB
reduction in the SNR resulting from utilization of a six bit A/D converter. In this instance the A/D sampling 25 rate could be correspondingly increased to maintain a constant SNR.
Thus the present invention has been described with reference to a particular em~odiment in connection with a particular application. Those having ordinary skill in 30 the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. For example, the invention is not limited to subnetworks addressed by any particular number of antenna array elements. The 35 invention is further not limited to the specific mode of 14 .X05~63~:
orthogonally coaing the phase of the input signals.
Those skilled in the art may be aware of other t~rhniq~Pc for orthogonally coding the set of input signals such that each signal may serve as a noise source for adj acent 5 channels, and yet be separated therefrom by a decoding net~rork. Iqoreover, the scope of the present invention is not constrained by the particular scheme disclosed herein for converting the set of input signals into sampled I
and Q se~uences. It is therefore contemplated by the 10 appended claims to cover any and all such modifications.
.
Claims (17)
1. A digital beam forming network for generating an output beam in response to a set of N input signals, said set of input signals being provided by an antenna array having N elements upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising:
an encoder for generating a set of N orthogonal voltage waveforms;
a biphase modulator for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
an adder for combining said N phase modulated input signal to form a composite input signal;
a downconverter for generating an IF input signal in response to said composite input signal;
a converter for converting said IF input signal into baseband in-phase and quadrature-phase components;
a digital converter for converting said in-phase and quadrature-phase components to digital in-phase and digital quadrature-phase signals;
a decoder, coupled to said orthogonal encoder, for providing N decoded digital in-phase signals and N
decoded digital quadrature phase signals in response to said digital in-phase and quadrature-phase signals; and a digital beam former for generating said output beam by utilizing said decoded in-phase and quadrature-phase signals.
an encoder for generating a set of N orthogonal voltage waveforms;
a biphase modulator for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
an adder for combining said N phase modulated input signal to form a composite input signal;
a downconverter for generating an IF input signal in response to said composite input signal;
a converter for converting said IF input signal into baseband in-phase and quadrature-phase components;
a digital converter for converting said in-phase and quadrature-phase components to digital in-phase and digital quadrature-phase signals;
a decoder, coupled to said orthogonal encoder, for providing N decoded digital in-phase signals and N
decoded digital quadrature phase signals in response to said digital in-phase and quadrature-phase signals; and a digital beam former for generating said output beam by utilizing said decoded in-phase and quadrature-phase signals.
2. The digital beam forming network of Claim 1 wherein said decoder includes a first set of N matched filters addressed by said N digital in-phase signals, and a - 1b -second set of N matched filters addressed by said N
quadrature-phase signals.
quadrature-phase signals.
3. The digital beam forming network of Claim 2 wherein each of said matched filters includes means for mixing one of said digital in-phase signals with one of said orthogonal voltage waveforms, and each of said second set of matched filters includes means for mixing one said digital quadrature-phase signals with one of said orthogonal voltage waveforms.
4. The digital beam forming network of Claim 1 wherein said orthogonal encoder includes a square wave circuit operative at a first clock rate.
5. The digital beam forming network of Claim 4 further including a set of N amplifiers for amplifying said N
input signals.
input signals.
6. The digital beam forming network of Claim 5 further including a set of N input bandpass filters of known frequency bandwidths wherein the sum of said bandwidths is of a magnitude not larger than the magnitude of said first clock rate, and wherein each of said input filter are coupled to one of said amplifiers.
7. The digital beam forming network of Claim 6 wherein said biphase modulator includes a set of N biphase modulators, one of said modulators being coupled to each of said input bandpass filters.
8. The digital beam forming network of Claim 6 wherein said digital converter includes a first and second analog to digital converters for sampling said in-phase and quadrature phase components, said first and second converters being disposed to operate at a sampling rate having a magnitude of at least twice the magnitude of said sum of filter bandwidths.
9. The digital beam forming network of Claim 1 wherein said downconverter includes:
a mixer having first, second and third ports with said first port being addressed by said composite input signals and a local oscillator of a second frequency coupled to said second port of said mixer.
a mixer having first, second and third ports with said first port being addressed by said composite input signals and a local oscillator of a second frequency coupled to said second port of said mixer.
10. The digital beam forming network of Claim 9 further including an intermediate frequency bandpass filter coupled to said third port of said mixer.
11. A technique forming an output beam in response to a set of N input signals, said set of input signals being provided by an antenna array having N elements upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising the steps of:
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into baseband in-phase and quadrature-phase components;
f ) sampling said in-phase and quadrature-phase components to create N digital in-phase and N
digital quadrature-phase signals;
g) multiplying each of said orthogonal voltage waveforms with one of said N digital in-phase signals and one of said N digital quadrature-phase signals in order to provide N decoded digital in-phase signals and N decoded digital quadrature-phase signals; and h) generating said output beam by utilizing said decoded in-phase and quadrature-phase signals.
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into baseband in-phase and quadrature-phase components;
f ) sampling said in-phase and quadrature-phase components to create N digital in-phase and N
digital quadrature-phase signals;
g) multiplying each of said orthogonal voltage waveforms with one of said N digital in-phase signals and one of said N digital quadrature-phase signals in order to provide N decoded digital in-phase signals and N decoded digital quadrature-phase signals; and h) generating said output beam by utilizing said decoded in-phase and quadrature-phase signals.
12. The technique of Claim 11 wherein said step of generating said set of orthogonal voltages is performed at a first clock rate.
13. The technique of Claim 12 further including the step of passing each of said N input signals through one of a set of N bandpass filters of known bandwidths wherein the sum of said known bandwidths is of a magnitude not larger than the magnitude of said first clock rate.
14. The technique of Claim 13 wherein said step of sampling is performed at a sampling rate having a magnitude of at least twice the magnitude of said sum of filter bandwidths.
15. The technique of Claim 12 further including the step of varying said first clock rate in order to vary the bandwidth of said composite input signal.
16. A digital beam forming subnetwork for driving a digital beam former in response to a set of N input signals, said set of input signals being provided by N
elements of an antenna array upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising:
orthogonal encoder means for generating a set of N
orthogonal voltage waveforms;
biphase modulator means for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals for form a composite input signal;
downconverter means for generating an IF input signal in response to said composite input signal;
means for converting said IF input signal into baseband in-phase and quadrature-phase components;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadrature-phase signals to said digital beam former in response to said digital in-phase and quadrature-phase signals.
elements of an antenna array upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising:
orthogonal encoder means for generating a set of N
orthogonal voltage waveforms;
biphase modulator means for modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
adder means for combining said N phase modulated input signals for form a composite input signal;
downconverter means for generating an IF input signal in response to said composite input signal;
means for converting said IF input signal into baseband in-phase and quadrature-phase components;
means for sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and decoder means, coupled to said orthogonal encoder means, for providing N decoded digital in-phase signals and N decoded digital quadrature-phase signals to said digital beam former in response to said digital in-phase and quadrature-phase signals.
17. A technique for driving a digital beam former in response to a set of N input signals, said set of input signals being provided by N elements of an antenna array upon which is incident an electromagnetic wavefront of a first carrier frequency, comprising the steps of:
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into baseband in-phase and quadrature-phase components;
f) sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and g) multiplying each of said orthogonal voltage waveforms with one of said digital in-phase signals and one of said digital quadrature-phase signals in order to provide decoded digital in-phase signals and decoded digital quadrature phase signals to said beam former.
a) generating a set of N orthogonal voltage waveforms;
b) modulating the phase of each of said input signals in response to one of said orthogonal voltage waveforms thereby generating a set of N phase modulated input signals;
c) adding said N phase modulated input signals to form a composite input signal;
d) generating an IF input signal in response to said composite input signal;
e) converting said IF input signal into baseband in-phase and quadrature-phase components;
f) sampling said in-phase and quadrature-phase components to create digital in-phase and digital quadrature-phase signals; and g) multiplying each of said orthogonal voltage waveforms with one of said digital in-phase signals and one of said digital quadrature-phase signals in order to provide decoded digital in-phase signals and decoded digital quadrature phase signals to said beam former.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/632,846 US5077562A (en) | 1990-12-24 | 1990-12-24 | Digital beam-forming technique using temporary noise injection |
| US632,846 | 1990-12-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2050632A1 CA2050632A1 (en) | 1992-06-25 |
| CA2050632C true CA2050632C (en) | 1996-09-10 |
Family
ID=24537192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002050632A Expired - Fee Related CA2050632C (en) | 1990-12-24 | 1991-09-04 | Digital beam-forming technique using temporary noise injection |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5077562A (en) |
| EP (1) | EP0492821B1 (en) |
| JP (1) | JP2843457B2 (en) |
| AU (1) | AU647854B2 (en) |
| CA (1) | CA2050632C (en) |
| DE (1) | DE69126291T2 (en) |
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-
1990
- 1990-12-24 US US07/632,846 patent/US5077562A/en not_active Expired - Lifetime
-
1991
- 1991-09-04 CA CA002050632A patent/CA2050632C/en not_active Expired - Fee Related
- 1991-12-02 EP EP91311181A patent/EP0492821B1/en not_active Expired - Lifetime
- 1991-12-02 DE DE69126291T patent/DE69126291T2/en not_active Expired - Fee Related
- 1991-12-19 AU AU89933/91A patent/AU647854B2/en not_active Ceased
- 1991-12-24 JP JP3341448A patent/JP2843457B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA2050632A1 (en) | 1992-06-25 |
| DE69126291D1 (en) | 1997-07-03 |
| DE69126291T2 (en) | 1998-01-08 |
| AU647854B2 (en) | 1994-03-31 |
| US5077562A (en) | 1991-12-31 |
| JPH04296684A (en) | 1992-10-21 |
| EP0492821A3 (en) | 1992-10-07 |
| AU8993391A (en) | 1992-07-02 |
| EP0492821A2 (en) | 1992-07-01 |
| EP0492821B1 (en) | 1997-05-28 |
| JP2843457B2 (en) | 1999-01-06 |
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