KR100210633B1 - Multiple access up converter/modulator and method - Google Patents

Abstract

The multiple access digital up-converter / modulator includes selectors 1606, 1608 having inputs 1602, 1604 and outputs coupled to first and second interpolation filters 1610, 1626. An output of the first interpolation filter is selectively connected to the first mixer 1612 and the first adder 1622, the first adder also receiving a first phase value, the output of which is coupled to the first phase accumulator 1616. Coupled, the output of the first phase accumulator is coupled to a first sinusoidal generator 1614 and optionally coupled to a second sinusoidal generator 1630. Each output of the first and second mixers is selectively connected to an output adder 1634 and inputs of the first and second mixers. An output of the second interpolation filter 1626 is selectively connected to a second mixer 1628 and a second adder 1638, the second adder also receiving a second phase value, the output of which is a second phase accumulator ( 1640, the output of this second phase accumulator is optionally connected to a second sinusoidal generator.

Description

Up-conversion / modulation device and method, multi-access digital transmitter

Transmitters and receivers in communication systems typically have a wide variety of bandwidths and are designed to transmit and receive one of a number of signals that may be within a particular frequency range. Those skilled in the art will readily appreciate that these transmitters and receivers each emit or block electromagnetic radiation within a desired frequency band. Each transmitter and receiver may output or input electromagnetic radiation by several types of devices, including antennas, waveguides, coaxial cables and optical fibers.

Transmitters and receivers of these communication systems can transmit and receive multiple signals. However, such transmitters and receivers typically use circuits having different frequencies or bandwidths and duplicated for each signal being transmitted or received. This circuit duplication is not an optimal multichannel communication device design architecture because of the added cost and complexity associated with manufacturing a completely independent transmitter and / or receiver for each communication channel.

Another transmitter and receiver architecture is possible that can transmit and receive signals having a desired multi-channel wide bandwidth. This further structure of transmitters and receivers will use digitizers (eg, analog-to-digital converters) that operate at sufficiently high sampling rates to ensure that signals of the desired bandwidth can be digitized according to the Nyquist criteria. (Eg, digitizing at a sampling rate equal to at least twice the bandwidth). Subsequently, the digitalized signal is preferably preprocessed or subsequently processed using digital signal processing techniques to distinguish between multiple channels within the digitalized bandwidth.

1 shows a conventional broadband transceiver 100. A radio frequency (RF) signal is received at the antenna 102, processed through the RF converter 104, and then digitalized by the analog-to-digital converter 106. This digital signal is processed through discrete Fourier transform (DFT) 108, channel processor 110, and then transmitted from channel processor 110 to a cellular network and a public switched telephone network (PSTN). In transmission mode, signals received from the cellular network are processed through channel processor 110, inverse discrete Fourier transform (IDFT) 114, and digital-to-analog converter 116. The analog signal from the digital to analog converter 116 is up converted in the RF up converter 118 and radiated from the antenna 120.

A disadvantage of this other type of communication device is that the digital processing unit of the communication device is added to ensure that the Nyquist standard is satisfied for the maximum bandwidth of the received electromagnetic radiation equal to the sum of the individual communication channels forming the received composite electromagnetic radiation bandwidth. It must have a sufficiently high sampling rate. If the composite bandwidth signal is wide enough, the digital processing portion of the communication device is quite expensive and consumes a significant amount of power. In addition, the channels generated by the DFT or IDFT filtering techniques will typically be adjacent to each other.

As described above, there is a need for a transmitter and receiver capable of transmitting and receiving multiple signals in corresponding channels with the same transmitter or receiver circuitry. However, this transmitter and receiver circuit should preferably reduce the communication device design constraints associated with the transceiver structure described above. If such a transmitter and receiver structure could be developed, it would be ideally suited for cellular radiotelephone communication systems. Cellular base stations typically need to transmit and receive multiple channels within a wide frequency band (eg, 824 MHz to 894 MHz). In addition, due to the commercial pressure of cellular infrastructure and subscriber equipment manufacturers, these manufacturers have been studying ways to reduce the cost of communication devices. Similarly, this multi-channel transmitter and receiver architecture is well suited for personal communication systems (PCSs), which are smaller service areas (than their relative cellular service area) for each base station, and for that reason, to cover a given geographic area, More corresponding base stations will be needed. Operators that purchase base stations will hope to be less complex and less expensive to install across their authorized service area.

Additional advantages are achieved by designing multi-channel communication devices in which cellular and PCS manufacturers share the same analog signal processor. Conventional communication devices are designed to operate under a single information signal coding and channelization standard. In contrast, these multi-channel communication devices include digital signal processors which can be reprogrammed on purpose in the field after installation or via software during the manufacturing process, so that these multi-channel communication devices have several information signal coding and channeling standards. It can work according to one of these.

Another drawback of conventional communication system designs is that the hardware associated with the communication system is typically a single access method (i.e., advanced mobile phone service (AMPS), narrowband AMPS (NAMPS), United States digital cellular (USDC), personal digital cellular ( PDC) and its equivalent communication access method). Access to a communication system through multiple access, i.e., one of the access methods, requires significant hardware duplication and significant cost. Accordingly, there is a need for a communication system that provides multiple accesses without significantly increasing the amount of hardware required and the associated costs.

Numerous advantages and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

FIELD OF THE INVENTION The present invention relates to communication system transceivers and, more particularly, to multiple access digital up converters / modulators for use in communication system transceivers.

1 is a block diagram of a conventional multi-channel transceiver.

2 is a block diagram of a multi-channel receiver in accordance with a preferred embodiment of the present invention.

3 is a block diagram of a multi-channel transmitter in accordance with a preferred embodiment of the present invention.

4 is a block diagram of a multi-channel transceiver in accordance with a preferred embodiment of the present invention.

5 is a block diagram modified in such a way that the multi-channel receiver shown in FIG. 2 provides per-channel scanning in accordance with another preferred embodiment of the present invention.

6 is a block diagram of a multi-channel transceiver according to another preferred embodiment of the present invention.

7 is a block diagram of a multi-channel transceiver according to another preferred embodiment of the present invention.

8 is a block diagram illustrating a data path in a multichannel transceiver in accordance with a preferred embodiment of the present invention.

9 is a block diagram illustrating a data path in a multi-channel transceiver according to another preferred embodiment of the present invention.

10 is a block diagram illustrating data paths in a multi-channel transceiver according to another preferred embodiment of the present invention.

11 is a block diagram of a digital converter module for a multi-channel transceiver in accordance with the preferred embodiment of the present invention.

12 is a block diagram of a preferred embodiment of a digital down converter according to the present invention.

13 is a block diagram of a preferred embodiment of a digital up converter in accordance with the present invention.

14 is a block diagram of an up converter suitable for the digital up converter of the present invention.

Figure 15 is a block diagram of a modulator suitable for the digital up converter of the present invention.

16 is a block diagram of a preferred embodiment of an up converter / modulator for the digital up converter of the present invention.

Figure 17 is a block diagram of a preferred embodiment of a channel processor card in accordance with the present invention.

18 is a block diagram of another preferred embodiment of a channel processor card in accordance with the present invention.

19 is a flow chart showing a scanning procedure according to a preferred embodiment of the present invention.

The present invention relates to a wideband multi-channel transmitter and receiver (transceiver), which has high flexibility and redundancy and is particularly suitable for cellular or PCS communication systems. This transceiver provides multiple antennas with a combination of these characteristics with enhanced cellular operation, diversity acceptance, redundancy or improved user capability, preferably at reduced cost. The transceiver of the present invention achieves these and other features through a practical architecture that enhances performance through inherent digital processing and dynamic equipment sharing (DES).

In addition, the present invention provides multiple accesses without hardware duplication. The transceiver according to the invention uses a programmable digital down converter (DDC) and a programmable digital up converter (DUC). That is, each of the DUCs and DDCs can be programmed to provide various decimation / interpolation ratios to accommodate access methods with various signal formats and bandwidths. However, the programmability of the DUC does not fully provide multiple access. Thus, the DUC of the present invention also uses a unique hardware architecture that provides both frequency modulation (FM) and quadrature (I and Q) up conversion without significant hardware duplication and associated costs.

4 shows a transceiver 400 according to a preferred embodiment of the present invention. For ease of explanation, preferred embodiments of the wideband multi-channel digital receiver and transmitter 200, 300 of the transceiver 400 will be described, respectively. In addition, for a preferred implementation of the present invention, the transceiver is considered to operate in the cellular radio frequency (RF) band. However, it will be appreciated that the present invention can be readily applied to service any RF communication band, including, for example, PCS and other bands.

2 shows a wideband multi-channel digital receiver (receiver) 200 in accordance with a preferred embodiment of the present invention. Receiver 200 includes a number of antennas 202 (individually antennas 1, 3,..., N-1), each of which comprises an RF signal received at antenna 202 for an intermediate frequency (IF) signal. Is connected to a number of radio frequency mixers 204 that convert to. The mixer 204 includes at least suitable signal processing elements including filters, amplifiers, and oscillators to precondition the received RF signal, isolate the particular RF band of interest, and apply the RF signal to the desired IF signal. It should be understood that mixing them.

The IF signal is then sent to a number of analog-to-digital converters (ADCs) 210, where the entire band of interest is digitized. One of the disadvantages of conventional broadband receivers is that the ADC must operate at a fairly high sampling rate in order to fully and accurately digitize the entire band. For example, the cellular A and B bands occupy 25 MHz of the RF spectrum. According to known Nyquist standards, to accurately digitize the entire cellular band with a single ADC, the device must be capable of operating at a sampling rate higher than 50 MHz (or 50 Ms / s, Ms / s = million samples per second). do. Such devices have become increasingly common, which have been considered for using the latest ADC technology within the scope of the present invention. However, U.S. Patent Application, Co., Ltd., Split Frequency Band Signal Digitizer and Method of Smith et al. And Wideband Frequency Signal Digitizer and Method of Elder et al. An apparatus and method are disclosed for fully and accurately digitizing a wideband frequency signal using an operating ADC. The ADC 210 digitalizes the IF signal to generate a digital signal. These digital signals are then sent to a digital down converter (DDC) 214.

The DDC 214 of the preferred embodiment, shown in detail in FIG. 12, includes a switch 1216 to select an IF signal from one of the plurality of antennas 202. Based on the state of the switch 1216, the DDC 214 uses a high speed digital word string (eg, from the ADC 210 associated with the antenna selected in the preferred embodiment via a backplane interconnect 1108 (FIG. 11)). For example, approximately 60 MHz). The DDC 214 is operable to select a particular frequency (in the digital domain), thus providing decimation (rate reduction) and filtering the signal to the bandwidth associated with the channel of the communication system. Referring to FIG. 12, each DDC 214 includes a numerically controlled oscillator (NCO) 1218 and a complex multiplier 1220 to perform down conversion on a digital word string. Note that this was the second down conversion since the first down conversion was performed on the analog signal received by the mixer 204. The result of down conversion and complex multiplication is a data string that is a sphere with I (in-phase) and Q (quadrature) components spectrally shifted to a center frequency (baseband or 0 IF) of 0 Hz. The I and Q components of the data string are each sent to a pair of decimation filters 1222 to reduce the bandwidth and data rate at a rate that is appropriate for the particular communications system common air interface (CAI) being processed. In a preferred embodiment, the data rate output of the decimation filter is about 2.5 times the desired CAI bandwidth. It should be appreciated that the desired bandwidth can change the desired decimation filter 1224 output rate. The decimated data string is then low-pass filtered through digital filter 1224 to remove unwanted alias components. The decimation filter 1222 and the digital filter 1224 provide rough selectivity, with the final selectivity being achieved in the channel processor 228 in a known manner.

Referring to FIG. 2, a preferred embodiment is provided with a number of DDCs 214 interconnected to the ADC 210, respectively. Each DDC 214 may select one of a plurality of ADCs 210 / antennas 202 to receive high-speed digital word strings through the backplane 1106. The output of the DDC 214, low-speed data stream (e.g., approximately 10 MHz, baseband signal) is coupled to a time domain multiplexed (TDM) bus 226, through the output formatter 1232, to multiple channel processors. 228 is sent. By placing the DDC output on the TDM bus 226, one of the channel processors 228 may select one of the DDCs 214 to receive the baseband signal. If channel processor 228 or DDC 214 fails, channel processor 228 operates over control bus 224 and control bus interface 1234 to provide a channel processor that can be used with appropriate contention / mediation processing. By interconnecting to an available DDC, two channel processors can be prevented from accessing the same DDC. However, in the preferred embodiment, the DDC 214 is assigned a dedicated time slot on the TDM bus 226 for interconnecting the particular channel processor 228.

The channel processor 228 transmits a control signal to the DDC 214 via the control bus 224 to set digital word string processing parameters. That is, channel processor 228 may instruct DDC 214 to select the down conversion frequency, decimation rate, and filter characteristics (eg, bandwidth type, etc.) to process the digital data stream. NCO 1218, complex multiplier 1220, decimator 1222, and digital filter 1224 change the signal processing parameters in response to numerical control. This allows the receiver 200 to receive communication signals that conform to a number of different air interface standards.

With continued reference to FIG. 2, the receiver of the present invention also provides a plurality of receiver banks 230, 230 '. Each receiver bank 230 and 230'includes the aforementioned elements prior to the TDM bus 226 for receiving and processing radio frequency signals. For the diversity of the invention, one antenna from antenna 202 and one antenna from antenna 202 ', each associated with receiver banks 230 and 230' (see separately 2, 4,..., N). A pair of adjacent antennas is designed to serve the area of the communication system. The signals received at each antenna 202 and 202 'are processed independently through receiver banks 230 and 230'. Although one bus may be used for the channel processor 228, the outputs of the receiver banks 230 and 230 'may be transmitted on the TDM buses 226 and 226', respectively, to obtain diversity.

The channel processor 228 receives the baseband signal and performs the necessary baseband signal processing and selectivity to recover the communication channel. This process receives at least audio filtering in an analog CAI communication system, forward error correction in a digital CAI communication system, and a receive signal strength indication (RSSI) in all communication systems. Each channel processor 228 independently restores the traffic channel. In addition, to provide versatility, each channel processor 228 listens on each of the antenna pairs assigned to one sector and receives and processes two baseband signals, one per antenna. Channel processor 228 provides the interface 436 of FIG. 4 to a communication network, e.g., a cellular communication system, through a suitable interconnection to a base station or mobile switching center.

Referring to FIG. 17, a preferred embodiment of channel processor 228 is shown. As described below, each channel processor is operable in both transmit and receive operations. In a preferred embodiment, each channel processor 228 may service up to eight communication channels of the communication system (4 in diversity mode in receive mode) at the time of transmission and reception. Slow base station signals from TDM buses 226 and 226 'are received at input / output (I / O) ports 1740 and 1740', respectively, and sent to a pair of processors 1742 and 1742 '. Each processor 1742, 1742 ′ is associated with a digital signal processor (DSP) 1744, 1744 ′ and memory 1746, 1746 ′. Each processor 1742, 1742 ′ may serve four communication channels. As can be seen from the preferred embodiment of FIG. 17, the processors 1742, 1742 ′ are configured to listen to one or both of the receiver banks 230, 230 ′ as needed for the desired diversity arrangement. This structure enables diversity and at the same time provides redundancy. In receive mode, if one of the processors 1742 or 1742 'fails, the other processor 1742 or processor 1742' can still process the uplink baseband signal from the other receiver bank. Only diversity is lost. It should be appreciated that the processors 1742, 1742 ′ may be implemented with appropriate diversity selection or diversity combining processing power. Processors 1742, 1742 'also communicate with control elements 1748, 1748', respectively, to process and send control information to DDC 214 via I / O ports 1740, 1740 '.

With continued reference to FIG. 17, reference is made to FIG. 4, where the transmitter 300 (transmitter) of the transceiver 400 is shown. In transmit mode, channel processor 228 receives downline communication signals from the communication system network (via interface 436 not shown in FIG. 17) to communicate over the communication channel. These downlink signals are, for example, control or signaling information directed to the entire cell (e.g., page message) or to a particular area of the cell (e.g., handoff command) or downlink voice. And / or data (eg, traffic channels). Processors 1742, 1742 'in channel processor 228 operate independently on downlink signals, generating a low speed baseband signal. In transmission mode, channel processor 228 may service eight communication channels (traffic channels, signaling channels, or a combination thereof). If one of the processors 1742 or 1174 'fails, there is a loss of capability on the system but no loss of complete area or cell. In addition, removing one of the multiple channel processors 228 from the communication system results in only eight channels being lost.

The processing of the baseband signal through the transmitter 300 is complementary to the processing completed at the receiver 200. Although a single bus may be used, low speed baseband signals are transmitted from the channel processor 228 to the TDM white line buses 300 and 300 'via the I / O port 1740 or I / O port 1740'. Then, it is sent to a number of digital up converters (DUCs) 302. The DUC 302 interpolates the baseband signal at an appropriate data rate. All baseband signals from channel processor 228 need to be interpolated to ensure that they have the same rate so that the baseband signals can be summed at the center position. The interpolated baseband signal is then upconverted to an appropriate IF signal such as quadrature phase shift keying (QPSK), differential QPSK (DQPSK), frequency modulated (FM) or amplitude modulated (AM) signal (I, Q inputs). And modulation is accomplished within channel processor 228). The baseband signal is now a carrier modulated high speed baseband data signal offset from 0 Hz. The offset amount is controlled by the programming of the DUC 302. The modulated baseband signal is sent to the signal selector 306 over the high speed backplane interconnect 304. The signal selector selects a subgroup of modulated baseband signals. The selected subgroup is a communication channel transmitted within a specific zone of the communication system. The selected modulated baseband signal subgroups are then sent to digital summer 308 and summed. The still high speed aggregated signal is then transmitted to the digital-to-analog converter (DAC) 310 via the backplane interconnect 1130 and converted into an IF analog signal. These IF analog signals are then up converted by the up converter 314 into RF signals, amplified by the amplifier 418 (FIG. 4), and then radiated from the antenna 420 (FIG. 4).

In a preferred embodiment, in order to provide improved system reliability again, multiple DACs 310 are provided with a group 311 of three DACs placed on an RF shelf, one DAC one self. Related to. The DAC group 311 converts the three summed signals received on the individual signal buses 313 of the backplane interconnect 1130 into analog signals. This provides for increased dynamic range beyond what can be achieved with a single DAC. This arrangement also provides redundancy because if one of the DACs fails, another DAC is available. This result merely reduces system capacity and no overall area or cell is lost. The outputs of the group of DACs 311 that receive signals for the area of the communication system are then analog summed at summer 312 and the summed analog signals are sent to up converter 314.

Similar to the receiver 200, the transmitter 300 is also arranged in multiple transmitter banks (two shown as 330 and 330 ′). Transmitter banks 330 and 330 ′ include all the equipment for transmitter 300 between channel processor 228 and amplifier 418. For each transmitter bank 330, 330 ′, the output of up converter 314, which upconverts the summed analog signal for the region of the communication system, is summed in RF summer 316. The summed RF signal is transmitted to amplifier 418 and radiated at antenna 420. If the entire transmitter bank 330 or 330 'fails, only system capacity is still lost and there is no loss of the entire part of the communication system.

13 shows a DUC 302 according to a preferred embodiment of the present invention. In a preferred embodiment, a number of DUCs 302 are provided, each of which includes an up converter / modulator 1340 to receive downlink baseband signals from buses 300 and 300 'and control bus ( A control signal is received from the 224 through the formatter circuit 1341. The output of up converter / modulator 1340 is then sent to selector 306. In a preferred embodiment, the selector 306 can take the form of a dual input AND gate bank, with one input connected to one bit of a data word (ie, a modulated baseband signal). The control line remains high (logic 1), and the output follows the transition of the input. The output of the selector 306 is then sent to a digital summer bank 1308, where the digital summer bank transfers data from the previous digital summer associated with the other DUC into one of the plurality of signal paths 313. Add. Each signal path is associated with a zone of the communication system and sends a summation signal to the DAC group 311. When the selector 306 is opened, the output of the selector 306 becomes 0, and the signal input to the summer 1308 is not changed. It should also be noted that scaling is required on the input, output, or input / output of summer 1308 to scale the summed digital signal within the dynamic range of summer 1308. In this way, the outputs of the DUCs representing the signals towards a particular area of the communication system can be summed into a single signal and converted into analog signals. Otherwise, as achieved in the preferred embodiment, it is collected in sets and converted into analog signals by multiple DACs to increase dynamic range and provide redundancy.

Referring to Fig. 14, there is shown an up converter 1400 for I, Q modulation in accordance with the present invention. The up converter 1400 includes first and second interpolation filters 1402 and 1404 (ie, a finite impulse response (FIR) filter) for interpolating the I and Q portions of the baseband signal, respectively. The I and Q portions of the interpolated baseband signal are up-converted at mixers 1406 and 1408 which receive input from numerically controlled oscillator 1410. The numerically controlled oscillator (NCO) 1410 receives as input a fixed phase increment that depends on the product of the up conversion frequency ω _O and the inverse sample rate τ, i.e., the up conversion frequency. This small amount is supplied to the phase accumulator 1412 in the NCO 1410. The output of the phase accumulator 1412 is sent to each of the sine and cosine generators 1414 and 1416 in the sample phase phi, generating an up-conversion signal. The I and Q portions of the up-converted baseband signal are then summed in summer 1418 to output the modulated IF signal of up-converter 1400.

15 shows a modulator 1500 for direct modulation of phase, R, Θ modulation, direct modulation. The modulator 1500 provides a simple way of generating FM on the up converter 1400. A baseband signal interpolation filter 1502 (e.g., FIR filter) is sent and then scaled by kτ at scaler 1504. The interpolated and scaled baseband signal is summed with a fixed phase increment ω _O τ at summer 1506 in numerically controlled oscillator / modulator (NCOM) 1508. This summation is sent to phase accumulator 1510, which outputs a sample phase, and this output is sent to sinusoidal generator 1512, so that modulator 1500 outputs a modulated IF signal.

The apparatus shown in FIGS. 14 and 15 is suitable for use with the up converter / modulator 1340 of the present invention. However, up converter 1400 is not effective to generate FM, and modulator 1500 does not provide I, Q up conversion. 16 illustrates a preferred up-converter / modulator 1340 that provides both I, Q up-conversion and FM modulation, and thus provides multiple access using various access methods without significantly increasing base station hardware and cost. It is. Up converter / modulator 1340 provides I, Q up conversion for a single baseband signal or R, Θ modulation for two baseband signals.

The I, Q portion or two R, Θ signals of the baseband signal are input to up converter / modulator 1340 at each of ports 1602 and 1604. The signal selectors 1606, 1608 select between the I, Q or R, Θ signals based on the operating mode of the up converter / modulator 1340.

Regarding the processing of the I and Q signals, the I portion of the signal is sent from the selector 1606 to an interpolation filter (eg, FIR filter) 1610. The interpolated signal is sent to mixer 1612 and up-converted by a sine curve from cosine generator 1614. The cosine generator 1614 receives the input sample phase φ from the phase accumulator 1616. A selector 1618 is provided to select the 0 input for I, Q up conversion. The output of selector 1618 is scaled by kτ at scaler 1620 to lead to zero output, which is added to ω _O τ in adder 1622. In the case of the I, Q up-conversion, the sum, ω _O τ, is input to the phase accumulator 1616 to produce a sample phase output.

The processing of the Q portion of the signal is similar. The Q signal is selected by the selector 1608 and then sent to an interpolation filter (eg, FIR filter) 1626. The interpolated Q signal is sent to mixer 1628 and then up-converted by a sine curve from sine generator 1630. In the case of I and Q, the sine generator 1630 receives an input from a selector 1632 that selects the sample phase .phi. Produced by the phase accumulator 1616. The up-converted I, Q signals are summed at summer 1634 as an up-converted / modulated output of up-converter / modulator 1340 in I, Q mode.

In R, Θ processing, the selectors 1606, 1608 select two separate R, Θ signals. In R, Θ processing, up-converter / modulator 1340 processes both R, Θ signals simultaneously. The first signal, R, Θ-1 is interpolated and filtered by the interpolation filter 1610. In the case of R, Θ, selector 1618 selects the interpolated R, Θ-1 signal, which is scaled by kτ in scaler 1620 and then added to ω _O τ in adder 1622. The output of adder 1622 is sent to phase accumulator 1616, where a sample phase phi is generated and input to cosine generator 1614. The output of cosine generator 1614 is the first of the two modulated IF signal outputs of up converter / modulator 1340 in the R, Θ processing mode.

The second R, Θ signal, R, Θ-2 is selected by the selector 1608 and transmitted to the interpolation filter 1626. The interpolated R, Θ-2 signal is sent to the scaler 1636 and scaled by kτ. The scaled signal is then summed with ω _O τ at adder 1638. The output of the adder 1638 is input to the phase accumulator 1640 to produce an output sample phase, which is selected by the selector 1632 and sent to the sine generator 1630. The output of sine generator 1630 is the second of the two modulated IF signal outputs of up converter / modulator 1340 in R, Θ processing mode.

It will be appreciated that the value ω _O τ sent to the adders 1622 and 1638 may be unique to provide an appropriate phase output associated with the cosine generator 1614 or the sine generator 1630. The value ω _O τ may also be programmed under the control of the channel processor 228 to produce a specific carrier frequency output, for example, from the cosine generator 1614 or the sine generator 1630. Further, the scaler value kτ can be similarly programmed to select the frequency deviation.

While the receiver 200 and transmitter 300 of the transceiver 400 have been described separately, the transceiver 400 will now be described in more detail with reference to FIG. 4. The transceiver 400 is composed of a pair of transceiver banks 402, 404. Each bank is the same and includes a number of RF processing shelves 406. Each RF processing shelf 406 includes an RF mixer 408 and an ADC 410 that are coupled to receive and digitize a signal from antenna 412. The RF processing shelf 406 also includes three DACs 414, the outputs of which are summed by the summer 416 and sent to the RF up converter 418. The output of the RF up converter 417 is also sent to the RF summer 419 and summed with the corresponding output from the transceiver bank 404. The summed RF signal is transmitted to an amplifier 418 which is amplified and radiated from the antenna 420.

The signals received from the ADC 410 (not shown) are interconnected to a number of digital converter modules (DCMs) 426 via the receive bus 428. Similarly, the transmit signal is transmitted from DCM 426 to DAC 414 via transmit bus 430. As can be seen, receive bus 428 and transmit bus 430 are high-speed data buses implemented with a backplane structure within RF frame 432. In a preferred embodiment, the communication on the backplane is approximately 60 MHz, but due to the intimate physical relationship of the elements, such high speed communication is possible without significant error in the high speed data signal.

11 illustrates a preferred embodiment of DCM 426. The DCM 426 includes a plurality of DDC application specific integrated circuits 1102 and a plurality of DUC ASICs 1104 to process received and transmitted signals. The received signal is transmitted from the antenna 412 to the DDC ASIC 1102 via the communication line 1110 via the receive backplane interconnect 1108, the backplane receiver 1106 and the buffer / driver bank 1107. In a preferred embodiment, DCM 426 includes ten DDC ASICs 1102, and as described above, each DDC ASIC 1102 is implemented with three separate DDCs. In a preferred embodiment, eight DDC ASICs 1102 provide communication channel functionality and two DDC ASICs 1102 provide scanning functionality. The output of the DDC ASIC 1102 is sent to the backplane interconnect 1118 via the link 1112, backplane formatter 1114, and backplane driver 1116. Received signals from backplane interconnect 1118 are transmitted via interface medium 450 (FIG. 4) to multiple channel processors 448 arranged in groups at processor self 446.

In transmit mode, transmit signals are transmitted from channel processor 448 to multiple DUC ASICs 1104 via interface medium 450, backplane interconnect 1118, transmit backplane receiver 1120, and selector / formatter 1124. do. Each of the DUC ASICs 1104 includes four separate DUCs, which are for processing four communication channels in R, Θ mode, or two communication channels in I, Q mode, as described above. The output of the DUC ASIC 1104 is sent to the transmit backplane driver 1128 and backplane interconnect 1130 via line 1126 and then to the DAC 414.

It should be noted that the clock signal is provided to the device of DCM 426.

The interface medium 450 located between the DCM 426 and the channel processor 448 may be any suitable communication medium. For example, the interface medium may be a microwave line, a TDM span or an optical fiber line. In this arrangement the channel processor 448 may be located substantially far from the DCM 426 and the RF processing shelf 406. Thus, the channel processing function may be central, while the transceiver function is at the communication cell site. In this arrangement, the important part of the communication equipment can be located far from the actual communication cell site, so the configuration of the communication cell site is simplified. As a result, the operator can save the physical space required for the equipment and can perform more concentrated operation and maintenance.

The transceiver 400 shown in FIG. 4 includes three DCM 426 having 12 communication channel capabilities per DCM 426. This arrangement provides system reliability. If one DCM 426 fails, only part of the communication channel available in the system is lost. In addition, DCM can be modified to provide multiple air interface capabilities. That is, the DDC and DUC on DCM can be programmed separately for a specific air interface. Thus, the transceiver 400 provides multiple air interface capabilities.

From the foregoing, it will be appreciated that there are a number of advantages to the structure of the transceiver 400. Referring to FIG. 5, a receiver 500 of a transceiver 400 is shown that is substantially similar to the receiver 200 shown in FIG. Although a number of DDCs 214 and interconnected TDM buses 226 have been removed for clarity, it should be appreciated that the receiver 500 includes these devices. Receiver 500 receives the uplink digital signal from antenna 508 / mixer 509 and sends ADC (via selector 504) via selector 504 to transmit data signal to channel processor 510 via data bus 514. 506 includes additional DDCs 502 interconnected. During operation, channel processor 510 needs to examine other antennas besides the antennas currently processing the communication channel to determine whether they are transmitting on the best antenna in the communication cell. That is, if an antenna serving another area of a communication cell provides good quality communication, the communication line must be reset on that antenna. In order to determine the availability of such an antenna that provides good quality communication, the channel processor scans each zone of the communication cell. In the present invention, this is accomplished by channel processor 510 acquiring DDC 502 via control bus 512 and programming it to receive communication from each antenna in the communication cell. Received information, for example, received signal strength indications (RSSI) and the like, is evaluated by the channel processor 510 to determine whether a quality antenna is present. Processing at the DDC 502 is performed under the command of the channel processor 510 except that the DDC 502 receives signals from multiple antennas in the communication cell as opposed to a single antenna serving the active communication channel. Same as the treatment achieved in 214).

19 shows a method 1900-1926 to achieve this per-channel scanning feature. The method begins with bubble 1900 and proceeds to step 1902 where a timer is set. The channel processor then checks in step 1904 if the DDC 302 is idle, and if in idle, step 1906 checks if the control bus 312 is idle. If the control bus 312 is idle, the timer is stopped at step 1908, and at step 1909 the channel processor 310 captures the control bus 312. If the channel processor 310 is unable to capture the control bus 312, the method returns to step 1902. If the DDC 302 or control bus 312 is not idle, a timeout check is made at step 1910, and if the timeout has not been reached, the method checks again whether the DDC is available. If the timeout has been reached, an error is reported in step 1920, ie the channel processor 310 cannot complete the desired scan.

If the control bus 312 was successfully captured in step 1912, then in step 1914 the processor programs the DDC 302 for a scan operation. However, if the DDC 302 is not active at step 1916, the program is aborted and an error is reported at step 1920. If the DDC is active, then at 1918 the DDC 302 accepts programming to begin collecting samples from the various antennas 308. When all samples are collected in step 1922, the DDC is programmed to idle in step 1924 and the method ends in step 1926.

Another feature of the transceiver 400 is that it can provide signaling to a specific area or all areas of a communication cell. Referring again to FIGS. 3 and 13, the output of the up converter / modulator 1340 is sent to a selector 306 that selects output from a number of up converter / modulators 1340 towards a particular area of the communication cell. As shown in FIG. 3, for three zone communication cells, three data paths 313 are provided corresponding to three zones of the communication cell, and the function of the selector 306 is an upconverter on these three data paths. / Summing the output of the modulator 1340. In this manner, the downlink signal from up converter / modulator 1340 is transmitted to the appropriate area of the communication cell.

However, selector 306 provides the output of up converter / modulator 1340 to all signal paths 313. In this case, the downlink signal from up converter / modulator 1340 is transmitted simultaneously to all zones of the communication cell. Thus, all signaling channels via simucast designate the up-converter / modulator as the signaling channel and program the selector 306 to transmit downlink signals from this up-converter / modulator to all regions of the communication cell. Is generated by It should also be noted that signaling for a particular zone is achieved by reprogramming the selector 306 to transmit the downlink signal from the signaling up converter / modulator 1340 to one or more zones of the communication cell.

Referring to FIG. 6, a transceiver 600 is shown that includes the functional elements described with respect to the transceiver 400, but with a different arrangement of structures. The transceiver 600 advantageously provides downlink digital up conversions corresponding to uplink digital down conversions in the channel processor. The channel processor is then interconnected to the RF hardware via a high speed line.

In the receive mode, the RF signal is received at antenna 602 (individually numbers 1, 2, ..., n) and transmitted to the associated receive RF processing self 604. Each receive RF self 604 includes an RF down converter 606 and an analog to digital converter 608. The output of receive RF self 604 is a high-speed digital data stream that is transmitted to uplink channel 610 to multiple channel processors 612. Uplink bus 610 is a suitable high speed bus, such as an optical fiber bus. Channel processor 612 includes a selector that selects one antenna to receive the data stream, a DDC, and another baseband processing element 613 that selects and processes the data stream from one antenna to restore the communication channel. do. The communication channel is then transmitted to the cellular network and the PSTN via appropriate interconnects.

In transmit mode, the downlink signal is received by the channel processor 612 from the cellular network and the PSTN. The channel processor includes an up converter / modulator 615 that upconverts and modulates the downlink signal prior to transmitting the downlink data stream via the transmit bus 616 to the transmit RF processing self 614. It should be noted that the transmit bus 616 is also a suitable high speed bus. The transmit RF processing self 614 includes a digital summer 618, a DAC 620, and an RF up converter 622 for processing the downlink data stream into an RF analog signal. The RF analog signal is then transmitted via analog transmit bus 624 to power amplifier 626 and antenna 628 to radiate the RF signal.

Referring to FIG. 7, a transceiver 700 is shown that includes the functional elements described with respect to the transceiver 400 but has a different structural arrangement. The transceiver 700 will be described for a single zone of a separate communication system. It should be appreciated that the transceiver 700 can be easily modified to service multiple zones.

In the receive mode, the RF signal is received by the antenna 702 and transmitted to the receive RF processing shelf 704. Each of the received RF processing shelves 704 includes an RF down converter 703 and an ADC 705. The output of the received RF processing shelf 704 is a high speed data sequence, which is transmitted to the plurality of DDCs 708 via the high speed backplane 706. The DDC 708 operates as described above to select a high speed data string and down convert the data string. The output of the DDC 708 is a slow data stream that is sent to the channel processor 714 via bus 710 and bus 712. The channel processor 714 operates as described above to process the communication channel and transmit the communication channel to the cellular network and the PSTN via the channel bus 716 and the network interface 718. The DDC 708 of the transceiver 700 may also advantageously be located on the channel processor itself with suitable high speed backplane interconnects.

In transmit mode, the downlink signal is transmitted from the cellular network and the PSTN to the channel processor 714 via the interface 718 and the channel bus 716. The channel processor 714 upconverts and digitizes the downlink signal into an analog IF signal, including the DUC and the DAC. The analog IF signal is transmitted to the transmission matrix 724 via coaxial cable interconnect 722 or other suitable interconnect medium, where the downlink signal is combined with other downlink analog IF signals. The combined analog IF signal is then transmitted to RF up converter 728 via coaxial interconnect 726. The RF up converter 728 converts the IF signal into an RF signal. The RF signal from up converter 728 is RF summed in summer 730 and sent to a power amplifier and transmit antenna (not shown).

As can be seen from the transceiver 700, high speed data processing, i.e., digital up-conversion on the downlink signal, is advantageously made in the channel processor 714. A preferred embodiment of the channel processor 714 is shown in FIG. Channel processor 714 is mostly similar to channel processor 228 shown in FIG. In addition to these elements, the channel processor 714 includes a DUC 1802 coupled to receive downlink signals from the processors 1742, 1742 ′. The DUC 1802 upconverts the downlink signal and sends it to the DAC 1806, where the downlink signal is converted into an analog IF signal. The analog IF signal is then transmitted to the transmission matrix 724 via ports 1740 and 1740 '.

8, 9, and 10 illustrate an arrangement in which the elements of the transceiver 400 are interconnected. In order to ensure that one device fails and the entire cell is not lost, the daisy chain of the devices is avoided. As can be seen in FIG. 8, selector 800 is provided to DCM 802 prior to DUC 804 and DAC 806, for example, in a downlink configuration. Direct data line 808 is provided from DUC 804 to selector 800, from DCM 802 to DCM 802, and finally to DAC 806. Bypass data line 810 is also tapped directly on data line 808. In operation, if one or more DCM 802 fails, the selector 800 activates the appropriate bypass data line 810 to bypass the failed DCM 802 and continue to the amplifier 812 and transmit antenna 814. Allow a signal to be sent. It should be appreciated that uplink components may be similarly connected to provide a fail-safe receiver of the transceiver.

Another arrangement is shown in FIG. 9. In FIG. 9, channel processor 920 is interconnected to DCM 902 via TDM bus 922. DCMs are interconnected as shown in FIG. 8, and the selector 900 associated with each DCM 902 is not shown. It should be appreciated that the selector can be easily implemented directly in the DCM 902. Bypass line 924 interconnects channel processor 920 directly to the associated DCM and additional selectors (not shown) within DCM 902. If the channel processor 920 that crashes the TDM bus 922 fails or the TDM bus 922 itself fails, the selector in the DCM 902 activates the appropriate bypass line 924 to activate the DAC 906, The communication signal is continuously transmitted to the amplifier 912 and the transmit antenna 914.

Another arrangement is shown in FIG. 10. DCM 1002 are interconnected as shown in FIG. 8. In FIG. 10, direct line 1030 interconnects channel processors 1020 in a daisy chain fashion, and the outputs of each channel processor 1020 are summed in summer 1032 to add DCM (via TDM bus 1034). 1002). The bypass line 1036 forming the second bus is provided to the selector 1038 in a manner similar to that shown in DCM in FIG. 8. If one channel processor fails, the signal from the remaining channel processor 1020 is bypassed around the failed channel processor in the same manner as described for DCM 802 to selector 1000, DAC 1006, amplifier ( 1012 and antenna 1014.

Many advantages and features of the invention will be apparent from the foregoing description of some preferred embodiments. Numerous other embodiments, advantages, and features that fall within the scope of the invention will be apparent from the appended claims.

Claims (10)

A first selector and a second selector having a plurality of inputs and an output coupled to the first interpolation filter and the second interpolation filter, respectively; A first adder receiving a first programmable phase value and the output being coupled to a first phase accumulator, and an output of the first interpolation filter selectively coupled to a first mixer; An output of the first phase accumulator coupled to a first sinusoidal generator and selectively coupled to a second sinusoidal generator; A second adder receiving a second programmable phase value and the output being coupled to a second phase accumulator, and an output of the second interpolation filter selectively coupled to a second mixer; Each output of the first and second mixers is selectively connected to an output adder and to each input of the first and second mixers; An output of the second phase accumulator selectively connected to the second sinusoidal generator Up converter / modulator comprising a. The up-converter / modulator of claim 1 comprising first and second scalers programmable to variably scale the output of the first and second interpolation filters. First and second having a plurality of inputs connected to receive a plurality of input signals, and outputs respectively connected to inputs of the first and second interpolation filters, the first and second operating to select one of the plurality of input signals Contains a selector, In the first operation mode, An input signal having a first component and a second component is coupled to the up converter / modulator, whereby the first component is connected to the first interpolation filter through the first selector, and the second component is the second selector. Is connected to the second interpolation filter through; The output of the first interpolation filter is connected to a first input of a first mixer and the output of a first sinusoidal generator is connected to a second input of the first mixer and the output of the first mixer is a first input of an output adder. Connected to; The output of the second interpolation filter is connected to a first input of a second mixer and the output of a second sinusoidal generator is connected to a second input of the second mixer and the output of the second mixer is a second of the output adder. Is connected to the input; A first phase accumulator is connected to receive a first programmable phase value, and the phase value output of the first phase accumulator is connected to each input of the first and second sinusoidal generators; In the second operation mode, Since a first input signal and a second input signal are coupled to the up converter / modulator, the first input signal is coupled to the first interpolation filter through the first selector, and the second input signal is connected to the second selector. Is connected to the second interpolation filter through; An output of the first interpolation filter is coupled to a first programmable scaler; A first adder is coupled to receive a scaled output from the first programmable scaler and a first phase value, the first summed output value of the first adder is coupled to the first phase accumulator, and A phase value output of the phase accumulator is connected to the first sinusoidal generator; An output of the second interpolation filter is connected to a second scaler; A second adder is coupled to receive the scaled output from the second scaler and a second phase value, the second summed output of the second adder is coupled to a second phase accumulator, A phase value output is coupled to the second sinusoidal generator Multi-mode up converter / modulator. Means for selecting, from the plurality of input signals, a first signal having a first signal component and a second signal component or a second signal and a third signal each having a single signal component; When the first signal is selected, Means for interpolating the first signal component and the second signal component to generate first and second interpolated signal components, respectively; Means for mixing the first interpolated signal component with an output of a first means for generating a sinusoidal signal to produce a first mixed signal; Means for mixing the second interpolated signal component with an output of a second means for generating a sinusoidal signal to produce a second mixed signal; Means for adding the first mixed signal and the second mixed signal, If the second signal is selected, Means for interpolating the second signal and the third signal to generate a second interpolation signal and a third interpolation signal; Means for generating a first programmed phase value from the first interpolation signal; Means for generating a second programmed phase value from the third interpolation signal; Means for generating a first sinusoidal output signal and a second sinusoidal output signal from the second interpolation signal and the third interpolation signal, respectively. Device for up-converting / modulating a communication signal comprising a. 5. The apparatus of claim 4, wherein the means for interpolating the second signal and the third signal comprises means for interpolating the first signal component and the second signal component. 6. The apparatus of claim 4 or 5, wherein when the second and third signals are selected, the apparatus comprises means for programmably scaling the second interpolation signal and programmable scaling of the third interpolation signal. Means for up converting / modulating a communication signal. A method of upconverting / modulating a communication signal in a multiple access format: Selecting one of a communication signal under a first access format having a first component and a second component or a pair of communication signals, each under a second access format; When a communication signal under the first access format is selected, Interpolating the first component and the second component; Mixing the interpolated first component with the first sinusoidal signal and the interpolated second component with the second sinusoidal signal; Summing the interpolated and mixed first component with the interpolated and mixed second component Including, When the pair of communication signals are selected, Interpolating a first signal of the pair of communication signals and a second signal of the pair of communication signals; Summing the interpolated first signal and the first programmed phase value and summing the interpolated second signal and the second phase value; Determining a first phase angle from the summed first signal and determining a second phase angle from the summed second signal; Generating a first sinusoid from the first phase angle and generating a second sinusoid from the second phase angle Up conversion / modulation method comprising a communication signal. 8. The method of claim 7, wherein after the step of interpolating a first signal of the pair of communication signals and a second signal of the pair of communication signals, Programming a scaler to scale the interpolated first signal and the interpolated second signal. A plurality of channel processors for receiving a communication signal and processing the communication signal for transmission over one of the plurality of communication channels; A plurality of multiple access up converters / modulators associated with each of the plurality of communication channels and coupled to the channel processor for up converting and modulating the communication signal into a digital intermediate frequency signal in accordance with one of a plurality of access methods; A plurality of digital adders coupling the multiple access up converters / modulators to sum the digital intermediate frequency signals into a digital intermediate frequency signal subgroup; A digital to analog converter for converting the digital intermediate frequency signal subgroups into analog signals; A radio frequency up converter coupled to the digital to analog converter for converting the analog signal into a radio frequency signal; A power amplifier coupled to the up converter for amplifying the radio frequency signal and transmitting the radio frequency signal to an antenna Multiple access digital transmitter comprising a. 10. The apparatus of claim 9, wherein each of the multiple access up converters / modulators is A first selector and a second selector having a plurality of inputs and an output coupled to the first interpolation filter and the second interpolation filter, respectively; A first adder coupled to receive a first programmable phase value and an output coupled to a first phase accumulator, and an output of the first interpolation filter selectively coupled to a first mixer; An output of the first phase accumulator coupled to a first sinusoidal generator and selectively coupled to a second sinusoidal generator; A second adder coupled to receive a second programmable phase value, the output coupled to a second phase accumulator, and an output of the second interpolation filter selectively coupled to a second mixer; An output adder and each output of said first and second mixers selectively connected to respective inputs of said first and second mixers, respectively; An output of said second phase accumulator selectively coupled to a second sinusoidal generator, In the first mode of operation the output of the output adder is an up-converted output signal, and in the second mode of operation each output of the first and second sinusoidal generators is a modulated output signal. Multiple access digital transmitter.