CA2036169A1 - Boitiers de microcircuits, lamines - Google Patents

Boitiers de microcircuits, lamines

Info

Publication number
CA2036169A1
CA2036169A1 CA002036169A CA2036169A CA2036169A1 CA 2036169 A1 CA2036169 A1 CA 2036169A1 CA 002036169 A CA002036169 A CA 002036169A CA 2036169 A CA2036169 A CA 2036169A CA 2036169 A1 CA2036169 A1 CA 2036169A1
Authority
CA
Canada
Prior art keywords
laminates
stack
pressurizing medium
membrane
transfer membrane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002036169A
Other languages
English (en)
Inventor
William O. Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microelectronic Packaging America
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2036169A1 publication Critical patent/CA2036169A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B25/00Layered products comprising a layer of natural or synthetic rubber
    • B32B25/04Layered products comprising a layer of natural or synthetic rubber comprising rubber as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B25/042Layered products comprising a layer of natural or synthetic rubber comprising rubber as the main or only constituent of a layer, which is next to another layer of the same or of a different material of natural rubber or synthetic rubber
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B25/00Layered products comprising a layer of natural or synthetic rubber
    • B32B25/20Layered products comprising a layer of natural or synthetic rubber comprising silicone rubber
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2439/00Containers; Receptacles
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Materials For Medical Uses (AREA)
  • Die Bonding (AREA)
CA002036169A 1990-02-20 1991-02-12 Boitiers de microcircuits, lamines Abandoned CA2036169A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48309190A 1990-02-20 1990-02-20
US483,091 1990-02-20

Publications (1)

Publication Number Publication Date
CA2036169A1 true CA2036169A1 (fr) 1991-08-21

Family

ID=23918620

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002036169A Abandoned CA2036169A1 (fr) 1990-02-20 1991-02-12 Boitiers de microcircuits, lamines

Country Status (6)

Country Link
JP (1) JPH04214640A (fr)
KR (1) KR920000129A (fr)
CA (1) CA2036169A1 (fr)
DE (1) DE4105275A1 (fr)
FR (1) FR2658661A1 (fr)
GB (1) GB2243803A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10327746A1 (de) * 2003-06-18 2005-01-05 Giesecke & Devrient Gmbh Verfahren zum Fixieren einer Beschichtung auf einem Trägerband
JP2009117565A (ja) * 2007-11-06 2009-05-28 Maruwa Co Ltd 電子部品を装着するためのセラミック成形体及びその製造方法並びにその方法に使用される弾性被覆シート

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4737208A (en) * 1986-09-29 1988-04-12 American Telephone And Telegraph Company, At&T Bell Laboratories Method of fabricating multilayer structures with nonplanar surfaces
GB2222800B (en) * 1988-09-16 1992-02-19 Stc Plc Hybrid circuits

Also Published As

Publication number Publication date
DE4105275A1 (de) 1991-08-22
FR2658661A1 (fr) 1991-08-23
GB2243803A (en) 1991-11-13
GB9103242D0 (en) 1991-04-03
JPH04214640A (ja) 1992-08-05
KR920000129A (ko) 1992-01-10

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Legal Events

Date Code Title Description
FZDE Dead