CA2018938C - Microprocessor-based stand-alone digital protective relay for power transformers - Google Patents
Microprocessor-based stand-alone digital protective relay for power transformers Download PDFInfo
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Abstract
A stand alone protective apparatus and method is provided for electrical power devices. Power devices can be damaged due to conditions for example of over current, magnetizing in rush-current, over excitation voltage, saturation, ground fault or internal faults. To protect power devices from the noted conditions, electrical current of the power device is sensed and sampled. Digital processing is used for analyzing the digitally coded sample current and based on one of the conditions that can cause damage, a signal is provided for selectively actuating, by tripping an electric/electronic circuit breaker.
Description
~'~0~.~938 The present invention relates generally to power transformer protection, and particularly to methods and apparatuses that employ digital signal processing technigues. More particularly still, the preferred method and apparatus of the present invention are microprocessor based and utilize harmonic restraints and ground fault detection to provide reliable protection.
A general microprocessor based transformer monitoring system is disclosed in United States Patent 4,654,06 v granted March 31, 198'7 to Thomas D. Poyser et al. The system provides continuous on-line monitoring and analysis of transformer operation by monitoring various parameters related to transformer load (i.e. currents) and condition.
Maximum, minimum, and instantaneous values of the parame-ters are stored and analyzed. To perform the analysis, a hierarchy of thresholds is associated With each parameter. When a parameter exceeds any one of the thresholds, a response is produced by the transformer monitoring system. The type of response depends on the 20 level of the exceeded threshold in the hierarchy. The range of response produced by the transformer monitoring system includes: continuing normal periodic data col-lection and analysis, increasing the rate of data collec-tion and analysis, recommending an on-site physical check of the monitored transformer, reducing transformer load, and taking the transformer off line.
~oa~s93~
-z-A microprocessor based method for remote digital protection of distribution transformers is disclosed in United States Patent 4,745,512 granted May 17, 1988 to ,Tohn T. Hampson. The method measures and compares increases in both negative and positive phase reference currents on a distribution cable feeding a transformer and to trigger a circuit breaker to isolate the cable only if the negative sequence current increase exceeds a predetermined proportion of any simultaneous positive x0 seguence current increase. Consequently, energizing with a 12.5% unbalance current has been found possible without false tripping. The supply parameters are sampled with a sampling period of one cycle of the supply waveform.
Yet a third computer based system is disclosed in United States Patent 4,772.678 granted September 2U, 1988 to Yoshifumi Oura et al. In this transformer protection system, data of voltages and currents detected at indi--vidual terminals of a transformer connected to an electric power system are supplied to a computer. The computer 20 computes driving point admittances of the transformer on the basis of the voltages and current data and predeter-mined transfer admittances of the transformer and decides that an internal fault has occurred in the transformer when the values of the driving point admittances or shunt adaaittances deviate from pre-set reference values, thereby disconnecting the transformer from the electric power system. Thus, in such a system physical constants of known values peculiar to tha_ transformer being protected must be used in the computation.
30 The use of the second harmonic to distinguish the normal in-rush magnetizing currents from fault currents reg;uiring protective action has been disclosed by several United States patents.
United States Patent 2,29D,101 granted July 14, 1942 to Heinz Gutmann simply prevents operation of the protec-tive differential relay from tripping in over-current eases where the second harmonic exists.
In United States Patent 3,223,889 granted December :14, 1965 to Edmund 0. Schweitzer, in addition to the mere ~~aistence of the second harmonic also the phase difference between the harmonic arid the fundamental must exceed a predetermined value for the protective relay to trip.
lp United States Patent 4,477,854 granted October 16, :1984 to Masaji Usui et al discloses a relay adapted for protection of a transformer and capable of functioning with certainty upon occurrence of any internal fault in t:he transformer but not functioning in the case of an in-rush current which flows therein at the time of non-load e~nergization or the like. The relay comprises a ratio differential element for comparing the amount of a sup-F>ression current with that. of a differential current flowing in the transformer, an element for detecting the 2o content proportion of a second harmonic component in the differential current, a monostable multivibrator for sending an output of a fixed pulse width at the moment of detection of the differential current, an AND circuit for ~~roducing an output in accordance with the logical product condition relative to the output of the second-harmonic detection element and that of the monostable multivi-brator, a timing circuit f or producing an output when the output of the second-harmonic detection element continues f or a predetermined period of time, and gate means for 3o suppressing the output of the ratio differential element when either the output of the AND circuit or that of the timing circuit is being fe:d thereto.
~- 4 -In United States Patent 3,337,772 granted August 22, 1!x67 to Stig Andersson, in addition to the second harmonic the fifth harmonic is used to stabilize the protection device against increase in the difference current caused b~~ over-voltage, which causes an increase in the differ-ence current of the fifth harmonic.
In United States Patent 4,661,877 granted April 28, 1~~87 to Masaji Usui, a protective relay for a transformer i~csues a relay tripping command When the differential current that is the difference between currents in the primary and secondary windings of the transformer has a m~~gnitude larger 'that the specified value and, at the same time, when the cliff erential current includes the ffifth harmonic component less than the specified value.
Ar.~other cause of tripping signal generation is the dif-fe~rential current value processed to have a certain timer characteristics.
The present invention endeavors to provide a comprehensive stand-alone digital protective relay system anal method. In particular, it provides protection func ti.ons including percentage differential protection with second-harmonic restraint: for magnetizing in-rush and a fifth-harmonic restraint for overexcitation conditions, and a separate protection :Eor high impedance primary and secondary ground faults. N~ore narrowly, the ground relay is also equipped with~a second-harmonic restraint to pre ve~nt tripping during in-ru~;h and through fault conditions with Current Tr ansf ormer ( C . T . > saturation . Hence, 'the ground relay is able to diaferentiate between a through fault and a ground fault.
In the preferred method of the F~resent .inventir~n the Fourier algx~rithm for the harmonics cornputatic~n is used.
g~yw,evexy a,ny other relay algorithm may .be used try replac-ing only that particular subrou~:ine in the sortware» "A
State-Qf-The-Art P,eview of Transformer Protection A3gorithms" is a useful paper by M.A. Rahman and H.
;Feyasurya published in 'the IEEE Transacti.ans oyv. power ~~~.~.~e~yr Volv .girl ~~'n ~~I ~p~.L~ 19UU..
Appendix A is a paper deli~rered by the in'rentors to the Ga~eadian Elect: ical Association in March 26-29I 1990 at Montreal. S~uebec, Canadar detailing test results of the present protective relay system. Appendix F3 is a paper, delivered by the inventors to the TEEE PES Eu.rnrner Meeting Jury 7-14, 1989 at Long ~eachr Ca.li~ornia, ~ U. S.A. , detailed some test results of the present projective relay system.
Accordingly, the present invention provides a pro 2o tective relay apparatu:~ for proter_ting electrical power devices from damage due to conditions of ervercurrent, ground fault, through-fault, and the like, by producing a signal indicative of at least one o:~ the r_r~nditions to .cause interruption of flow of electrical current to the electrical power devices comprising: electrical current sensing means; sample-and-hall means for sampling the electrical current; a.na,log--tc~-digital co:wc~rter means for d::~r~itally encoding the sampled current; and digital pro cessing means for analyzing ;:he dligitally encoded current 30 ir, a predetermined manner to identify at l~:ast ore of the ccnditians .and produce the signal.
In on,e feature of the protacti.ve relay apparatus, the electrical current sensing means cosnprisiny current tran5-zt~~e~~e former means for sensing electrical current flow through the electrical power device, and second current trans-former means for sensing ground fault current in the e7lectrical power device. The protective relay apparatus may further include Iow pass filter means intermediate the first and second current transformer means and the sample-and-hold means.
In another feature of the protective relay apparatus, the digital processing means comprising stored program 1o means for storing encoded current samples provided in sequence by the analog-to-digital converter means and calculating from the stored encoded current samples dif-ferential, through, and ground fault currents sense by th~~ first and second current transformer means.
The present invention also provides a method for protecting an electrical power device, comprising:
(a) sensing electrical current flow in the power device;
(b;i periodically sampling current sensed in step (a);
(c;~ digitally encoding the current sampled in step (b);
20 (d;~ analyzing the digitally encoded current in a pre-determined manner to determine instantaneous values of fundamental, second harmonic, and fifth harmonic com-ponents thereof; and (e) comparing the second and fifth harmonic components to the fundamental component in a pr~e~determined manner to indicate a fault condition.
In one feature of the method for protecting an electrical power device, the method further comprises the following step between steps (c) and (d): analyzing the digitally encoded current by calculating differential, 3o through, and ground fault cur rents in the electrical Bower device. Step (d) comprises applying a predetermined dis-crete fourier transform to compute the instantaneous values of fundamental, second harmonic, and fifth harmonic 20 x.9939 c<>mponents. Step (al further includes the step of incre-me~nting fault-count associated with a predetermined fault condition when the fault: condition is indicated and of resetting the fault-count: when the fault condition is not indicated.
In another feature of the method for protecting the e~.ectrical power device, the method further includes the fol lowing step: ( f ) examining the fault-count and causing a trip signal to be sent to cause interruption of electri-ca~l power to the electrical power device when the fault-to oouwt exceeds a predetermined threshold.
In the accompanying drawings, Figure 1 is a block schematic of the apparatus of the present invention connected to the power transformer protected;
Figure 2 is a more detailed block schematic of the data acquisition circuits shaven in Figure 1;
Figure 3 is a more detailed block schematic of the signal processing circuits shown in Figure 1; and Figure 4 is a flow-chart of the method and software 20 implementing ail 'the protections in the signal processing circuits shown in Figure 3.
Figure 1 of the drawings shows the block schematic of the digital protective relay apparatus and its con-nection to a protected power transformer 10. By way of example, the power.transformer ZO is a 5 kVA deltalstar three-phase power transforrner having three primary coils 11. 12, and 13 connected :i.n a delta configuration, and having three secondary coils 14, 15, and 16 connected in a star configuration. The three primary windings 11, 12, 30 and 13 are connected to a three-phase power source through three triac circuit breakers 17, 18, and 19 by means of input terminals a, b, and c. In order to sense 'the three x!718938 g -primary currents ila, ilb and ilc there are three corres-ponding current transformers 20, 21, and 22 in a star con-figuration for sensing the primary currents between the triacs 17, 18, and 19 and the primary windings 11, 12, and 13. Likewise, the secondary or load currents of the .secondary windings 14, 15, and 16 are sensed by three current transformers 23, 24, and 25, which are connected :in a star configuration to sense the currents in the :respective leads between the secondary windings and a l0 three-pole circuit breaker 26 which connects and discon-nects the secondary power to a three-phase load 27, which rnay of course be a remote load. Current flowing from 'the common point of the three secondary windings 14, 15, and .L6 to the ground (GND) is sensed by a further current t-ransformer 28. Thus, the current transformers 20, 21, 2, 23, 24, 25, and 28 provide a voltage each across shunt Resistors 20a, 21a, 22a, 23a, 24a, 25a and 28a, which is proportional to the respective current. The three ~~econdary currents are designated i2a~ i2b' and i2c and 20 flow from the secondary windings 14, 15, and 16, respec-tively. The ground current sensed by cureent transformer s!8 is designated i2g . Up to this point the described part of L~'igure 1 corresponds to conventional arrangements for power transformers and their connections.
The currents induced in the seven current trans-formers 20 to 25 and ~28 comprise the seven inputs to data acquisition circuits 29, t:he output of which is processed t~y signal processing circuits 30 which, when necessary, outputs a trip signal to cause the triacs 17, 18, and 19, 30 and, when so desired, the circuit breaker 26, to discon-nect the input power at terminals a, b, and a to the transformer 10 (and also t:o disconner_t the load 27), thus protecting the transformer 10 from damage due to shorts and over currents.
2~~.8938 - g The data acquisition circuits 29 comprise three sub-components, namely, a scaler and anti-aliasing low pass filter 31; a sample-and-hold circuit 32; and a multiplexer 33. The signal processing circuits 30 comprise an analog-to-digital converter 34, a digital signal processor 35, and a sampling clock 36.
In Figure 2 the seven analog signals from the current transformers 20 to 25 and 28 are applied each to the non-inverting input of an associated operational amplifier 37 1o to 43, each of which is adjusted by the variable resis-tance thereacross to scale the current 'transformers signal.
at its input to be compatible with the analog-to-digital converter 34 which ultimately processes it, and also to compensate for any gain sarrors in signal paths between the seven channels in the data acquisition circuits 29. The output of each operational amplifier is applied to an anti-aliasing low pass filter 44 to 50, the output of which is applied to a corresponding sample-and-hold circuit 51 to 57. Accordingly, due to the use of the 20 seven parallel sample-and-hold circuits 51 to 57, the corresponding three primary, three secondary, and one ground current picked-up by the current transformers 20 to 25 and 28 are sampled simultaneously during the same sampling interval. The: output of the sample-and-hold circuits 51 to 57 are multiplexed in a multiplexer 58 and appear in time sequence at its output to be applied to the analog-to-digital (A/D) converter 34. The anti-aliasing low pass filter 44 to 50~ is shown in detail in Appendix A Figure 4.
30 Turning now to Figure 3, the sampled analog signals supplied by the multiplexes 58 (in Figure 2> are input to the analog-to-digital converter 34, the encoded 12-bit output of which is applied to a data bus by means of two ~~18~38 tri-state buffers 59 and 60, which are necessary due to the fact that the A/D converter 34 is not fast enough to be interfaced directly with a digital signal processor 35.
'she processor 35 also interfaces its addressing and con-trol functions by means of a digital output port 61, which aupplies the three address bits A0, A1, and A2 to control ir_he multiplexes 58. A crystal 62 oscillating at a fre-duency of 15,36 kHz supplies that frequency to a divider fi3 which then provides the sampling clock of 960 HZ to c;ach of the sample-and-hold circuits 51 to 57, as well as i:o the processor 35 via :interrupt latch 64. All of the devices shown in Figure 3 are generally well known in 'the art and commercially available. And while a general pur-~~ose microprocessor could be used as the signal processor ~~S complex hardware would be required including multiple ~~rocessors. The preferred processor 35 is a device avail-able from Texas Instruments under Part No. TMS 320E15, which has an on-chip program memory of 4 k words and a data memory of 256 words, which is quite sufficient to 2p implement the software shown in flow chart form in Figure 9 without necessitating external memory use and interface .
The operation of the system and the method of the F~resent invention will now be described with particular reference to the f low chart of Figure 4 . At the star t (65) the system is initialized (66) by the processor 35, whereupon the circuit breakers 17, 18, and 19 are closed by sending a logic "high" on the trip signal lead 67.
The processor 35 then waits for an interrupt ( 68 ) . At the falling edge of the sampling clock the sampled 30 current transformer signals are held and, at the same time, the processor 35 is interrupted and selects (69) one of the seven channels via the multiplexes 58, which is then applied to the analog-to-digital converter 34.
The latter, after approximately 22 microseconds, outputs the 12-bit word to be read (71) by the processor 35.
These three steps (69, 70, and 71) are repeated seven times until all the helci samples in the sample-and-hold circuits 51 to 57 have been applied to the A/D converter 34 and read by the processor 35. The processor 35 then calculates the differential, the through, and the ground fault currents .(72). This computation is performed by the processor 35 in accordance with the three sets of l0 formulas (1), (21, and (3) given on page 2 of Appendix A
hereto. Once the calculation in step 72 is completed, the system then checks whether or not it should effect instantaneous tripping of the circuit breakers (73). A
trip command is given only if any one of the differential currents calculated in step 72 exceeds, and remains above, a predetermined threshold, for two consecutive samples.
If no tripping command is. issued as the result of step 73 then the program proceeds and calls on the discrete Fourier transform (DFT) to compute the fundamental, the 20 second, and the fifth harmonic components of the three differential currents determined in step 72, and computes therefrom the combined harmonic components ID21, ID22, and ID25 (as per equation (6) given on page 3 of the Appen-dix). Having computed and stored the requisite Com-ponents, the system moves to Check for the second harmonic restraint (75). This is accomplished by computing the square of a threshold of 0.1767 (17.67%) times ID2~ and if this product exceeds ID'1 then an in-rush Condition is declared and the program branches to call the ground relay 30 routine in step 80. If an in-rush condition is not .declared then the system proceeds to step 76 to check for 'the fifth harmonic restraint condition. This condition is checked by multiplying the squaz-e of a threshold of ~~1~938 0 .125 ( 12 . 5% ) by ID25 and if the product exceeds ID21 then .3n overexcitation condition is declared and a predeter-mined upper pick-up value C'o is selected (77), otherwise ,3 predetermined lower value Co is selected 178). These ~~alues Co and C'o correspond to two differential current ~~alues in the percentage differential characteristic (PDC), (for example, as shown in Figure 1 in Appendix A).
'.ehe percentage differential characteristic is called ( 79 ) and is checked as follows:
l0 No trip is declared if 'the fundamental primary differential current Id''(a,b,c)1 does not exceed the selected value, Co2 or C'o2 (78). If Id'(a,b,c)1 exceeds ~t:he selected value and if the fundamental through-current 7:t2(a,b,c)1 does not exceed the value of (1 PU)2' then a l:ault is declared. On the other hand if It2 (a,b,c), Exceeds the value of (1 P1:1)2 and then if Id2(a,b,c)1 also exceeds C2,xI2t (a,b,c, ) 1, no fault is declared. Otherwise << fault is declared. 11?11 corresponds to the value of rated primary current of the Bower transformer and C1=
20 (1.125 (12.5% slope). Thus, PDC is checked three times, one for each phase a,b, anal c. If fault is declared, then t;he fault counter of the particular phase is incremented, otherwise it is reset.
The system then proceeds to check for the presence of any primary ar secondary ground fault ( 80 ) . This check i.s performed with a second harmonic restraint as explained s~bove, but with a threshc>ld of . 088 ( 8 . 8% ) . The reason f.'or using the harmonic restraint in addition to threshold restraint here is that they ground relay is found to oper-30 a,te when the cure ent transformers saturate during in-rush a.nd through-fault conditions. During a through-fault, large second and higher order harmonics are present in the clround fault current, whereas during ground fault of 2~J18938 either primary or secondary, the second and higher order harmonics are very low. Hence with this harmonic restraint, the ground relay is able to differentiate between a through-fault and a ground fault, as a result the sensitivity of the: ground relay may be adjusted as desired by varying they pick-up value Cat~ If a ground fault is declared in step 80, then the program increments the corresponding fault: counter, but if a ground fault is not declared, the counter is reset. The program then moves to step 81 where all the fault counters are checked 1o to see if any one of them exceeds a preset value Td (Td = 1 for the differential relay; Td = 5 for the ground relay) , in which case a trip signal is sent to the circuit breakers (82?. After a trip signal has been issued, the system waits in a loop until the reset button is pressed (83) to restart operation. If as the result of the check-ing of the fault counters none exceeded the predetermined threshold Td then the program branches back into step 68 to wait for an interrupt to commence selecting the chan-nels by means of multiplexes 58, and the cycle resumes.
A general microprocessor based transformer monitoring system is disclosed in United States Patent 4,654,06 v granted March 31, 198'7 to Thomas D. Poyser et al. The system provides continuous on-line monitoring and analysis of transformer operation by monitoring various parameters related to transformer load (i.e. currents) and condition.
Maximum, minimum, and instantaneous values of the parame-ters are stored and analyzed. To perform the analysis, a hierarchy of thresholds is associated With each parameter. When a parameter exceeds any one of the thresholds, a response is produced by the transformer monitoring system. The type of response depends on the 20 level of the exceeded threshold in the hierarchy. The range of response produced by the transformer monitoring system includes: continuing normal periodic data col-lection and analysis, increasing the rate of data collec-tion and analysis, recommending an on-site physical check of the monitored transformer, reducing transformer load, and taking the transformer off line.
~oa~s93~
-z-A microprocessor based method for remote digital protection of distribution transformers is disclosed in United States Patent 4,745,512 granted May 17, 1988 to ,Tohn T. Hampson. The method measures and compares increases in both negative and positive phase reference currents on a distribution cable feeding a transformer and to trigger a circuit breaker to isolate the cable only if the negative sequence current increase exceeds a predetermined proportion of any simultaneous positive x0 seguence current increase. Consequently, energizing with a 12.5% unbalance current has been found possible without false tripping. The supply parameters are sampled with a sampling period of one cycle of the supply waveform.
Yet a third computer based system is disclosed in United States Patent 4,772.678 granted September 2U, 1988 to Yoshifumi Oura et al. In this transformer protection system, data of voltages and currents detected at indi--vidual terminals of a transformer connected to an electric power system are supplied to a computer. The computer 20 computes driving point admittances of the transformer on the basis of the voltages and current data and predeter-mined transfer admittances of the transformer and decides that an internal fault has occurred in the transformer when the values of the driving point admittances or shunt adaaittances deviate from pre-set reference values, thereby disconnecting the transformer from the electric power system. Thus, in such a system physical constants of known values peculiar to tha_ transformer being protected must be used in the computation.
30 The use of the second harmonic to distinguish the normal in-rush magnetizing currents from fault currents reg;uiring protective action has been disclosed by several United States patents.
United States Patent 2,29D,101 granted July 14, 1942 to Heinz Gutmann simply prevents operation of the protec-tive differential relay from tripping in over-current eases where the second harmonic exists.
In United States Patent 3,223,889 granted December :14, 1965 to Edmund 0. Schweitzer, in addition to the mere ~~aistence of the second harmonic also the phase difference between the harmonic arid the fundamental must exceed a predetermined value for the protective relay to trip.
lp United States Patent 4,477,854 granted October 16, :1984 to Masaji Usui et al discloses a relay adapted for protection of a transformer and capable of functioning with certainty upon occurrence of any internal fault in t:he transformer but not functioning in the case of an in-rush current which flows therein at the time of non-load e~nergization or the like. The relay comprises a ratio differential element for comparing the amount of a sup-F>ression current with that. of a differential current flowing in the transformer, an element for detecting the 2o content proportion of a second harmonic component in the differential current, a monostable multivibrator for sending an output of a fixed pulse width at the moment of detection of the differential current, an AND circuit for ~~roducing an output in accordance with the logical product condition relative to the output of the second-harmonic detection element and that of the monostable multivi-brator, a timing circuit f or producing an output when the output of the second-harmonic detection element continues f or a predetermined period of time, and gate means for 3o suppressing the output of the ratio differential element when either the output of the AND circuit or that of the timing circuit is being fe:d thereto.
~- 4 -In United States Patent 3,337,772 granted August 22, 1!x67 to Stig Andersson, in addition to the second harmonic the fifth harmonic is used to stabilize the protection device against increase in the difference current caused b~~ over-voltage, which causes an increase in the differ-ence current of the fifth harmonic.
In United States Patent 4,661,877 granted April 28, 1~~87 to Masaji Usui, a protective relay for a transformer i~csues a relay tripping command When the differential current that is the difference between currents in the primary and secondary windings of the transformer has a m~~gnitude larger 'that the specified value and, at the same time, when the cliff erential current includes the ffifth harmonic component less than the specified value.
Ar.~other cause of tripping signal generation is the dif-fe~rential current value processed to have a certain timer characteristics.
The present invention endeavors to provide a comprehensive stand-alone digital protective relay system anal method. In particular, it provides protection func ti.ons including percentage differential protection with second-harmonic restraint: for magnetizing in-rush and a fifth-harmonic restraint for overexcitation conditions, and a separate protection :Eor high impedance primary and secondary ground faults. N~ore narrowly, the ground relay is also equipped with~a second-harmonic restraint to pre ve~nt tripping during in-ru~;h and through fault conditions with Current Tr ansf ormer ( C . T . > saturation . Hence, 'the ground relay is able to diaferentiate between a through fault and a ground fault.
In the preferred method of the F~resent .inventir~n the Fourier algx~rithm for the harmonics cornputatic~n is used.
g~yw,evexy a,ny other relay algorithm may .be used try replac-ing only that particular subrou~:ine in the sortware» "A
State-Qf-The-Art P,eview of Transformer Protection A3gorithms" is a useful paper by M.A. Rahman and H.
;Feyasurya published in 'the IEEE Transacti.ans oyv. power ~~~.~.~e~yr Volv .girl ~~'n ~~I ~p~.L~ 19UU..
Appendix A is a paper deli~rered by the in'rentors to the Ga~eadian Elect: ical Association in March 26-29I 1990 at Montreal. S~uebec, Canadar detailing test results of the present protective relay system. Appendix F3 is a paper, delivered by the inventors to the TEEE PES Eu.rnrner Meeting Jury 7-14, 1989 at Long ~eachr Ca.li~ornia, ~ U. S.A. , detailed some test results of the present projective relay system.
Accordingly, the present invention provides a pro 2o tective relay apparatu:~ for proter_ting electrical power devices from damage due to conditions of ervercurrent, ground fault, through-fault, and the like, by producing a signal indicative of at least one o:~ the r_r~nditions to .cause interruption of flow of electrical current to the electrical power devices comprising: electrical current sensing means; sample-and-hall means for sampling the electrical current; a.na,log--tc~-digital co:wc~rter means for d::~r~itally encoding the sampled current; and digital pro cessing means for analyzing ;:he dligitally encoded current 30 ir, a predetermined manner to identify at l~:ast ore of the ccnditians .and produce the signal.
In on,e feature of the protacti.ve relay apparatus, the electrical current sensing means cosnprisiny current tran5-zt~~e~~e former means for sensing electrical current flow through the electrical power device, and second current trans-former means for sensing ground fault current in the e7lectrical power device. The protective relay apparatus may further include Iow pass filter means intermediate the first and second current transformer means and the sample-and-hold means.
In another feature of the protective relay apparatus, the digital processing means comprising stored program 1o means for storing encoded current samples provided in sequence by the analog-to-digital converter means and calculating from the stored encoded current samples dif-ferential, through, and ground fault currents sense by th~~ first and second current transformer means.
The present invention also provides a method for protecting an electrical power device, comprising:
(a) sensing electrical current flow in the power device;
(b;i periodically sampling current sensed in step (a);
(c;~ digitally encoding the current sampled in step (b);
20 (d;~ analyzing the digitally encoded current in a pre-determined manner to determine instantaneous values of fundamental, second harmonic, and fifth harmonic com-ponents thereof; and (e) comparing the second and fifth harmonic components to the fundamental component in a pr~e~determined manner to indicate a fault condition.
In one feature of the method for protecting an electrical power device, the method further comprises the following step between steps (c) and (d): analyzing the digitally encoded current by calculating differential, 3o through, and ground fault cur rents in the electrical Bower device. Step (d) comprises applying a predetermined dis-crete fourier transform to compute the instantaneous values of fundamental, second harmonic, and fifth harmonic 20 x.9939 c<>mponents. Step (al further includes the step of incre-me~nting fault-count associated with a predetermined fault condition when the fault: condition is indicated and of resetting the fault-count: when the fault condition is not indicated.
In another feature of the method for protecting the e~.ectrical power device, the method further includes the fol lowing step: ( f ) examining the fault-count and causing a trip signal to be sent to cause interruption of electri-ca~l power to the electrical power device when the fault-to oouwt exceeds a predetermined threshold.
In the accompanying drawings, Figure 1 is a block schematic of the apparatus of the present invention connected to the power transformer protected;
Figure 2 is a more detailed block schematic of the data acquisition circuits shaven in Figure 1;
Figure 3 is a more detailed block schematic of the signal processing circuits shown in Figure 1; and Figure 4 is a flow-chart of the method and software 20 implementing ail 'the protections in the signal processing circuits shown in Figure 3.
Figure 1 of the drawings shows the block schematic of the digital protective relay apparatus and its con-nection to a protected power transformer 10. By way of example, the power.transformer ZO is a 5 kVA deltalstar three-phase power transforrner having three primary coils 11. 12, and 13 connected :i.n a delta configuration, and having three secondary coils 14, 15, and 16 connected in a star configuration. The three primary windings 11, 12, 30 and 13 are connected to a three-phase power source through three triac circuit breakers 17, 18, and 19 by means of input terminals a, b, and c. In order to sense 'the three x!718938 g -primary currents ila, ilb and ilc there are three corres-ponding current transformers 20, 21, and 22 in a star con-figuration for sensing the primary currents between the triacs 17, 18, and 19 and the primary windings 11, 12, and 13. Likewise, the secondary or load currents of the .secondary windings 14, 15, and 16 are sensed by three current transformers 23, 24, and 25, which are connected :in a star configuration to sense the currents in the :respective leads between the secondary windings and a l0 three-pole circuit breaker 26 which connects and discon-nects the secondary power to a three-phase load 27, which rnay of course be a remote load. Current flowing from 'the common point of the three secondary windings 14, 15, and .L6 to the ground (GND) is sensed by a further current t-ransformer 28. Thus, the current transformers 20, 21, 2, 23, 24, 25, and 28 provide a voltage each across shunt Resistors 20a, 21a, 22a, 23a, 24a, 25a and 28a, which is proportional to the respective current. The three ~~econdary currents are designated i2a~ i2b' and i2c and 20 flow from the secondary windings 14, 15, and 16, respec-tively. The ground current sensed by cureent transformer s!8 is designated i2g . Up to this point the described part of L~'igure 1 corresponds to conventional arrangements for power transformers and their connections.
The currents induced in the seven current trans-formers 20 to 25 and ~28 comprise the seven inputs to data acquisition circuits 29, t:he output of which is processed t~y signal processing circuits 30 which, when necessary, outputs a trip signal to cause the triacs 17, 18, and 19, 30 and, when so desired, the circuit breaker 26, to discon-nect the input power at terminals a, b, and a to the transformer 10 (and also t:o disconner_t the load 27), thus protecting the transformer 10 from damage due to shorts and over currents.
2~~.8938 - g The data acquisition circuits 29 comprise three sub-components, namely, a scaler and anti-aliasing low pass filter 31; a sample-and-hold circuit 32; and a multiplexer 33. The signal processing circuits 30 comprise an analog-to-digital converter 34, a digital signal processor 35, and a sampling clock 36.
In Figure 2 the seven analog signals from the current transformers 20 to 25 and 28 are applied each to the non-inverting input of an associated operational amplifier 37 1o to 43, each of which is adjusted by the variable resis-tance thereacross to scale the current 'transformers signal.
at its input to be compatible with the analog-to-digital converter 34 which ultimately processes it, and also to compensate for any gain sarrors in signal paths between the seven channels in the data acquisition circuits 29. The output of each operational amplifier is applied to an anti-aliasing low pass filter 44 to 50, the output of which is applied to a corresponding sample-and-hold circuit 51 to 57. Accordingly, due to the use of the 20 seven parallel sample-and-hold circuits 51 to 57, the corresponding three primary, three secondary, and one ground current picked-up by the current transformers 20 to 25 and 28 are sampled simultaneously during the same sampling interval. The: output of the sample-and-hold circuits 51 to 57 are multiplexed in a multiplexer 58 and appear in time sequence at its output to be applied to the analog-to-digital (A/D) converter 34. The anti-aliasing low pass filter 44 to 50~ is shown in detail in Appendix A Figure 4.
30 Turning now to Figure 3, the sampled analog signals supplied by the multiplexes 58 (in Figure 2> are input to the analog-to-digital converter 34, the encoded 12-bit output of which is applied to a data bus by means of two ~~18~38 tri-state buffers 59 and 60, which are necessary due to the fact that the A/D converter 34 is not fast enough to be interfaced directly with a digital signal processor 35.
'she processor 35 also interfaces its addressing and con-trol functions by means of a digital output port 61, which aupplies the three address bits A0, A1, and A2 to control ir_he multiplexes 58. A crystal 62 oscillating at a fre-duency of 15,36 kHz supplies that frequency to a divider fi3 which then provides the sampling clock of 960 HZ to c;ach of the sample-and-hold circuits 51 to 57, as well as i:o the processor 35 via :interrupt latch 64. All of the devices shown in Figure 3 are generally well known in 'the art and commercially available. And while a general pur-~~ose microprocessor could be used as the signal processor ~~S complex hardware would be required including multiple ~~rocessors. The preferred processor 35 is a device avail-able from Texas Instruments under Part No. TMS 320E15, which has an on-chip program memory of 4 k words and a data memory of 256 words, which is quite sufficient to 2p implement the software shown in flow chart form in Figure 9 without necessitating external memory use and interface .
The operation of the system and the method of the F~resent invention will now be described with particular reference to the f low chart of Figure 4 . At the star t (65) the system is initialized (66) by the processor 35, whereupon the circuit breakers 17, 18, and 19 are closed by sending a logic "high" on the trip signal lead 67.
The processor 35 then waits for an interrupt ( 68 ) . At the falling edge of the sampling clock the sampled 30 current transformer signals are held and, at the same time, the processor 35 is interrupted and selects (69) one of the seven channels via the multiplexes 58, which is then applied to the analog-to-digital converter 34.
The latter, after approximately 22 microseconds, outputs the 12-bit word to be read (71) by the processor 35.
These three steps (69, 70, and 71) are repeated seven times until all the helci samples in the sample-and-hold circuits 51 to 57 have been applied to the A/D converter 34 and read by the processor 35. The processor 35 then calculates the differential, the through, and the ground fault currents .(72). This computation is performed by the processor 35 in accordance with the three sets of l0 formulas (1), (21, and (3) given on page 2 of Appendix A
hereto. Once the calculation in step 72 is completed, the system then checks whether or not it should effect instantaneous tripping of the circuit breakers (73). A
trip command is given only if any one of the differential currents calculated in step 72 exceeds, and remains above, a predetermined threshold, for two consecutive samples.
If no tripping command is. issued as the result of step 73 then the program proceeds and calls on the discrete Fourier transform (DFT) to compute the fundamental, the 20 second, and the fifth harmonic components of the three differential currents determined in step 72, and computes therefrom the combined harmonic components ID21, ID22, and ID25 (as per equation (6) given on page 3 of the Appen-dix). Having computed and stored the requisite Com-ponents, the system moves to Check for the second harmonic restraint (75). This is accomplished by computing the square of a threshold of 0.1767 (17.67%) times ID2~ and if this product exceeds ID'1 then an in-rush Condition is declared and the program branches to call the ground relay 30 routine in step 80. If an in-rush condition is not .declared then the system proceeds to step 76 to check for 'the fifth harmonic restraint condition. This condition is checked by multiplying the squaz-e of a threshold of ~~1~938 0 .125 ( 12 . 5% ) by ID25 and if the product exceeds ID21 then .3n overexcitation condition is declared and a predeter-mined upper pick-up value C'o is selected (77), otherwise ,3 predetermined lower value Co is selected 178). These ~~alues Co and C'o correspond to two differential current ~~alues in the percentage differential characteristic (PDC), (for example, as shown in Figure 1 in Appendix A).
'.ehe percentage differential characteristic is called ( 79 ) and is checked as follows:
l0 No trip is declared if 'the fundamental primary differential current Id''(a,b,c)1 does not exceed the selected value, Co2 or C'o2 (78). If Id'(a,b,c)1 exceeds ~t:he selected value and if the fundamental through-current 7:t2(a,b,c)1 does not exceed the value of (1 PU)2' then a l:ault is declared. On the other hand if It2 (a,b,c), Exceeds the value of (1 P1:1)2 and then if Id2(a,b,c)1 also exceeds C2,xI2t (a,b,c, ) 1, no fault is declared. Otherwise << fault is declared. 11?11 corresponds to the value of rated primary current of the Bower transformer and C1=
20 (1.125 (12.5% slope). Thus, PDC is checked three times, one for each phase a,b, anal c. If fault is declared, then t;he fault counter of the particular phase is incremented, otherwise it is reset.
The system then proceeds to check for the presence of any primary ar secondary ground fault ( 80 ) . This check i.s performed with a second harmonic restraint as explained s~bove, but with a threshc>ld of . 088 ( 8 . 8% ) . The reason f.'or using the harmonic restraint in addition to threshold restraint here is that they ground relay is found to oper-30 a,te when the cure ent transformers saturate during in-rush a.nd through-fault conditions. During a through-fault, large second and higher order harmonics are present in the clround fault current, whereas during ground fault of 2~J18938 either primary or secondary, the second and higher order harmonics are very low. Hence with this harmonic restraint, the ground relay is able to differentiate between a through-fault and a ground fault, as a result the sensitivity of the: ground relay may be adjusted as desired by varying they pick-up value Cat~ If a ground fault is declared in step 80, then the program increments the corresponding fault: counter, but if a ground fault is not declared, the counter is reset. The program then moves to step 81 where all the fault counters are checked 1o to see if any one of them exceeds a preset value Td (Td = 1 for the differential relay; Td = 5 for the ground relay) , in which case a trip signal is sent to the circuit breakers (82?. After a trip signal has been issued, the system waits in a loop until the reset button is pressed (83) to restart operation. If as the result of the check-ing of the fault counters none exceeded the predetermined threshold Td then the program branches back into step 68 to wait for an interrupt to commence selecting the chan-nels by means of multiplexes 58, and the cycle resumes.
Claims (17)
1. A stand alone protective relay apparatus for protecting an electrical power device from damage due to conditions of overcurrent, magnetizing in-rush current, over-excitation voltage, saturation, ground fault, internal faults, mismatched ratio error for external fault outside the device, current, internal fault and in-rush occurring both independently and simultaneous, said stand alone protective relay apparatus comprising:
means for sensing electrical current;
means for sampling and holding said electrical current;
filtering apparatus, operatively connected to said means for sensing and said means for sampling and holding;
analog-to-digital converter means for digitally encoding the sampled current;
digital processing means for analyzing the digitally-encoded current to identify at least one of the said conditions; and digital output interruption signal-producing means for producing an actuation signal for a digital power switching device, upon the identification of at least one of the said conditions, to cause an interrupt of a flow of electrical current to said electrical power device.
means for sensing electrical current;
means for sampling and holding said electrical current;
filtering apparatus, operatively connected to said means for sensing and said means for sampling and holding;
analog-to-digital converter means for digitally encoding the sampled current;
digital processing means for analyzing the digitally-encoded current to identify at least one of the said conditions; and digital output interruption signal-producing means for producing an actuation signal for a digital power switching device, upon the identification of at least one of the said conditions, to cause an interrupt of a flow of electrical current to said electrical power device.
2. The protective relay apparatus as defined in claim 1, said means for sensing electrical current including a first current transformer means for sensing electrical current flow through said electrical power device, and a second current transformer for sensing ground fault current in said electrical power device.
3. The protective relay apparatus as defined in claim 2, wherein said filtering apparatus includes a low pass filter means operatively connected between said first and second current transformers and said means for sampling and holding.
4. The protective relay apparatus as defined in claim 3, further comprising multiplexer means operatively connected between said means for sampling and holding and said analog-to-digital converter means for applying to said analog-to-digital converter means sampled current signals in sequence.
5. The protective relay apparatus as defined in claim 4, said digital processing means comprising at least one stored program for storing encoded current samples provided in sequence by said analog-to-digital converter means and calculating from said stored encoded current samples differential, through, and ground fault currents as sensed by said first and second current transformers means.
6. A method for protecting an electrical power device having an electronic/electrical circuit breaker therein, said method comprising:
(a) sensing electrical current flow in said power device;
(b) periodically sampling current sensed in step (a);
(c) digitally encoding the current sampled in step (b);
(d) analyzing the digitally encoded current in a predetermined manner to determine instantaneous values of fundamental, second harmonic, and fifth harmonic components thereof;
and (e) comparing said second and fifth harmonic components to said fundamental component in a predetermined manner to indicate (i) a fault condition, and, if said fault condition is indicated, then to initiate an output trip signal to said electronic/electrical circuit breaker tripping said circuit breaker; or (ii) an in-rush condition and, if said in-rush condition is indicated, then to initiate an output non-trip signal or restraint signal to said electronic/electrical circuit breaker so that said circuit breaker remains open; or (iii) at least one of an over-excitation voltage, saturation, and ratio-error condition and, if said condition is indicated then to initiate a tripping signal, tripping said electronic/electrical circuit breaker; or (iv) at least one of an over-excitation voltage saturation and ratio conditions and, if said condition is indicated then to initiate an alarm signal actuating an alarm.
(a) sensing electrical current flow in said power device;
(b) periodically sampling current sensed in step (a);
(c) digitally encoding the current sampled in step (b);
(d) analyzing the digitally encoded current in a predetermined manner to determine instantaneous values of fundamental, second harmonic, and fifth harmonic components thereof;
and (e) comparing said second and fifth harmonic components to said fundamental component in a predetermined manner to indicate (i) a fault condition, and, if said fault condition is indicated, then to initiate an output trip signal to said electronic/electrical circuit breaker tripping said circuit breaker; or (ii) an in-rush condition and, if said in-rush condition is indicated, then to initiate an output non-trip signal or restraint signal to said electronic/electrical circuit breaker so that said circuit breaker remains open; or (iii) at least one of an over-excitation voltage, saturation, and ratio-error condition and, if said condition is indicated then to initiate a tripping signal, tripping said electronic/electrical circuit breaker; or (iv) at least one of an over-excitation voltage saturation and ratio conditions and, if said condition is indicated then to initiate an alarm signal actuating an alarm.
7. The method for protecting an electrical power device as defined in claim 6 further comprising the following step between steps (c) and (d): analyzing the digitally encoded current by calculating differential, through, and ground fault currents in said electrical power device.
8. The method for protecting an electrical power device as defined in claim 7, wherein step (d) comprises applying a predetermined discrete fourier transform to compute said instantaneous values of fundamental, second harmonic, and fifth harmonic components.
9. A stand alone protective relay apparatus for protecting an electrical power device from damage due to conditions of overcurrent, magnetizing in-rush current, over-excitation voltage, saturation, ground fault, internal faults, mismatched ratio error for external fault outside the device, current, internal fault and in-rush occurring both independently and simultaneous, said stand alone protective relay apparatus comprising:
means for sensing electrical current;
means for sampling and holding said electrical current;
filtering apparatus, operatively connected to said means for sensing and said means for sampling and holding;
analog-to-digital converter means for digitally encoding the sampled current;
digital processing means for analyzing the digitally-encoded current to identify at least one of the said conditions; and digital output interruption signal-processing means for producing an actuation signal for a digital power switching device, upon the identification of at least one of the said conditions, to cause an interrupt of a flow of electric current to said electrical power device;
wherein said signal trips an electric/electrical circuit breaker resulting in the interrupt of electrical current to said electrical power device.
means for sensing electrical current;
means for sampling and holding said electrical current;
filtering apparatus, operatively connected to said means for sensing and said means for sampling and holding;
analog-to-digital converter means for digitally encoding the sampled current;
digital processing means for analyzing the digitally-encoded current to identify at least one of the said conditions; and digital output interruption signal-processing means for producing an actuation signal for a digital power switching device, upon the identification of at least one of the said conditions, to cause an interrupt of a flow of electric current to said electrical power device;
wherein said signal trips an electric/electrical circuit breaker resulting in the interrupt of electrical current to said electrical power device.
10. A method of protecting an electrical power device with circuit breakers contained therein, said method comprising the steps of:
(a) actuating the power device and closing the circuit breakers;
(b) sensing and periodically sampling current in said power device a plurality of times;
(c) calculating the differential of through and ground fault currents;
(d) determining after step (c) is completed, if the circuit breakers should be tripped; and (e) tripping said circuit breakers by giving a tripping command to said circuit breakers.
(a) actuating the power device and closing the circuit breakers;
(b) sensing and periodically sampling current in said power device a plurality of times;
(c) calculating the differential of through and ground fault currents;
(d) determining after step (c) is completed, if the circuit breakers should be tripped; and (e) tripping said circuit breakers by giving a tripping command to said circuit breakers.
11. The method of claim 10, wherein said plurality of times in step (b) is seven.
12. The method of claim 10 wherein said tripping command is given when one of the differential currents calculated in step (c) remain above a predetermined threshold for two consecutive samples.
13. A stand alone self contained protective relay apparatus relay for protecting a transformer from damage due to conditions of overcurrent, magnetizing in-rush current, over-excitation voltage saturation, ground fault, internal faults, mismatched ratio error for external fault said protective relay comprising:
(a) data acquisition circuits for receiving and processing current from a plurality of transformers;
(b) signal processing circuits connected to said data acquisition circuits said signal processing circuits processing signals from said data acquisition circuits for sending tripping signals; and (c) circuit breakers receiving said tripping signals so that current to said transformers are interrupted upon receipt of said tripping signals.
(a) data acquisition circuits for receiving and processing current from a plurality of transformers;
(b) signal processing circuits connected to said data acquisition circuits said signal processing circuits processing signals from said data acquisition circuits for sending tripping signals; and (c) circuit breakers receiving said tripping signals so that current to said transformers are interrupted upon receipt of said tripping signals.
14. The protective relay apparatus according to claim 13, wherein said data acquisition circuits include:
(a) a scaler and low pass filter;
(b) a sample and hold circuit; and
(a) a scaler and low pass filter;
(b) a sample and hold circuit; and
15. The protective relay apparatus of claim 14, wherein said signal processing circuit includes:
(a) an analog to digital converter;
(b) a digital signal processor; and (c) a sampling clock.
(a) an analog to digital converter;
(b) a digital signal processor; and (c) a sampling clock.
16. The protective relay apparatus according to claim 15, wherein there are two tri-state buffers connected between said analog to digital converter and said signal processor.
17. The protective relay apparatus according to claim 14, wherein said scaler includes at least one operational amplifier connected to a variable resistor for adjusting the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2018938 CA2018938C (en) | 1990-06-13 | 1990-06-13 | Microprocessor-based stand-alone digital protective relay for power transformers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2018938 CA2018938C (en) | 1990-06-13 | 1990-06-13 | Microprocessor-based stand-alone digital protective relay for power transformers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2018938A1 CA2018938A1 (en) | 1991-12-13 |
| CA2018938C true CA2018938C (en) | 2002-01-08 |
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ID=4145216
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2018938 Expired - Fee Related CA2018938C (en) | 1990-06-13 | 1990-06-13 | Microprocessor-based stand-alone digital protective relay for power transformers |
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| Country | Link |
|---|---|
| CA (1) | CA2018938C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3157112A1 (en) * | 2015-10-12 | 2017-04-19 | General Electric Technology GmbH | Improvements in or relating to the protection of power transformers |
-
1990
- 1990-06-13 CA CA 2018938 patent/CA2018938C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3157112A1 (en) * | 2015-10-12 | 2017-04-19 | General Electric Technology GmbH | Improvements in or relating to the protection of power transformers |
| WO2017064148A1 (en) * | 2015-10-12 | 2017-04-20 | General Electric Technology Gmbh | Improvements in or relating to the protection of power transformers |
| CN108141031A (en) * | 2015-10-12 | 2018-06-08 | 通用电器技术有限公司 | The improvement of power trans-former protection or related improvement |
| CN108141031B (en) * | 2015-10-12 | 2020-11-24 | 通用电器技术有限公司 | Improvements in or relating to protection of power transformers |
| US10916932B2 (en) | 2015-10-12 | 2021-02-09 | General Electric Technology Gmbh | Protection of power transformers |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2018938A1 (en) | 1991-12-13 |
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