CA2016407C - Logic tracking interface circuit - Google Patents
Logic tracking interface circuitInfo
- Publication number
- CA2016407C CA2016407C CA 2016407 CA2016407A CA2016407C CA 2016407 C CA2016407 C CA 2016407C CA 2016407 CA2016407 CA 2016407 CA 2016407 A CA2016407 A CA 2016407A CA 2016407 C CA2016407 C CA 2016407C
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- comparator means
- input
- feedback
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
- H03K19/018542—Interface arrangements of Schottky barrier type [MESFET] with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
A logic tracking interface circuit includes a signal comparator, a feedback comparator and a logic gate of the type to be driven by the interface circuit. The mean of the inverting and noninverting outputs of the signal comparator is applied as an input to the feedback comparator, the other input being provided by the logic gate. The inverted output of the feedback comparator is used to control the common mode of the signal comparator.
Description
- 1 - 2016 ~07 LOGIC TRACKING INTERFACE CIRCUIT
This invention relates to logic tracking interface circuits and is particularly concerned with such circuits for high-speed for critical timing applications.
Interface circuits are used whenever data has to enter or leave an integrated circuit or within an integrated circuit when different logic families are used.
A known form of input circuit is based on a comparator which has as inputs the incoming signal and either a 0 reference voltage or a complementary incoming signal. The output or outputs from the comparator then drive the logic internal to the integrated circuit through appropriate level shift devices.
For an application in which high-speed or critical timing is required, the common-mode output of the comparator must be m;n;m; zed. For a range of input voltages, common-mode output may cause the complementary outputs from the comparator to be both high or both low.
This may lead to timing distortion of a time-varying input.
- 20 A known method of reducing the effects of common-mode output is the use of common-mode feedback. With common-mode feedback, the mean of the inverting and non-inverting outputs from the comparator is used to control the comparator. However, this method may suffer from sensitivity to power supply and manufacturing process variations. This sensitivity arises from the fact that any changes in the logic levels will change the value of the mean and cannot be differentiated from changes in the common-mode output.
An object of the present invention is to provide an improved logic tracking interface circuit.
A logic tracking interface circuit comprising a signal comparator means having first and second signal inputs, a control input, and first and second outputs; a potential divider, connected between the first and second outputs of the signal comparator means, for providing a mean signal value; and a feedback comparator means, having first and -f - 2 - 2016~07 second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the mean signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means; wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
lo An advantage of the present invention is its accommodation of process variations and temperature and supply voltage fluctuations.
According to the present invention a second comparator, a feedback comparator, is provided which compares the mean output from the signal comparator with the decision voltage obtained from a sample logic gate of the type being driven by the input circuit.
The present invention will be further understood from the following description with reference to the drawings in which:
Fig. 1 schematically illustrates a logic tracking interface circuit in accordance with a first embodiment of the present invention; and Fig. 2 schematically illustrates a logic tracking interface circuit in accordance with a second embodiment of the present invention.
Referring to Fig. 1, there is illustrated an embodiment in accordance with the present invention including a signal comparator 10, having positive and negative inputs 12 and 14, respectively, non-inverting and inverting outputs 16 and 18, respectively, and common-mode control input 20, a feedback comparator 22 having positive and negative inputs 24 and 26, respectively, and an inverting output 28 and an inverting logic gate 3Q.
Ideally, the signal comparator 10 includes level shifters (not shown in Fig. 1) to produce appropriate output levels.
A pair of resistors 32 and 34 are serially connected between the outputs 16 and 18 of the signal comparator 10. A junction 36 between the resistors 32 and 34 is connected to the positive input 24 of the feedback comparator 22. An optional capacitor 38 (shown in broken line) may be connected between the junction 36 and ground. The negative input 26 of the feedback comparator 22 is connected to the output of the inverting logic gate 30. The inverting output 28 of the feedback comparator 22 is connected to the common-mode control input 20 of the signal comparator 10. The input of the inverting logic gate 30 is connected via a capacitor 40 to ground. A resistor 42 is connected between the input and output of the inverting logic gate 30.
In operation, the resistors 32 and 34 are used to obtain a mean of the signal levels at outputs 16 and 18 of the signal comparator 10.
The mean is then input to the feedback comparator 22. The other input to the feedback comparator 22 is provided by the inverting logic gate 30 with feedback to produce a steady output of its decision level (i.e. that voltage for which the inverted output equals the input causing it). The inverted output 28 of the feedback comparator 22 drives the common-mode control 20 of the signal comparator 10.
Suppose that the signal comparator 10 produces outputs with a high bias (i.e. both outputs high during part of the input transition), then the mean output level fed into the feedback comparator 22 turns down the common-mode of the signal comparator 10. Similarly, a low common mode will result in the common-mode being increased by the feedback comparator 22.
The advantage of this circuit over conventional common-mode feedback can be seen when variations in the logic due to temperature, supply voltage or processing are considered. In this case, the actual decision level is fed into the feedback comparator 22 and adjusts the common mode of the signal comparator 10 to realign the output signals.
As long as the high and low levels coming from the signal comparator 10 are the same for both the noninverted and inverted outputs 16 and 18, the operation of this circuit does not depend on any property of the input signal. To work properly, the decision level must be equal to the mean of the high and low signal levels; if this is not the case a certain amount of overdrive must be provided by the outputs from the signal comparator 10.
A second embodiment in accordance with the present invention is schematically illustrated in Fig. 2. An ECL
(emitter coupled logic) to BFL (buffered FET logic) logic tracking input circuit is provided using depletion-mode GaAs MESFET (metal schottky field effect transistor) technology. The circuit includes a signal comparator 50, a feedback comparator 90 and a BFL inverting logic gate 120.
The signal comparator 50 includes inputs 52 and 54 and outputs 56 and 58. To the inputs 52 and 54 may be applied o either data and a reference voltage or differential data.
The inputs 52 and 54 are connected to gates of a differential MESFET pair 60 and 62, respectively. Current source corrected MESFETs 64 and 66 are loads which convert changes in MESFET 60 and 62 currents, respectively, to voltages changes. Source followers 68 and 70 provide current gain, and outputs are level shifted by connection via diode chains 72, 74, 76 and 78, 80, 82, respectively, to MESFET pulldown current sources 84 and 86, respectively.
The outputs 56 and 58 are non-inverting and inverting, respectively.
The feedback comparator 90 has inputs 92 and 94 which are buffered and level shifted by a MESFET 96 and diodes 98, 100 and 102, and MESFET 104 and diodes 106, 108, and 110, respectively, before being applied to a differential pair of MESFETs 112 and 114. The differential pair 112 and 114 direct a portion of current from a current source MESFET 116 to common sources of the differential pair 60 and 62 of the signal comparator 50. The differential pair 112 and 114 are also connected to MESFET pulldown current sources 118 and 119, respectively.
The BFL inverting logic gate 120 is of the type used internally in the circuit interfaced by the logic tracking circuit. The BFL inverting logic gate 120 includes an input 122 connected to a gate of MESFET 124. A current source corrected MESFET 126 acts as a load which converts changes in the MESFET 124 current to voltage changes. A
source follower MESFET 128 provides current gain and is R
.~`
-4a - 2016407 connected to an output 130. A level shifted output 132 is provided by connection of the output 130 to a MESFET
pulldown current source 134 via diodes 136, 138, and 140, the output 132 being connected between the diode 140 and the MESFET 134. A diode 142 is arranged as the stabilizing capacitor, connected between the input 122 and the output 132, in place of the capacitor 40 of Fig. 1. Connecting the diode 142 to the output 132 rather than to ground as shown in Fig. 1 increases its ~' .
2016~07 effective capacitance due to the Miller effect, thereby allowing the use of a physically smaller diode. Diodes 144 to 158 form a clamp circuit 160 having a junction 162, between the differential pair 60 and 62 of the signal comparator 50. Resistors 164 and 166 are series connected between the noninverting and inverting outputs 56 and 58 of the signal comparator 50. The mean or common-mode output component is taken from the junction between the resistors 164 and 166, and is applied to the input 122 of the BFL inverting logic gate 120.
The input 122 of the BFL inverting gate 120 is also connected to the input 94 to the MESFET 104. The unshifted output 130 of the BFL inverting gate 120 is connected to the junction 162 of the clamping circuit 160. Connection of the output 128 to the differential pair 60 and 62 via the clamp circuit 160 limits the unshifted output levels to within two forward diode drops of the potential of the output 130. The output 132 of the BFL inverting gate 120 is connected to the input 92 of the MESFET 96. Connecting the BFL
inverting logic gate 120 in this manner instead of as shown in Fig. 1, allows its gain to be added to that of the feedback comparator 90, resulting in a circuit less sensitive to process and power supply variations.
In operation, suppose that a perturbation results in the potential at the junction between the resistors 164 and 166 rising.
This rising potential causes a fall in the potential of outputs 130 and 132 of the BFL inverting logic gate 120. Reducing the potential at the output 130 lowers the output levels of the differential pair 60 and 62 via the clamping effect, but the loop gain in this path is only that of the BFL inverter. A higher potential value at the junction between the resistors 164 and 166 and a lower value at the output 132 of the BFL inverting logic gate 120 when applied to the feedback comparator 90 increases the portion of the current from the current source MESFET 116 that is fed to the signal comparator 50. The action of increasing the current to the differential pair of MESFETs 112 and 114 is to lower the common-mode voltage. The clamping circuit 160 prevents static levels from deviating from their desired values, so the major effect of the current control is to adjust the behaviour during signal changes, minimizing the time when both outputs are in ~O``I6~07 -the same state and thereby improving the high frequency performance of the interface.
While the embodiment of Fig. 2 uses depletion mode GaAs MESFET
technology, depletion mode metal silicon field effect transistor technology may be used.
Numerous modifications, variations and adaptations may be made to the particular embodiments of the invention described above without departing from the scope of the invention, which is defined in the claims.
This invention relates to logic tracking interface circuits and is particularly concerned with such circuits for high-speed for critical timing applications.
Interface circuits are used whenever data has to enter or leave an integrated circuit or within an integrated circuit when different logic families are used.
A known form of input circuit is based on a comparator which has as inputs the incoming signal and either a 0 reference voltage or a complementary incoming signal. The output or outputs from the comparator then drive the logic internal to the integrated circuit through appropriate level shift devices.
For an application in which high-speed or critical timing is required, the common-mode output of the comparator must be m;n;m; zed. For a range of input voltages, common-mode output may cause the complementary outputs from the comparator to be both high or both low.
This may lead to timing distortion of a time-varying input.
- 20 A known method of reducing the effects of common-mode output is the use of common-mode feedback. With common-mode feedback, the mean of the inverting and non-inverting outputs from the comparator is used to control the comparator. However, this method may suffer from sensitivity to power supply and manufacturing process variations. This sensitivity arises from the fact that any changes in the logic levels will change the value of the mean and cannot be differentiated from changes in the common-mode output.
An object of the present invention is to provide an improved logic tracking interface circuit.
A logic tracking interface circuit comprising a signal comparator means having first and second signal inputs, a control input, and first and second outputs; a potential divider, connected between the first and second outputs of the signal comparator means, for providing a mean signal value; and a feedback comparator means, having first and -f - 2 - 2016~07 second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the mean signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means; wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
lo An advantage of the present invention is its accommodation of process variations and temperature and supply voltage fluctuations.
According to the present invention a second comparator, a feedback comparator, is provided which compares the mean output from the signal comparator with the decision voltage obtained from a sample logic gate of the type being driven by the input circuit.
The present invention will be further understood from the following description with reference to the drawings in which:
Fig. 1 schematically illustrates a logic tracking interface circuit in accordance with a first embodiment of the present invention; and Fig. 2 schematically illustrates a logic tracking interface circuit in accordance with a second embodiment of the present invention.
Referring to Fig. 1, there is illustrated an embodiment in accordance with the present invention including a signal comparator 10, having positive and negative inputs 12 and 14, respectively, non-inverting and inverting outputs 16 and 18, respectively, and common-mode control input 20, a feedback comparator 22 having positive and negative inputs 24 and 26, respectively, and an inverting output 28 and an inverting logic gate 3Q.
Ideally, the signal comparator 10 includes level shifters (not shown in Fig. 1) to produce appropriate output levels.
A pair of resistors 32 and 34 are serially connected between the outputs 16 and 18 of the signal comparator 10. A junction 36 between the resistors 32 and 34 is connected to the positive input 24 of the feedback comparator 22. An optional capacitor 38 (shown in broken line) may be connected between the junction 36 and ground. The negative input 26 of the feedback comparator 22 is connected to the output of the inverting logic gate 30. The inverting output 28 of the feedback comparator 22 is connected to the common-mode control input 20 of the signal comparator 10. The input of the inverting logic gate 30 is connected via a capacitor 40 to ground. A resistor 42 is connected between the input and output of the inverting logic gate 30.
In operation, the resistors 32 and 34 are used to obtain a mean of the signal levels at outputs 16 and 18 of the signal comparator 10.
The mean is then input to the feedback comparator 22. The other input to the feedback comparator 22 is provided by the inverting logic gate 30 with feedback to produce a steady output of its decision level (i.e. that voltage for which the inverted output equals the input causing it). The inverted output 28 of the feedback comparator 22 drives the common-mode control 20 of the signal comparator 10.
Suppose that the signal comparator 10 produces outputs with a high bias (i.e. both outputs high during part of the input transition), then the mean output level fed into the feedback comparator 22 turns down the common-mode of the signal comparator 10. Similarly, a low common mode will result in the common-mode being increased by the feedback comparator 22.
The advantage of this circuit over conventional common-mode feedback can be seen when variations in the logic due to temperature, supply voltage or processing are considered. In this case, the actual decision level is fed into the feedback comparator 22 and adjusts the common mode of the signal comparator 10 to realign the output signals.
As long as the high and low levels coming from the signal comparator 10 are the same for both the noninverted and inverted outputs 16 and 18, the operation of this circuit does not depend on any property of the input signal. To work properly, the decision level must be equal to the mean of the high and low signal levels; if this is not the case a certain amount of overdrive must be provided by the outputs from the signal comparator 10.
A second embodiment in accordance with the present invention is schematically illustrated in Fig. 2. An ECL
(emitter coupled logic) to BFL (buffered FET logic) logic tracking input circuit is provided using depletion-mode GaAs MESFET (metal schottky field effect transistor) technology. The circuit includes a signal comparator 50, a feedback comparator 90 and a BFL inverting logic gate 120.
The signal comparator 50 includes inputs 52 and 54 and outputs 56 and 58. To the inputs 52 and 54 may be applied o either data and a reference voltage or differential data.
The inputs 52 and 54 are connected to gates of a differential MESFET pair 60 and 62, respectively. Current source corrected MESFETs 64 and 66 are loads which convert changes in MESFET 60 and 62 currents, respectively, to voltages changes. Source followers 68 and 70 provide current gain, and outputs are level shifted by connection via diode chains 72, 74, 76 and 78, 80, 82, respectively, to MESFET pulldown current sources 84 and 86, respectively.
The outputs 56 and 58 are non-inverting and inverting, respectively.
The feedback comparator 90 has inputs 92 and 94 which are buffered and level shifted by a MESFET 96 and diodes 98, 100 and 102, and MESFET 104 and diodes 106, 108, and 110, respectively, before being applied to a differential pair of MESFETs 112 and 114. The differential pair 112 and 114 direct a portion of current from a current source MESFET 116 to common sources of the differential pair 60 and 62 of the signal comparator 50. The differential pair 112 and 114 are also connected to MESFET pulldown current sources 118 and 119, respectively.
The BFL inverting logic gate 120 is of the type used internally in the circuit interfaced by the logic tracking circuit. The BFL inverting logic gate 120 includes an input 122 connected to a gate of MESFET 124. A current source corrected MESFET 126 acts as a load which converts changes in the MESFET 124 current to voltage changes. A
source follower MESFET 128 provides current gain and is R
.~`
-4a - 2016407 connected to an output 130. A level shifted output 132 is provided by connection of the output 130 to a MESFET
pulldown current source 134 via diodes 136, 138, and 140, the output 132 being connected between the diode 140 and the MESFET 134. A diode 142 is arranged as the stabilizing capacitor, connected between the input 122 and the output 132, in place of the capacitor 40 of Fig. 1. Connecting the diode 142 to the output 132 rather than to ground as shown in Fig. 1 increases its ~' .
2016~07 effective capacitance due to the Miller effect, thereby allowing the use of a physically smaller diode. Diodes 144 to 158 form a clamp circuit 160 having a junction 162, between the differential pair 60 and 62 of the signal comparator 50. Resistors 164 and 166 are series connected between the noninverting and inverting outputs 56 and 58 of the signal comparator 50. The mean or common-mode output component is taken from the junction between the resistors 164 and 166, and is applied to the input 122 of the BFL inverting logic gate 120.
The input 122 of the BFL inverting gate 120 is also connected to the input 94 to the MESFET 104. The unshifted output 130 of the BFL inverting gate 120 is connected to the junction 162 of the clamping circuit 160. Connection of the output 128 to the differential pair 60 and 62 via the clamp circuit 160 limits the unshifted output levels to within two forward diode drops of the potential of the output 130. The output 132 of the BFL inverting gate 120 is connected to the input 92 of the MESFET 96. Connecting the BFL
inverting logic gate 120 in this manner instead of as shown in Fig. 1, allows its gain to be added to that of the feedback comparator 90, resulting in a circuit less sensitive to process and power supply variations.
In operation, suppose that a perturbation results in the potential at the junction between the resistors 164 and 166 rising.
This rising potential causes a fall in the potential of outputs 130 and 132 of the BFL inverting logic gate 120. Reducing the potential at the output 130 lowers the output levels of the differential pair 60 and 62 via the clamping effect, but the loop gain in this path is only that of the BFL inverter. A higher potential value at the junction between the resistors 164 and 166 and a lower value at the output 132 of the BFL inverting logic gate 120 when applied to the feedback comparator 90 increases the portion of the current from the current source MESFET 116 that is fed to the signal comparator 50. The action of increasing the current to the differential pair of MESFETs 112 and 114 is to lower the common-mode voltage. The clamping circuit 160 prevents static levels from deviating from their desired values, so the major effect of the current control is to adjust the behaviour during signal changes, minimizing the time when both outputs are in ~O``I6~07 -the same state and thereby improving the high frequency performance of the interface.
While the embodiment of Fig. 2 uses depletion mode GaAs MESFET
technology, depletion mode metal silicon field effect transistor technology may be used.
Numerous modifications, variations and adaptations may be made to the particular embodiments of the invention described above without departing from the scope of the invention, which is defined in the claims.
Claims (13)
1. A logic tracking interface circuit comprising:
a signal comparator means having first and second signal inputs, a control input, and first and second outputs;
a potential divider, connected between the first and second outputs of the signal comparator means, for providing a mean signal value; and a feedback comparator means, having first and second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the mean signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means;
wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
a signal comparator means having first and second signal inputs, a control input, and first and second outputs;
a potential divider, connected between the first and second outputs of the signal comparator means, for providing a mean signal value; and a feedback comparator means, having first and second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the mean signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means;
wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
2. A circuit as claimed in claim 1 wherein the logic gate means includes an inverting logic gate.
3. A circuit as claimed in claim 2 wherein the inverting logic gate has a feedback resistor connected between its input and output.
4. A circuit as claimed in claim 3 wherein the input of the inverting logic gate is capacitively coupled to ground.
5. A circuit as claimed in claim 3 wherein the input of the inverting logic gate is capacitively coupled via a forward biased diode to the feedback comparator means.
6. A circuit as claimed in claim 3 wherein the signal comparator means includes output level shifting means.
7. A circuit as claimed in claim 6 wherein the first input of the feedback comparator means is capacitively coupled to ground.
8. A circuit as claimed in claim 2 wherein the signal comparator means includes depletion mode metal silicon field effect transistors.
9. A circuit as claimed in claim 6 wherein the feedback comparator means includes depletion mode metal silicon field effect transistors.
10. A circuit as claimed in claim 6 wherein the inverting logic gate means includes depletion mode metal silicon field effect transistors.
11. A circuit as claimed in claim 2 wherein the signal comparator means includes depletion mode GaAs MESFETs.
12. A circuit as claimed in claim 6 wherein the feedback comparator means includes depletion mode GaAs MESFETS.
13. A circuit as claimed in claim 6 wherein the inverting logic gate means includes depletion mode GaAs MESFETs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2016407 CA2016407C (en) | 1990-05-09 | 1990-05-09 | Logic tracking interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2016407 CA2016407C (en) | 1990-05-09 | 1990-05-09 | Logic tracking interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2016407A1 CA2016407A1 (en) | 1991-11-09 |
| CA2016407C true CA2016407C (en) | 1996-08-06 |
Family
ID=4144950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2016407 Expired - Fee Related CA2016407C (en) | 1990-05-09 | 1990-05-09 | Logic tracking interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2016407C (en) |
-
1990
- 1990-05-09 CA CA 2016407 patent/CA2016407C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2016407A1 (en) | 1991-11-09 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |