CA2009744C - Pipelined floating-point load instruction for microprocessor - Google Patents

Pipelined floating-point load instruction for microprocessor Download PDF

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Publication number
CA2009744C
CA2009744C CA002009744A CA2009744A CA2009744C CA 2009744 C CA2009744 C CA 2009744C CA 002009744 A CA002009744 A CA 002009744A CA 2009744 A CA2009744 A CA 2009744A CA 2009744 C CA2009744 C CA 2009744C
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CA
Canada
Prior art keywords
data
floating
bus
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA002009744A
Other languages
English (en)
French (fr)
Other versions
CA2009744A1 (en
Inventor
Leslie D. Kohn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CA2009744A1 publication Critical patent/CA2009744A1/en
Application granted granted Critical
Publication of CA2009744C publication Critical patent/CA2009744C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CA002009744A 1989-02-10 1990-02-09 Pipelined floating-point load instruction for microprocessor Expired - Lifetime CA2009744C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30942989A 1989-02-10 1989-02-10
US309,429 1989-02-10

Publications (2)

Publication Number Publication Date
CA2009744A1 CA2009744A1 (en) 1990-08-10
CA2009744C true CA2009744C (en) 2005-06-28

Family

ID=23198201

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002009744A Expired - Lifetime CA2009744C (en) 1989-02-10 1990-02-09 Pipelined floating-point load instruction for microprocessor

Country Status (6)

Country Link
JP (1) JPH02242429A (zh)
AU (1) AU618425B2 (zh)
CA (1) CA2009744C (zh)
DE (1) DE4001165C2 (zh)
FR (1) FR2643166A1 (zh)
GB (1) GB2228116B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438669A (en) * 1991-11-20 1995-08-01 Hitachi, Ltd. Data processor with improved loop handling utilizing improved register allocation
US5673407A (en) * 1994-03-08 1997-09-30 Texas Instruments Incorporated Data processor having capability to perform both floating point operations and memory access in response to a single instruction
US6275904B1 (en) * 1998-03-31 2001-08-14 Intel Corporation Cache pollution avoidance instructions
US7454585B2 (en) 2005-12-22 2008-11-18 International Business Machines Corporation Efficient and flexible memory copy operation
US7506132B2 (en) 2005-12-22 2009-03-17 International Business Machines Corporation Validity of address ranges used in semi-synchronous memory copy operations
US7484062B2 (en) 2005-12-22 2009-01-27 International Business Machines Corporation Cache injection semi-synchronous memory copy operation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
JPS6069746A (ja) * 1983-09-26 1985-04-20 Fujitsu Ltd ベクトル・デ−タ処理装置の制御方式
US4600986A (en) * 1984-04-02 1986-07-15 Sperry Corporation Pipelined split stack with high performance interleaved decode
JPS61160142A (ja) * 1984-12-29 1986-07-19 Hitachi Ltd デ−タ処理装置
US4873630A (en) * 1985-07-31 1989-10-10 Unisys Corporation Scientific processor to support a host processor referencing common memory
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
JPS62115571A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd ベクトルアクセス制御方式
JPS63157235A (ja) * 1986-12-12 1988-06-30 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン コンピユータ・システムの制御装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations
US8769248B2 (en) 1995-08-16 2014-07-01 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

Also Published As

Publication number Publication date
DE4001165C2 (de) 1999-01-21
CA2009744A1 (en) 1990-08-10
AU4561889A (en) 1990-08-16
DE4001165A1 (de) 1990-08-16
JPH02242429A (ja) 1990-09-26
GB2228116B (en) 1993-05-26
GB2228116A (en) 1990-08-15
FR2643166B1 (zh) 1995-03-17
GB8925453D0 (en) 1989-12-28
AU618425B2 (en) 1991-12-19
FR2643166A1 (fr) 1990-08-17

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