CA1280814C - Integrity securing monitor and method for a security installation - Google Patents

Abstract

ABSTRACT

The security of fire, intrusion and other security systems is improved by the disclosed monitor and method for providing an indication of the possible degradation in the integrity of a communications link and of the operability of a security sensor, both parts of the security system, and for removing the indication only in the event of a successful simulation.

Description

-1'~80~314 FIELD OF THE INVENTION

1 The present invention is directed to the field of remote 2 indicationf and more particularly, to a novel intëgrity 3 securing monitor and method for a security installation.
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4 In a typical prior-art security installation one or more security sensors are provided locally about an environment to 6 be secured. The security sensors are responsive to such 7 specific events as an unauthorized intrusion and smoke and~or 8 heat to provide a signal indication of the occurrence of the - 9 event. The signal is applied to an alarm means, and o~ten indicated at a control and alarm center over a communication 11 l~nk. The remote center may be a police station or a central~
12 often computerized, control unit. The communlcation link 13 usually is in the form of electrical wires or, less o~ten, some 14 other telecommunications channel.
The ~unctional integrity of the security installation is a 16 condition precedent to the provision of effective 17 countermeasures intended to circumvent or ameliorate the ' ~, ~'q~ ~j y ', :

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1 threat. Without an adequate notice of the oceurring of the 2 environmental event it is impossible to take responsible action 3 to preserve life or property.

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SUMMARY Of THE INYENTION

4 The monitor and method for securing the integrity of a security installation of the present invention includes a 6 remote control and alarm center, one or more local security 7 sensors for discriminating possible alarm events in the sensed 8 environment, a communication link between the remote control and alarm center and the one or more local security sensors, contemplates means for providing a signal indication of link 11 integrity, means for providing a signal indication of the 12 intrinsic integrity of one or more of the parts of the one or 13 more sensors, and further contemplates means for providing a 14 signal indication of the functional integrity o~ the one or more sensors as environmental event detectors. Means are 16 further contemplated for storing data representative of 17 possible degradation in the integrity either of the links, the 18 one or more sensors as such, and in the discrimina~ing ability 19 o~ the one or more sensors. Means responsive to the data are .
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1 contemplated for signaling the event degradatlon. Means are 2 contemplated responsive to degradation events for re-setting 3 the data only after insuring system operability as by the 4 successful detection of a simulated system detectable event.
The present invention checks the integrity of the 6 communications link and of the intrinsic and extrinsic sensor 7 operation ability, and thus secures the security installation 8 against system mode failures that heretofore have gone 9 undetected. A security installation constructed in accordance ~ith the present invention is much more reliable than 11 heretofore possible, so that the sPcurity of property and life 12 against loss, theft and damage is subs~antially improved.
13 In the preferred embodiment, the integrity securing monitor 14 and method for a secure installation of the present invention includes a motion detection sub-system having a transceiver, a 16 transducer impedance monitoring sub-system connected to the 17 transducer for providing a signal representative of intrinsic 18 and ~xtrinsic transducer fault conditions, and a data latch 19 responsive to the impedance fault signal to store a signal representative of the fault condition. Means are provided ~or 21 reseting the latch only upon the successful simulation of 22 system operation by detection of a walk-test by the motion 23 ~etector.

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BRIEF DESCRIP~IûN Of THE DRAWINGS

: 1 Other features and attendant advantages of the present 2 invention will become apparent as .the invention becomes better 3 understond by referring to the following solely exemplary and 4 non-limiting detailed description of the preferred embodiments thereof, and to the drawings, wherein:

6 Figure 1 is block diagram o~ the integrity securing monitor 7 and method for a security installation according to the present 8 invention; and 9 Figure 2 is a detailed block diagram o~ the presently : 10 preferred embodiment of the integrity securing monitor and 11 method for a security installation according to the present 12 :invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
' . 13 As used herein, the term ~s0curity installation~ primarily 14 means either a fire detection or an intrusion detection system, although the. present invention has utility in other types o~
16 security systems. Referring now to Figure 1, generally .

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1 designated at 10 is a block diagram of the integrity securing 2 monitor and method for a security installation of the present 3 invention. The monitor 10 includes a sensor 12 for sensing 4 predetermined environment events schematically illustrated in the drawings by a box 14. An alarm signal processor 16 6 designated 'ASP', of any type suitable to detect the event and 7 thereby signal an alarm, is connected to the sensor 12. A
8 trouble signal processor 18 designated 'TSP' is connected to g the sensor 17 for providing a fault or trouble signal indication of potential mechanical, electrical, and other 11 sensor intrinsic failure states as well as sensor extrinsic 12 functionality modes. As used herein the term "intrinsic" means 13 the components and specific component subcooperation of the 14 sensor and the term "extrinsic" means the specific sensor functionality. The output of the trouble signal processor 18 16 is connected to the set input of a data latch 20, such as a 17 flip-flop or other memory means. The output of the alarm 18 signal processor 16 is connected through one input of an AND
19 gate 22 or other logic to the falling edge triggered reset input of the latch 20. The other input to the AND gate 22 is 21 an enable signal to be described selectively provided thereto 22 during sensor alarm function simulation. The Q outp~t of the ~LZ~3~)8~4 1 latch 20 is connected to one input o~ an AND gate 24 or other 2 suitable logic. The other input of the AND gate 24 is 3 trouble înhibit signal to be described. A timer circuit 26, 4 operatively coupled to the trouble signal processor 18 and to the alarm signal processor 16, is responsive to a test signal 6I to be described to activate the processors 16, 18 for link 7 integrity determinations in a manner to be described.
8 Sensors 12 are locally distributed about an environmental 9 region to be secured, one being specifically illustrated for concise illustration. A bus 28 carries the alarm and trouble 11 signals to a controller 30 and carries the enable, inhibit, and 12 test signals provided by the controller 30 to the one or more 13 sensors 10.
14 Upon the occurrence of an event capable of being sensed by the sensor 12, the processor 16 discriminates the event and 16 provides an alarm signal to the station 30 representative of a 17 possible threat, whereupon appropriate countermeasures may be 18 initiated. Concurrently with alarm signal processing, the 19 trouble signal processor 18 monitors the intrinsic and extrinsic operability of the sensor 1~. In the event of an 21 intrinsic or extrinsic fault or possible trouble in the 22 operability or possible operability o~ the sensor 12, a trouble , .

~8~ L4 1 signal is produced by the trouble signal processor 18. The 2 latch 20 latches the trouble signal in memory, and the Q output 3 of the latch 20 produces a latched output signal. The latched 4 output signal is passed through the gate 24, and signals the alarm station 30 of a possible trouble or fault condition with 6 respect to the state of the sensor 12. Because the gate 20 is 7 latched, the control unit continues to ~see" the possible 8 trouble situation, until the latch is reset, by a success~ul g demonstration o~ sensor operability to be described.
The central unit 30 executes a simulation sequence to 11 determine s2nsor operability and, as part of the simulation 12 signal, applies an enable signal to the gate 22O While the 3 enable signal is being applied, the sensor 12 is tested, 14 manually, to determine whether or not it properly responds to the functional test situation. If it is properly operative, 16 the ASP 16 is operative to produc~e a simulated alarm signal to 17 the gate 22. The gate 22 then produces, because both its 18 inputs are "high", a signal that resets the latch 20 to its 19 nominal state. The Q output thereo~ goes "low", and the trouble signal is therewith removed.
21 The remote station processor is operative to produce a test 22 signal on the sensor bus 28 to determine the communications ..

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1 integrity o~ the link 28 and included circuit portions. After 2 a predetermined time delay, the timer 26 is operative in 3 response to the test signal to provide ASP 16 and TSP 18 4 outputs that simulate alarm and trouble conditions. The processor 3~ is operative, in response to the simulated alarm 6 and trouble signals occurring appropriately time delayed on the 7 bus 28, to determine that the link 28 and included circuit 8 paths are appropriately functional. If no signal from one or both of the processors 16, 18 appears, or if a signal after the wrong time interval appears, on the bus 28, the processor flags 11 a possible sensor bus failure or communications link fault 12 condition, and appropriate correction is initiated. An inhibit 13 signal is selectively provided on the bus 28 by the 14 controller 30 to inihibit the trouble signal from being applied to the bus 28, ~or example, during the time it takes to have 16 someone go to the location oF the sensor to test its 17 operability.
18 Referring now to Figure 2, generally designated at 34 is a 19 detailed block diagram of the presently preferred embodiment of the integrity securing monitor and method for a security 21 installation according to the present inven~ion. The presently ~2 preferred alarm signal processor is enclosed in a dashed box 36 1~0~

1 and the presently preferred trouble signal processor is 2 enclosed in a dashed box 38. The alarm signal processor 36 is 3 connected via a variable gain amp 40 and a multiplexer 42 to 4 two transceivers 44, 44' alternately operative as a transmitter and as a receiver. The alarm signal processor 36 includes a 6 phase shift network 46 and a phase shift network 48 that are 7 operative in response to the ultrasonic amplified signal 8 produced by the amplifier 40 to provide quadrature ultrasonic 9 detection signals. The quadrature ultrasonic detection signals are mixed with the carrier frequency signal produced by an ll oscillator 50 and synchronously detected to baseband by 12 mixers 52, 54. The quadrature detected baseband signals are 13 individually Doppler bandpass filtered by amplifier and filter 14 circuitry 56, 58. A 90 degree phase relation subsists between the Doppler detected signals.
16 The Doppler quadrature signal produced by the ampli~ier and 17 filter 56 is fed to sample and hold device 60 through a mute 18 switch 62. The mute switch 62 has a duty cycle and frequency 19 so selected by divider 63 as to mute, i.e. dis-able, beat-frequencies, at the transceiver 44, 44' on-to-off 21 transitions, .from producing ~alse alarm signals. The other 22 Doppler quadrature signal produced by the amplifier and a~4 1 ~llter 58 ls ~ed to a symmetr~cal limlter 66, such as a Schmldt 2 trigger then to a pulse shaper 68, and through an invertor 70 3 to the sample enable input o~ the sample and hold 60 as a 4 Doppler synchronous pulse tra~n output. The 90 degrçe phase S relatlon ls processed by the zero crossing detecting Schm~dt 6 trigger'as disclosed in U.S. Patent No. 3,7C0,400.

7 For true intruder .motion either radially towards or away 8 ~rom the ultrasonI.G receiver, the sample and hold circuit 60 9 will be consistently enabled producing a corresponding one o~
Doppler bl-dlrectlonal ultrasonic detection sub-system signals 11 much more o~ten statlstically than random events so that the 12 sample and hold circuit passes the charge to an integrator 70 13 which rapidly bu~lds up to and trips the associated threshold 1q o~ a bi-level comparator generally desi3nated 71 coupled to the output o~ the integrato~ 700 Upon tripping the one o~
16 thresholds, a timer 72 is enabled, and after a predetermined 17 time, the output of the tlmer act~vates the co~l o~ a relay 1a driver 74, and provides an alarm slgnal Indication o~ intruder 19 motion, locally, and over a bus 75 to a remote controller, not shown in Figu~e ~. Re~erence may be had to commonly-assigned, 21 United States Patent No. 4,625,199 issued November 25, 1986 for a 22 refere~ce t~ other.U.S. patents which dis¢lose suitakle alarm .

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1 signal processors, and for a further description o.f the 2 operation of the alarm signal processor quadrature channels, 3 among other things.
4 Acoustical trouble signalling processor 38 includes the frequency divider 63 which is coupled to the multiplexer 42.
6 The divider controlled multiplexer is operative to repetitively 7 switch the transducers 44, 44', alternately to the 8 oscillator 50 and to the alarm signal processing circuit to be 9 described in such a way that while one transceiver is in its transmit mode the other is in its receive mode, and 11 conversely. For example, while the transceiver 44 operative as 12 an uLtrasonic receiver is operatively connected through the ]3 amplifier 40 to the alarm signal processing circuitry 36, the 14 transceiver 44' is operative as an ultrasonic transmitter and is operatively connected to the oscillator 50 through an 16 amplifier 73. For the next cycle of the switching signal 17 applied to the control input of the multiplexer 42, the 18 $ransceiver 44 is oper.ative as an ultrasonic transmitter while 19 the transceiver 44' is operative as an ultrasonic receiver. It will be appreciated that the above process continues 21 synchronously with the output signal of the osci.llator 50 as 22 converted through the multiplexer clock output of the ~requency 23 divider 63.

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1 Each of the transceivers 44, 44' in its transmitting mode 2 has a characteristic electrical impedance that falls within a 3 nominal range of values in normal operation. Such factors as 4 pollutants andtor excessive pressure and temperature changes in the acoustic propagation medium, as well as masking attempts in 6 the nearfield of the transceivers 44, 44', change the acoustic 7 impedance of the propagation medium. Due to the phenomenon of 8 transduction reciprocity, the electrical impedance o~ the transceivers in the transmit mode therewith changes proportionately. Moreover, such electro-mechanical failure 11 conditions as defective vibrating membranes, piezoelectric 12 crystals, and transducer housing cracks, among others, and such 13 electrical ~ailure conditions as open and short circuit 14 conditions, likewise produce detectable changes of the characteristic electrical impedance of the transceivers 44, 441 16 when operatiny in their transmit mode. The trouble signal 17 processor is operative to detect the changes of the 18 chaxacteristic electrical impedances to provide sel~-diagnostic 19 alarm signals in response thereto.
A conventional current mirror circuit 78 is coupled to the 21 oscillator 50 for providing a signaL having a level that is 22 representative of the electrical impedance of the _ 13 -1;~80B~

l transceivers 44, 44 respectively in their transmitting mode.
2 The circuit 78 includes matched transisturs operatively 3 connected as a so-called current mirror, with the collector cf 4 one of the transistors connected to an output of the ; 5 amplifier 73, and with the collector of the other transistor 6 connected through a resistor to a source o~ constant 7 potential. A self-diagnostic impedance is picked off between 8 the resistor and the collector of the other transistor.
9 For a given preselected constant operating drive voltage for the transceivers 44, 44', any acoustically, mechanically, 11 or electrically-induced changes in the electrical impedance o~
12 the transceivers in their transmitting mode produce 13 correspondingly dif~erent currents into the -collector of the 14 first transistor of the current mirror. As will be readily appreciated, the current through the collector of the second 16 transistor mirrors the current through the collector of the 17 first transistor in the so-called ourrent-mirror circuit, and 18 since the voltage dropped through the resistor depends on the 19 current through the second transistor, a voltage signal having a level representative of the electrical impedance of the 21 transceivers 44, 44' in the transmitting mode is thereby 22 produced. If the signal representative of the electrical ~ ~0 8~ ~

1 impedance of the transceivers in the transmitting mode is 2 within prescribed D.C. and A.C. bounds to be described, then 3 both the intrinsic operation and the extrinsic operation, and 4 hence integrity, of the sen~or aspect of the security installation is in order. But if it is in an out-of-bound 6 condition, then this is indicative of potential mechanical, 7 electrical, acoustical, and other sources of failure and false 8 alarm situations, a trouble signal is latched, a test procedure 9 to be described is enabled, and only upon the successful simulation of sensor operability is the trouble indication 11 removed.
12 The signal having a voltage that represents the acoustical 13 impedance of the transceivers 44, 44' in the transmitting mode 14 is connected, on parallel circuit legs, one the one hand to an A.C. window comparator generally designated 80 through a 16 transducer difference compensating circuit generally 17 designated 81, and on the other to a D.C. ~indow comparator 18 generally designated ~2. The difference removing circuit 81 19 includes a demultiplexer 83 and two differentiators 85, 87, one for each o~ the transce.ivers 44, 44'. An adder 89 sums the 21 outputs of the differentiators 85, 87. The circuit 83 keeps 22 the channels of the transceivers separate, so that non-matched _ 15 -.
808~4 1 transceivers, with dif~erent characteristlcs, can thereby be 2 employe~ without falsely indicating an out-of-bounds AC signal 3 component oossible trouble condition.
4 The preselected thresholds Yl, V2 of the comparator 80 are selected to define the upper boundary and the lower boundary o~
6 an alternating current window for detecting out-of-bounds 7 levels of the A.C. component of the voltage signal 8 representative of the electrical impedance of the 9 transceivers 12, 12' in their transmitting mode. Whenever the alternating current components of the Yoltage signal exceed the 11 nominal bounds established by the thresholds, the comparator 80 12 is operative to produce an output signal to indicate an 13 out-of-bounds alarm condition.
13 The D.C. window comparator 82 includes dual, preselected 14 thresholds Vl, V2 selected to define the upper boundary and the lower boundary of a direct current window for detecting 16 out-of-bounds levels of the D~C. components of the signal 17 representative of electrical impedance of the 18 transceivers 44, 44' in the transmitting mode. The 19 comparator 82 is operative in resonse to out-of bounds D.C.
signal component levels to produce output signal indication of 21 the out-of-bounds condition.

~L~8~a~4 l Upon the accurrence o~ events detectable by the acoustic 2 trouble processor 38, a signal is applied to the set input of a 3 data latch 86. The Q nutput o~ the latch 86 is thereby pulsed 4 "high", an~ an output indication of an electronic trouble signal is applied through a transitor switch 88 over the bus 75 6 to the central control processor. The events that are 7 detectable by the acoustic trouble processor 38 include the 8 following intrinsic and extrinsic transceiver operation and 9 environmental items. An open circuit condition such as would be produced by a disconnection of the drive oscillator. A
11 damaged crystal oscillator, no air pressure in the near-field 12 of the transceivers, excessive pollution in the propagation 13 medium of one but not the other Or the transceivers, defective 14 vibrating membranes 9 piezoelectric crystals, or one or more transceiver housing defects of one of the transceivers but not 16 of the other transceiver, atmospheric vapor condensation on the 17 face of one transceiver but not on the other, a short-circuit 18 condition in one transceiver but not in the other, 19 deterioration of one transceiver due to aging and the like but not the other, excessive temperature and pressure conditions 21 and/or excessive polution of the propagation paths o~ both of 2~ the transceivers, a masking attempt, such as by cupping one o~
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~80a~4 1 the transceivers over by hand, among others~ Re~erence may be 2 had to cGmmonly-assigned U.S. Patent No~ 4,647,913 issu~d Mar 3 3, 1987~ or a further de~cription o~ the acoustic trouble 4 processor, and ~or exemplary waveforms illustrative o~ the S operation o~ the acoustic trouble processor.
6 The lntegrity o~ the communications link is pre~erably 7 monitored by the remote con~rol unit by producing a test signal 8 at a predetermined time~ or at predetermined tlmes, which test ~ signal is applied to the sensor bus 75. The test slgnal on the lQ bus ~s coupled by a switch network 90 to the alarm event :~11 timer 72. The t~mer 72 produces a simulated alarm signal in 12 response to the test signalj a~ter elaspe of ~ts time interval, . 13 ~hich alarm signal is applied, through the relay driver 74, to .~14 the bus 75 tor transmission back to the controller. The test . 15 signal, after being selectively delayed, is also switched, by : 16 the switch network 90, to the output port of the latch 86, : 17 which then triggers the trouble output drive 88, and therewith :18 simulates a simulated trouble or fault condition s~gnal back 19 ~er the bus to the central unit at the appropriate time. As 2Q will be appreciated, the above-descrLbed test sequence does not 21 ef~ect the memory latch 86, the state o~ which is transparent ;

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~.~8U814 l to the test signal. The predetermined time delay provided by 2 the alarm event timer 72, it will be appreciated, could be 3 provided by any other timing means~ but the alarm timer is 4 pre~erably employed for this purpose to reduce overalL
component usage. The delay is important, insofar as the back signalling, at the appropriately delayed time, serves to 7 confirm that the system is properly responding to the test 8 signal. It will be appreciated that the test function, in 4 addition to insuring the integrity of the communication link as such, also insures that that portion of the circuitry over ll which the test signal is applied, (that is the test 13gic 12switch 90, the alarm timer 72, the alarm relay driver 74, and 13 electronic trouble output driver 88, in the preferred 14 embodiment) 9 LS also operative in their intended manner.
15The remote central control, in the event o~ its receipt of 16 an electronic trouble signal over the sensor bus, returns an 17 enable signal to the potentially breached unit. The enable 18 signal is received by conventional logic 94, such as an AND
19 gate. Responsible personnel then perform an in-the-field simulation of an alarm event, such as walk-testing the 21 ultrasonic motion detection of sub-system. The alarm signal 22 processor 36 is operable to produce a simulated alarm signal, _ 19 --- .; . ~- -~ ~ 80 ~

1 which is applied to the logic 94, and together with the enable 2 signal, drives the output of the logic 94 "high", which resets 3 the memory latch 86 for removing the trouble Indication.
4 The preferred embodiment is exemplary only., the principles that underlie the present invention have utility in alarm 6 contexts employing different technology, and as will be 7 appreciated by those skilled in the art, the present invention 8 has wide utility in diverse fire and intrusion security ~ systems, among others; and is not to be limited except by the scope and spirit of the claims.

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Claims (13)

1. A self-secured security installation, comprising:
means including a sensor for providing detection of an event in the operative locale of the sensor;
means including an alarm coupled to the means including the sensor via a communication link for providing an explicit indication remote from the sensor that the event is occurring in response to the detection of the event;
means coupled to the sensor for monitoring the operative integrity of the sensor;
means coupled to the communication link for monitoring the communications integrity of the communication link;
means including a memory individually responsive to a degradation in the integrity of the communications link and of the sensor for latching in the memory trouble or fault data representative of the degradation and for providing a possible trouble or fault signal; and means operative in response to a successful simulation of the function of the sensor for releasing the memory and removing the possible trouble or fault signal.

2. The invention of claim 1, wherein said sensor integrity monitoring means monitors the electrical integrity of the sensor.

3. The invention of claim 1, wherein said sensor integrity monitoring means monitors the mechanical integrity of the sensor.

4. The invention of claim 1, wherein said sensor integrity monitoring means monitors the acoustical integrity of the sensor.

5. The invention of claim 1, wherein said communications link integrity monitoring means is cyclically operative.

6. The invention of claim 5, wherein said cyclically operative communications link integrity monitoring means includes means for cyclically sending a test signal over the communication link from the means including an alarm to the means including the sensor, and means responsive to a predetermined characteristic of the return of the test signal from the means including the sensor to the means including the alarm over the communication link indicative of whether or not the communication integrity of the line is degraded.

7. The invention of claim 6, wherein the characteristic is a time interval.

8. A method for insuring the security of a security installation of the type having at least one local sensor, a remote central alarm and control unit, and a communication link therbetween, comprising the steps of:
monitoring the integrity of the communication link;
monitoring the integrity of the sensor;
storing a trouble indication in a memory element in the event that either the integrity of the link or the integrity of the sensor is degraded;
generating a signal in response to detection of a simulated sensor detectable event in the operative local of the sensor if a trouble indication has been stored; and using said signal generated in response to the simulated sensor detectable event to remove the trouble indication from the memory element because it is representative of a successful simulation of communication link and sensor functionality.

9. The invention of claim 8, wherein the sensor is a motion-responsive sensor, and said simulation includes walk-testing the sensor.

10. The invention of claim 8, wherein said storing step includes the step of storing the trouble indication as a data signal in a memory element.

11. A security installation, comprising:
a transceiver;
means coupled to said transceiver for providing an alarm signal indication upon detection of doppler-components in the transceiver output signal representative of intruder motion;
means coupled to said transceiver for providing an electrical signal having a voltage representative of the impedance of the transceiver in its transmit mode;
means responsive to the voltage for signalling possible trouble associated with the transceiver in response to whether or not the voltage meets predetermined criteria;
means responsive to the production of a trouble signal for storing a representation of the trouble state; and means responsive to a successful walk-test simulation of the operability of the transceiver for removing the trouble signal and resetting the memory element.

12. The system of claim 11, further including means coupled to the communication link for monitoring the integrity of the communications link, and further including means responsive to a degradation in the communication link for storing in the resetable memory element means an indication representative of the possible communication link degradation.

13. The system of claim 12, further including means responsive to an indication of a possible communication link integrity degradation and further responsive to a successful walk-test simulation of the functional operability of the transceiver for removing the indication and resetting the memory means.