CA1264494A - Frame buffer memory - Google Patents
Frame buffer memoryInfo
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- CA1264494A CA1264494A CA000584636A CA584636A CA1264494A CA 1264494 A CA1264494 A CA 1264494A CA 000584636 A CA000584636 A CA 000584636A CA 584636 A CA584636 A CA 584636A CA 1264494 A CA1264494 A CA 1264494A
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Abstract
Abstract:
The present invention relates to an apparatus for storing and bit shifting a sequence of data words. The apparatus is comprised of a first unit for receiving and storing a first sequence of data words and for outputting the first data word sequence in the same order as it is received. The apparatus further includes a storage unit to store a next to last data word outputted by the first unit. A unit is provided to output a second data word sequence with each word thereof being comprised of a selected number of bits of the last data output word and the next to last data output word. Finally, a second unit is provided for receiving and storing the second sequence of data words, and for outputting the second data word sequence in the same order as it is received.
The present invention relates to an apparatus for storing and bit shifting a sequence of data words. The apparatus is comprised of a first unit for receiving and storing a first sequence of data words and for outputting the first data word sequence in the same order as it is received. The apparatus further includes a storage unit to store a next to last data word outputted by the first unit. A unit is provided to output a second data word sequence with each word thereof being comprised of a selected number of bits of the last data output word and the next to last data output word. Finally, a second unit is provided for receiving and storing the second sequence of data words, and for outputting the second data word sequence in the same order as it is received.
Description
Frame buffer memory _ . _ This is a division o copending Canadian Patent Applic~tion Serial No. S04,401 which was filed on March 18, 1986.
Background of the Invention S~he present invention relatès to frarne bu~fer memory systems for raster displays, and more particularly to an apparatus for facilitating rapid scrolling of raster displays in either vertical or horizontal directions.
Raster scan frame bu~fer displays have become increasingly popular as the price of semiconductor memory has decreased. The image to be displayed is represented in a large memory that saves a digital representat;on of the intensity and/or color or each picture element, or pixel, on the screen. By properly recording the data in the memory an arbitrary image can be displayed, making the display hardward insensitive to image content. The frame buffer memory is equipped with hardware to generate a video signal to refresh the display and with a memory port ~to allow a host computer or display processor to change the ~rame buffer memory in order to change the image being displayed~ i Interactive graphics applications require rapid :;
changes to the frame buffer memory. Although the speed of the ho~t display processor is clearly important to high performance, so also are the properties of the memory system, particularly update bandwidth, the rate at which the host processo~ or data processor may access the frame bufer memory. For a given memory technology the implicit geometry of frame buffer memory access can af~ect this rate.
The process of æcrolling an image, or a portion of an ~;image on a screen involves reading pixel data from one :~
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area of a frame buffer memory and writing it to another area. In the prior art, frame buffer memories have been arranged such that groups of pixels along scan lines are stored at sequentially addressed memory locations.
5 Scrolling speed has been improved by providing first in, first out (FIFO) buffers for storing sev~ral words of pixel data rapidly read fro~ such sequential memory addresses, with the low bits of the addresses being rapidly incremented by a counter rather than by the host 10 display controller. The data stored in the FIF0 buffer is then written back into memory at the new address sequence also utilizing the counter to rapidly increment the address~ While this approach improves scrolling speed, further improvement in scrolling speed is desirable.
Summary of the Invention According to the invention, a frame buffer memory has a random access memory (RAM) for storing pixel data in groups, each group containing pixel data corresponding to a separate set of a plurality of pixels along a horizontal 20 raster line of a display. Each group is separately ad~ressed. The RAM is organized into tiles, with each ~ tile comprising an array of pixel data ~roup rows and ;~ ~ columns corresponding to a separate rectangular subset of horizontall.y and vertically contiguous display pixels.
25 The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel group row within each tile is addressed, while a second subset of the column address determines which pixel group column within each tile is addressed. ~11 other bits of the row and column addresses determine which tile is addressed. In this arrangement, locations within the R~M sharing a common row address but with differing column addresses can be sequentially accessed at a higher rate than locations with differing row addresses. According to a further aspect of the ` ~ invention, a first-in, first-out bu~er, provided to store the se~uences of data read from the RAM, also includes a barrel shifter to shift bit positions of the data groups so stored to facilita~e proper pixel alignment during a horizontal scrolling operation.
According to the invention, means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that groups within a selected tile row or column may be successively addressed in any order.
This provides rapid addressing of sequences of pixel da~a corresponding to contiguous rows or columns of display pixels and facilitates rapid scrolling of a display window in any vertical or horizontal direction.
According to the invention, a logic circuit is provided to rapidly modify sequences of data read from the RAM and stored in the buffer prior to rewriting the data to the RAM thereby allowing rapid alteration of pixel attributes.
It is an object of the present invention to provide an improved frame bufer memory system permitting rapid horizontal and vertical scrolling and alteration of pixel data.
In accordance with one aspect of the invention there is provided an apparatus for storing and bit shifting a sequence of data words comprising: first means for ~ receiving and storing first sequence of data words, and -~ for outputting said first data word sequence in the same order as it is received; means to store a next to last - data word outputted by said first means; means to output a 30~ second data word sequence, ea¢h word thereo~ comprising a selected number of bits of said last data output word and said next to last data output word; and second means ~or receiving and storing said second s~uence of data words, and for outputting said second data word sequence in the same order as it is received.
The~subject matter of the present invention is particularly pointed out and distinctly claimed in the ,:
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concluding portion of this specification. However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with accompanying drawings wherein like reference characters refer to like elements.
The present invention taken in conjunction with the invention described in copending Canadian Patent Application Serial No. 504,401 will be described in detail hereinbelow with the aid of the accompanying drawings, in which:
FIG. 1 is a block diagram of a frame buffer memory system employing the present invention;
FIG. 2 is a chart of the addressing of a memory tile;
FIG. 3 is a block diagram of a data controller of FIG.
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FIG 4 is a block diagram of the rasterop combination logic circuit of FIG. 3;
FIG. 5 is a block diagram of the FIF0 control circuit 20 of FIG. 2, and FIG. 6 is a table o input and output relations for the read only memory at FIG. 5.
Detailed Descri~tion ~ eferring to FIG. 1, a frame buffer memory system 10, 25 depicted in block diagram form, is adapted to generate an image on cathode ray tube (CRT~ 12 based on data transmitted over a sixteen bit data bus 14 from a controlling device such as a host computer or display processor system. The image on the CRT 12 is made up of 30 pixels and ~the color or other attribute of each pixel is controlled by the state of a corresponding eight bit pixel data word. The frame buffer memory 10 comprises a random access memory (RAM~ array 16 for storing the pixel data, a ^ set o~eigh~ data controllers 20 Eor controlliny the flow 35 of data between the RAM array 16 and the data bus 14, an . .
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I/O controller 18 for controlliny addressing of the RAM array 16, and a conventional video output cir-cuit 22 for generatiny t~e appropriate CRT 12 refresh signals to achieve the desired display S based on the pixel data stored in the RAM array 16.
RAM array 16 comprises a set of 128 64K x lb:it : RAM chips arranged in an array of eight rows (planes) and sixteen columns. Each RAM chip is addressed by a sixteen bit word but has only eight address bus 10 terminals connected to an ei~ht bit address bus 25 Therefore each ~AM chip in array 16 is of the type wherein ~ddressing occurs in two steps. First an eight bit row addre~ is placed on the RAM address bus 25 and a row address strobe (RAS) is applied to strobe the row address into the RAM chip. Then an eight bit column address is place~ on the ~AM
address bus ~5 and a colu~n addre~s ~trobe (CAS~ is appli~d to strobe the column address into the RAM
~:~ ohip. Data is read from or written into the RAM at ; 20 the row and column addres~ according to the state of an applaed read/wri~e (R/W~ con~rol signal ~, ~ carried on control lines 26. A single C~S line is ;~ ~ applied in com~on to each ~AM ohip o~ the array 16 ~hile a separate ~AS line labeled ~ASO-~AS15 is applied in comm~n to each of the eight RAM chips of `~ each o~ the~sixte~n array 16 columns.
; ~ ; Each R~M chip has a data IjO terminal through which a sin~l~ data bit 1~ read ~rom or written to the R~N ~hip. The data I/O ter~inals o all 8iX-teen RAM~ o~ each;:array plane are connected through a ~ixt~en line data ~us 60 ~o a corresponding:data controller 20 ~o tha~ each data controller 20 can end or receive sixteen bits of data to or from the sixteen RAM chips of a given plane during a memory ~ 35 write or a memory read operation. The data bus 6Q
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of each array plane is also brought out to the video output circuits 22 to permit data to pass from array 16 to the video output circ~uits for screen refresh.
The fir3t ~it of each pixel is stored in plane O of array 16. ~he second bit of each pixel is stored in plane l at the same RAM adaress and in the same ~AI~array 16 column as the first bit of the pixel. In a similar fashion successive pixel bits of each pixel are stored in successive planes, the eighth bit o~ each pixel being stored in plane 7. Since each R~M chip of the array 16 comprises 64K storage locations and since there are 16 RAM
chips in each plane o~ the array 16, a total of 64K
15 x L6 or 1024K eight bit pixels may be stored in the array with sixteen pixels stored at each array address allowing, for example, a 1,024 X 1,024 pixel display.
During a memory write cycle, each data ç~on-: 2Q troller 20 transmits a sixteen bit word over the associated plane data bus 60 to ~he corresponding plane ~AM 16, o~e bit being applied to each of th~
sixteen similarly addres~ed memory cells of the memory array 16 piane. Selected RAM colu~ns in ~:25 array 16 are ~AS strobed at the same time and then ever~r RAM is CAS strobed so that the data from the data controllers 20 may be Written into the ~AS
strobed ~AMs of the corresponding array 16 planes.
:~herePore fro~ one to sixteen similarly~addressed :~30 pixels may be changed in a single write cycle~
During a r~emory read cycle, each RAM in the array is RAS strobed and then CAS strobed so that data may be read from each RAM array 16 plane and ,trans~itted to an associated data controller 20.
35 Therefore one or more corresponding bits of e~ch .
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of sixteen similarly addr~ss~d pixels may be read in a single read cycle.
I/O controller 18 comprises counters 30 and 34, registers 32 and 36, refxesh circuits ~0 a~d muLtiplexer 38. During a re~d or a write access cycle, the eurrent sixteen bit memory address i5 transmitted to I/O controller 18 from the display controller over an address bu~; 24. Address bits A00 and A01 of the current address are stored in X
10 counter 30, bits A02-P05 are stored in X register 32, bits A06-AO~ are 6tored in Y counter 34 and bits A08-~A15 are stored in Y register 36. Once ~he two bit data values are stored in counters 30 and 32, either counter may then increment or decrement the stored count on receipt of a C~TX or CNTY pulse over control lines ~ fxom _he display processor.
The count direc~ion (up or down~ is deter~ined by ; the state o~ a s~n~le bit I~C~DEC indicati~g signal -:~ also transmitted to the X and ~ counters over . .
control line 26. The data ~tored i~ counters 30 ~; and 34 and in registers 32 and 36 is applied to P.
~; and B inputs of 32/8 bit multiplexer 38 with bi~s A02-A05 a~d A08-All being applied to input A of multiplexer 38 and with bit~ A00, ~01, A06, -A07 and A12-A15 being applied to input B. During a memory read or write access, prior to a RAS strobe, multî-plexer 38 is switched ~uch that it~ input A is transmitted to its output, i. e. address lin~ 25 to ~:j the ~AM array 16. :Therefore ~he eight bits applied : 30 to input A of multiplexer 3~ compxise the row : addre~s for the aray. Then, prior to a CAS
s~:robe,: ~ultiplexer 38~ witched ~ pass the :~- eight bits appearin~ at input B to address bus 25.
Therefore the eight b~ts~at input ~ compri~e the column address for he aFray.
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Eight bit row and column addresses are also generated by a convention~l refresh counter in circuit 40 and applied to C and D inputs of multi-plexer 38. During a screen refresh operation, the ~ultiplexer 38 alternately appLies the C and D
inputs to the ~M array address bus as internal : counters in the refresh circuit generate all combi-nations of the row and column addre~ses. A refresh operation is initiated by a s~ngle bit signal REF
on control Lines ?6 from the disp~ay processor.
The ~witehin~ position of multiplexer 38 is also controlled by the REF signal and a single bit RAS/C~S signal on control lines 26.
The pixel data words are stored in each plane o~ memory array 16 in 409S blocks, or "tiles", each having four rows, with four sixteen bi~ data words in each ro~ as shown in FIG. 2. In FIGo 2 the : large rectangle represe~t3 a tile while each small rectangle therein represents a sixteen bit pixel word. The sixty-~our pixe1s o~ the four, sixteen .~ bit:data words of each tile row correspond to sixty ~our ~uccessive pixels of A raster line on the , display of CRT 12, while the four rows of each tile correspond ~o ~our contiguous raster lines on the display~ When the array is addressed, the particu-lar one ~f the sixteen words currently addressed in each tile i8 ~determined by the same ~our addres ~its A00, A01~ A06 and A07, each o~ which are colu~n address strobed.~ The ~our bit address ~A07, A06, AOl, A00) o~ each word o~ a ti1e i~ .
shown in the corresponding smal1 re~tan~lè in FIG.
Background of the Invention S~he present invention relatès to frarne bu~fer memory systems for raster displays, and more particularly to an apparatus for facilitating rapid scrolling of raster displays in either vertical or horizontal directions.
Raster scan frame bu~fer displays have become increasingly popular as the price of semiconductor memory has decreased. The image to be displayed is represented in a large memory that saves a digital representat;on of the intensity and/or color or each picture element, or pixel, on the screen. By properly recording the data in the memory an arbitrary image can be displayed, making the display hardward insensitive to image content. The frame buffer memory is equipped with hardware to generate a video signal to refresh the display and with a memory port ~to allow a host computer or display processor to change the ~rame buffer memory in order to change the image being displayed~ i Interactive graphics applications require rapid :;
changes to the frame buffer memory. Although the speed of the ho~t display processor is clearly important to high performance, so also are the properties of the memory system, particularly update bandwidth, the rate at which the host processo~ or data processor may access the frame bufer memory. For a given memory technology the implicit geometry of frame buffer memory access can af~ect this rate.
The process of æcrolling an image, or a portion of an ~;image on a screen involves reading pixel data from one :~
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area of a frame buffer memory and writing it to another area. In the prior art, frame buffer memories have been arranged such that groups of pixels along scan lines are stored at sequentially addressed memory locations.
5 Scrolling speed has been improved by providing first in, first out (FIFO) buffers for storing sev~ral words of pixel data rapidly read fro~ such sequential memory addresses, with the low bits of the addresses being rapidly incremented by a counter rather than by the host 10 display controller. The data stored in the FIF0 buffer is then written back into memory at the new address sequence also utilizing the counter to rapidly increment the address~ While this approach improves scrolling speed, further improvement in scrolling speed is desirable.
Summary of the Invention According to the invention, a frame buffer memory has a random access memory (RAM) for storing pixel data in groups, each group containing pixel data corresponding to a separate set of a plurality of pixels along a horizontal 20 raster line of a display. Each group is separately ad~ressed. The RAM is organized into tiles, with each ~ tile comprising an array of pixel data ~roup rows and ;~ ~ columns corresponding to a separate rectangular subset of horizontall.y and vertically contiguous display pixels.
25 The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel group row within each tile is addressed, while a second subset of the column address determines which pixel group column within each tile is addressed. ~11 other bits of the row and column addresses determine which tile is addressed. In this arrangement, locations within the R~M sharing a common row address but with differing column addresses can be sequentially accessed at a higher rate than locations with differing row addresses. According to a further aspect of the ` ~ invention, a first-in, first-out bu~er, provided to store the se~uences of data read from the RAM, also includes a barrel shifter to shift bit positions of the data groups so stored to facilita~e proper pixel alignment during a horizontal scrolling operation.
According to the invention, means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that groups within a selected tile row or column may be successively addressed in any order.
This provides rapid addressing of sequences of pixel da~a corresponding to contiguous rows or columns of display pixels and facilitates rapid scrolling of a display window in any vertical or horizontal direction.
According to the invention, a logic circuit is provided to rapidly modify sequences of data read from the RAM and stored in the buffer prior to rewriting the data to the RAM thereby allowing rapid alteration of pixel attributes.
It is an object of the present invention to provide an improved frame bufer memory system permitting rapid horizontal and vertical scrolling and alteration of pixel data.
In accordance with one aspect of the invention there is provided an apparatus for storing and bit shifting a sequence of data words comprising: first means for ~ receiving and storing first sequence of data words, and -~ for outputting said first data word sequence in the same order as it is received; means to store a next to last - data word outputted by said first means; means to output a 30~ second data word sequence, ea¢h word thereo~ comprising a selected number of bits of said last data output word and said next to last data output word; and second means ~or receiving and storing said second s~uence of data words, and for outputting said second data word sequence in the same order as it is received.
The~subject matter of the present invention is particularly pointed out and distinctly claimed in the ,:
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concluding portion of this specification. However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with accompanying drawings wherein like reference characters refer to like elements.
The present invention taken in conjunction with the invention described in copending Canadian Patent Application Serial No. 504,401 will be described in detail hereinbelow with the aid of the accompanying drawings, in which:
FIG. 1 is a block diagram of a frame buffer memory system employing the present invention;
FIG. 2 is a chart of the addressing of a memory tile;
FIG. 3 is a block diagram of a data controller of FIG.
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FIG 4 is a block diagram of the rasterop combination logic circuit of FIG. 3;
FIG. 5 is a block diagram of the FIF0 control circuit 20 of FIG. 2, and FIG. 6 is a table o input and output relations for the read only memory at FIG. 5.
Detailed Descri~tion ~ eferring to FIG. 1, a frame buffer memory system 10, 25 depicted in block diagram form, is adapted to generate an image on cathode ray tube (CRT~ 12 based on data transmitted over a sixteen bit data bus 14 from a controlling device such as a host computer or display processor system. The image on the CRT 12 is made up of 30 pixels and ~the color or other attribute of each pixel is controlled by the state of a corresponding eight bit pixel data word. The frame buffer memory 10 comprises a random access memory (RAM~ array 16 for storing the pixel data, a ^ set o~eigh~ data controllers 20 Eor controlliny the flow 35 of data between the RAM array 16 and the data bus 14, an . .
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I/O controller 18 for controlliny addressing of the RAM array 16, and a conventional video output cir-cuit 22 for generatiny t~e appropriate CRT 12 refresh signals to achieve the desired display S based on the pixel data stored in the RAM array 16.
RAM array 16 comprises a set of 128 64K x lb:it : RAM chips arranged in an array of eight rows (planes) and sixteen columns. Each RAM chip is addressed by a sixteen bit word but has only eight address bus 10 terminals connected to an ei~ht bit address bus 25 Therefore each ~AM chip in array 16 is of the type wherein ~ddressing occurs in two steps. First an eight bit row addre~ is placed on the RAM address bus 25 and a row address strobe (RAS) is applied to strobe the row address into the RAM chip. Then an eight bit column address is place~ on the ~AM
address bus ~5 and a colu~n addre~s ~trobe (CAS~ is appli~d to strobe the column address into the RAM
~:~ ohip. Data is read from or written into the RAM at ; 20 the row and column addres~ according to the state of an applaed read/wri~e (R/W~ con~rol signal ~, ~ carried on control lines 26. A single C~S line is ;~ ~ applied in com~on to each ~AM ohip o~ the array 16 ~hile a separate ~AS line labeled ~ASO-~AS15 is applied in comm~n to each of the eight RAM chips of `~ each o~ the~sixte~n array 16 columns.
; ~ ; Each R~M chip has a data IjO terminal through which a sin~l~ data bit 1~ read ~rom or written to the R~N ~hip. The data I/O ter~inals o all 8iX-teen RAM~ o~ each;:array plane are connected through a ~ixt~en line data ~us 60 ~o a corresponding:data controller 20 ~o tha~ each data controller 20 can end or receive sixteen bits of data to or from the sixteen RAM chips of a given plane during a memory ~ 35 write or a memory read operation. The data bus 6Q
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of each array plane is also brought out to the video output circuits 22 to permit data to pass from array 16 to the video output circ~uits for screen refresh.
The fir3t ~it of each pixel is stored in plane O of array 16. ~he second bit of each pixel is stored in plane l at the same RAM adaress and in the same ~AI~array 16 column as the first bit of the pixel. In a similar fashion successive pixel bits of each pixel are stored in successive planes, the eighth bit o~ each pixel being stored in plane 7. Since each R~M chip of the array 16 comprises 64K storage locations and since there are 16 RAM
chips in each plane o~ the array 16, a total of 64K
15 x L6 or 1024K eight bit pixels may be stored in the array with sixteen pixels stored at each array address allowing, for example, a 1,024 X 1,024 pixel display.
During a memory write cycle, each data ç~on-: 2Q troller 20 transmits a sixteen bit word over the associated plane data bus 60 to ~he corresponding plane ~AM 16, o~e bit being applied to each of th~
sixteen similarly addres~ed memory cells of the memory array 16 piane. Selected RAM colu~ns in ~:25 array 16 are ~AS strobed at the same time and then ever~r RAM is CAS strobed so that the data from the data controllers 20 may be Written into the ~AS
strobed ~AMs of the corresponding array 16 planes.
:~herePore fro~ one to sixteen similarly~addressed :~30 pixels may be changed in a single write cycle~
During a r~emory read cycle, each RAM in the array is RAS strobed and then CAS strobed so that data may be read from each RAM array 16 plane and ,trans~itted to an associated data controller 20.
35 Therefore one or more corresponding bits of e~ch .
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of sixteen similarly addr~ss~d pixels may be read in a single read cycle.
I/O controller 18 comprises counters 30 and 34, registers 32 and 36, refxesh circuits ~0 a~d muLtiplexer 38. During a re~d or a write access cycle, the eurrent sixteen bit memory address i5 transmitted to I/O controller 18 from the display controller over an address bu~; 24. Address bits A00 and A01 of the current address are stored in X
10 counter 30, bits A02-P05 are stored in X register 32, bits A06-AO~ are 6tored in Y counter 34 and bits A08-~A15 are stored in Y register 36. Once ~he two bit data values are stored in counters 30 and 32, either counter may then increment or decrement the stored count on receipt of a C~TX or CNTY pulse over control lines ~ fxom _he display processor.
The count direc~ion (up or down~ is deter~ined by ; the state o~ a s~n~le bit I~C~DEC indicati~g signal -:~ also transmitted to the X and ~ counters over . .
control line 26. The data ~tored i~ counters 30 ~; and 34 and in registers 32 and 36 is applied to P.
~; and B inputs of 32/8 bit multiplexer 38 with bi~s A02-A05 a~d A08-All being applied to input A of multiplexer 38 and with bit~ A00, ~01, A06, -A07 and A12-A15 being applied to input B. During a memory read or write access, prior to a RAS strobe, multî-plexer 38 is switched ~uch that it~ input A is transmitted to its output, i. e. address lin~ 25 to ~:j the ~AM array 16. :Therefore ~he eight bits applied : 30 to input A of multiplexer 3~ compxise the row : addre~s for the aray. Then, prior to a CAS
s~:robe,: ~ultiplexer 38~ witched ~ pass the :~- eight bits appearin~ at input B to address bus 25.
Therefore the eight b~ts~at input ~ compri~e the column address for he aFray.
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Eight bit row and column addresses are also generated by a convention~l refresh counter in circuit 40 and applied to C and D inputs of multi-plexer 38. During a screen refresh operation, the ~ultiplexer 38 alternately appLies the C and D
inputs to the ~M array address bus as internal : counters in the refresh circuit generate all combi-nations of the row and column addre~ses. A refresh operation is initiated by a s~ngle bit signal REF
on control Lines ?6 from the disp~ay processor.
The ~witehin~ position of multiplexer 38 is also controlled by the REF signal and a single bit RAS/C~S signal on control lines 26.
The pixel data words are stored in each plane o~ memory array 16 in 409S blocks, or "tiles", each having four rows, with four sixteen bi~ data words in each ro~ as shown in FIG. 2. In FIGo 2 the : large rectangle represe~t3 a tile while each small rectangle therein represents a sixteen bit pixel word. The sixty-~our pixe1s o~ the four, sixteen .~ bit:data words of each tile row correspond to sixty ~our ~uccessive pixels of A raster line on the , display of CRT 12, while the four rows of each tile correspond ~o ~our contiguous raster lines on the display~ When the array is addressed, the particu-lar one ~f the sixteen words currently addressed in each tile i8 ~determined by the same ~our addres ~its A00, A01~ A06 and A07, each o~ which are colu~n address strobed.~ The ~our bit address ~A07, A06, AOl, A00) o~ each word o~ a ti1e i~ .
shown in the corresponding smal1 re~tan~lè in FIG.
2. ~he other twelve bi~s of the sixteen bit memory array addr~ss determine which of the 4096 tiles of the array 16 are being a~c~ssed.
~: 35 Durin~ a scrol1ing opera~ion, where a sec:ion ~`''' .
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of the display is to be moved to another part ofthe screen, data is read from one area of the memory array 16 and rewritten to another area. In the present in~ention, th~ four words of a selected tile row or column may be read or written in rapid ~uccession by generating a single RAS strobe on all the RASC-RAS15 l ines followed by a series of four CAS strobes, with the appropriate two of four tile address bits being incremented or decre~ented by X
counter 30 or Y counter 34 of FIG. 1 prior tr:i the CAS strobes. For instance, whe~ scrolling the display horizontally, the twelve bit ~ddress o~ a particular tile, along with the four bit address of the first word in a selected tile row are generated 15 by the display ~rocessor. These sixteen address : bits are placed on address bus 24 and transmitted ~: to the display bu~fer 10 where they are stored as .~ de~cribed above in counters 30 and 34 and registers 32 and 36 and then applied to ~ultiplexer 38.
20 I~itially AQl and A00 are both O's. A07 or A06 may be any combination depending on which tile row is selectea. The first data word o~ the selected tile row is then read ~nd transmitted to the data controllers 20 after the ~irst RAS and CAS strobes.
The X counter 30 is pul~ed with a CNTX si~nal while the I~C~DEC signal is in a state indicating cre~ental~counting, thereby incrementing ~00 to a logical 1. A second CAS strobe is applied to the ;~ array 16 without an intervening RAS strobe such : 30 that the second word o~ the 6elected tile row is column addressed, read and then trans~itted to the data controllers 20~ Another ~AS strobe is un-necessary beca~se the row address of all words in the tile row is the same. The X counter 30 ~urther increments the two bit A01, A00 word a second time such that A01 is set to a logical 1 while A00 is set to a logical 0, and then a third CAS strobe is applied to the array 16 to address the third word of the row. The two bit address is incremented ~ 5 again so that A01 an~ A00 are both logical 1~9 : and a fourth CAS s~robe is applied ~o the RAM array 16 therea~ter so that the fourth data word in the selected tile row is read and transmitted to the data controllers 20. ~he four words thus read from 10 each plane are stored in the associated data con-troller 20 and may be later writ~en to a different tile of the array in a similar fashion, using a RAS
strobe followed by four CAS strobes.
A data read or write operation for a vertical : 15 scroll would operate in a similar fas~ion except - that th~ Y counter 34 increments or decrements the data bi~s A07 and A06 such that ~he four word~ o~ a selected tile column are successively read or writ-: ten utilizing one RAS stro~e:followed by four CAS
strobes. For:an upward scroll, data wsrds of a tile column are read and written from top to bot-tom. Therefore the Y ~ounter 34 is incremented after each C~S ~;~robe~ Fvr a downward scroil, ~ .
: Y counter 34 is~re~enbe~afber.eacK ~A5.signal.
When the left or ri~ht edge of a ~indow to be vertically scroiled doe~ not coincide with the irst or last bi~ of a data word, the RAM chips :~ storing pixels lying out:side the window bou~daries -~ are no~ RAS strobed. Therefore only the data sets ; 30 of a boundary~word;corresponding to pixel~lying in~id~ the wlndow area are read and rewri tten : ~ during a~vertical ~crolling operation.
: : Thus the~til~e arrangement~of the present : inven~ion per~its:access t~ four sUccessive ~emory words during a~single memory~read or~write cycle.
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Since the four memory words accessed correspond to either vertically or horizontally contiguous pixels on the display 22, and since counters 30 and 34 can either increment or decrement the address, the four data words can be read left to right, righ~ to left, ~op to bottom, or bottom to top~ ~his allows rapid scro:lling in any of four directionsO
The plane 0 data controller 20 of FIG. 1 is depicte~
in more detailed block diagram form in FIG. 3. ~he topology and operation of each of the other data controllers associated with RAM planes 1-7 is similar.
During a memor~ read cycle, single bit data read from e:ach : of the six~een RAMs of any plane passes over data bus 60, ; through buffer 62 and 32/16 bit multiplexer 64, and into lS data register 66. The switching position of multiplexer 64 is controlled by a read/write indicating signal R/W
transmitted over one control line 26 rom the display processor. Once stored in data register 66, the sixteen bit data w~rd from the plane may be transmitted to the 20. display processor through bufer 68 and over data lines 14.
:~ Du~ing a ~emory write cycle, data to be written in~o the plane 0 R~s is initially stored in data register 66 and then transmitted to the RAMs through buffer 70 and over the plane 0 data bus 60. Prior to storage in register 66, ~n preparation for a me~ory write operation, the data to be written into memory is generated At an output D oE a rasterop traSter operation) combination logic circuit 82 ~described here;nbelow) and applied to a second sixteen bi~ input of multiplexer 64. Lo~ic circuit 3Q 82 has three 16 bit inputs A~, B and C and is adapted to generate the sixteen bit output word D, each bit of which is some selected Boolean combination of the corresponding ~ - bits o~ the three inputs A, B and C. The particular ;~ logical combination of inputs to be performed by logic circuit 82 is selected by preloading a rule register 86 with an eight bit word which is then applied to an input ..
logic circuit 82. This eight bit data word is loaded into rule register 86 by transmitting it from the display processor over data bus 14 and through buffer 76 and latch 78.
Referring to FIG. 4, a preferred embodi~ent of rasterop logic circuit 82, depicted in b]Lock diagram form, comprises a set of sixteen 8/1 multiplexers 96, labeled MUX 0 - MUX 15. Eight data llnes ~R0 - R7), one bit each of the rule data stored by rule register 86, are applied to the eight input terminals of each multiplexer 96. The first bit ~A0, B0 or C0) of each of the sixteen bit words appearing at the A, B and C input terminals of logic circuit 82 is applied to a corresponding one of three control inputs to ~UX 0~ Similarly, successive bits of the A, B and C inputs of logic circuit 82 are applied to the control inputs of successive multiplexers 96. The single bit output D0-D15 of each multiplexer of rasterop logic circuit 82 comprises a separate bit o~ the sixteen bit output D of logic circuit B2.
Each multiplexer 96 passes a data bit (a 0 or a 1) ~-~ carried by one of the rule register ~6 output lines . R0-R7 to the associated multiplexer output line D0-D15, ~r the R0-R7 line bein~ selected according to the three bit code A0-A15, B0-B15, C0-CIS appearing at the control ~: 25 terminals of the ~ultiplexer. Each multiplexer 96 ~ay therefore be programmed to genera~e an output D0-D15 ~ state on occurrence of any combination of the correspond-:~ ing A0-~15, B0-B15, C0-C15 input states simply by storing the appropriate eight bit data in rule ', : ' :
reqister 86 to appropriately set the states of the R0-R7 1 ines.
Referring again to ~IG. 3, a sixteen hit data word may be transmitted from the display controll~r over data bus 14, through buffer 76, latch 78 and 32/15 bit multiplex~r 80 and into anput C of rasterop combination logic circuit 82. The switchiny p~sition of multiplexer ~0 is determined by a contxol bit (SCR) carried on control lines 26 ~ro~ the display processor. ~he sixteen bit word thus transmltted by th~ di6play controller to input terminal C of logic circuit 82 may thet~ be modiied i f desired by logic c:ircuit 82 and passed through output D and multiplexer 64 to data register 66 for 15 storage therein and subsequent writing to a selected address o the plane 0 E~AM chips.
The 16 bit data word at input A of logic circuit 82 may be read from the plane 0 RAMs ~nd ~ransmitted through buffer 62 and 32/16 bit multi-plexer 92 and latch 94 to terminal A, the switchangstate of ~ultiplexer 92 being controlled by the . same ~/W control signal on control lines control-ling the switching state of ~ultiplexer 64. Al~er-natively, the data a~peari~g at ~erminal A of logic ~ 25 circui~ 82 may, during a ~e~ory write operation, be :~ transmitted ro~ the external control system to terminal A o~rer ~ata bus 14, ~ and through buffer 76, ~- latch 78, ~ultiplexer g2 and la~ch 94. The si~teen bit~word stored in data re~ister 66 continuously : 30 appears at input B of logic circuit 82.
The loading of regis~e~ and latches 66, 70, 86 and 92 is co~trolled by strobe ~ignals generated by address decoder 95 based on register addre6s appearing in address bus 24.
; 35 Durin~ a scrolling operation, the data re~d ~, ' ,i :~ ' .
from array 16 is stored i~ a first in, first out (FIF0) scrolling buffer 100 comprising a set of eight sixteen bit latches 102 ~LATCH l - LATCH 8), barrel ~hifter 104, and PIF0 control circuit 106.
Latches 1~5 are connected in series between the output of bufer 62 and one input of barrel shifter 104. The output of latch 4 is also applied to another input of barrel shifter 104. Latches 6-8 are connected in series between the output of barr~l shifter 104 ~nd o~e input of multipLexer 80.
FIF0 control circuit 106 selectively enables LATCHES 1-8 by energizing control lines El - ~8 connected there~o. With the latch enabled, the data appear;ng a~ its input also appears at its lS output such that the latch appears transparent to : incoming data. When a control input is deener-gized, the associated latch "latches" ~o that the .
latch output is fixed at its last state and is unaffected by la~ch inpu~ changes.
~ ~0 D2ta words read from array 16 duriny a scrol-:~ . ling operat;on pass from latch to latch in FIF0 bu~er lO0. The sixteen ~it output word of latc.h 4 .
and the sixteen bit output word o~ latch 5 comprise a thirty-two bit circular input word ~o barrel ~ 25 shiter 104. Barrel shifter lO~ generates a six-: tee~ bit output word comprising any selected ~ix-teen consecutive bits of the thirty-two bit circu-lar input word. The outpu~ of barrel shifter 104 beeomes the input to latch 6~ There are thirty diferent sets of sixteen consecutive bit~ in a thirty-two bit circular word and ~he particular set 6elected and outputted by the barrel shifter 104 ifi determined by a five bit data word SB applied to a :;
: 6hift control input of barrel shifter 104. This word i8 initially stored in a mode register 84 ., -, ' ~, ' ,j ~
after having been ~enerated by the display proces-sor and transmitted to register 84 over data line 14, and through buffer 76 and latch 78. The SB
word is then passed from mode register 84 throuyh FIFO control cireuit 106 to barrel shifter 104.
During a ~ert~cal scrolling operation, sets of four pixel data words of a tile column are read sequentially from array 16 using the RAS strobes followed by four CAS strobes as described above.
The CAS signals are carried on control lines 26 to FIFO control circuit 106. A system clock signal i~
also applied to FIFO control circuit 106 over con-trol lines 26. Initially all of the FIFO buf~er latches 102 are unlatched such that they all appear transparent to input data. As each data word is read, it is applied to the input of latch 1 o~ FIFO
; bu~fer 100. On the ~irst system clock signal fol-lowlng he fir~t CAS signal, FIFO control circui~
106 deenegi~eæ line El to }atch 1 ~ausing latch 1 to latch. Since all of the other la~ches are u~latched, the first da~a word falls through the . buffer to the outpu of latch 5. For a vertical scrolling:operation, the data SB applied to barrel shifter 104 is set such that the barrel shifter 25 . does not "shift", or in other words, the sixteen ~bit data at the output of latch 5 i8 passed ~hrough to la~oh 6 while the sixteen bits in latch 4~are ignorea by barrel sh~fter 104.
The passage of data:through most commercially 30~ availa~ barrel fihi~ters i:s relativ~ly slow ~om-pa~ed to the passage of data through a latch. Thus the ~irst data word may no~ have time to pass through the barrel shifter:104 during the fir~t fiy~tem clock cycle. :On the:next sys~em clock : ~ 35 cycle, control circuit 106 latches latch 5 and :
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unlatches latch 1. Thus, when the next data word is read following a second CAS signal and sent to the FIFQ buffer, it passes through latches 1-4, but not latch S. In the meantime, the ~irst dat~ word passes through the barrel shif ter and at least through latch 6. On the first clock cycle ~ollowing the second CAS strobe, control circuit 106 latches latch 6 and latch 1 and unlatches latch 5. The f ixst data word passes to the output of 10 latch ~ while progress of the second data word thrc>ugh the buffer is stopp d at the output of : latch 5. On the next clock cycle, latches 1 and 5 are unlatched while latches 5 and 8 are latched.
I a third data word is read on occurrence o~ a : 15 third CAS signal, it passes through latch 1. On the ~irst clock cycle after the third CAS signal, latches 1 and 6 are latched while latch 5 ~ unlatche~. ~atch 8 remains latched. A~ this poi~t ; the ~irst data word appears at the output of latch :~ 20 ~, the second data word is halted at the input to ~ latch ~, and the third data word is blocXed at the :~ input to latch 6. On the next clock cycle, latc~es ~ and 6 unlatch while latches 5 and 7 latch. At this point, the ~ir6t data word appears at the outpu~ of latch 8, the seco~d data word appears at the output of latch 7, and ~the third data word appears at the outp~t o~ latch 5.
If a four~h data word;is read ollowing a fourth CAS ~trobe, it pas~es to latch 1. Latches 1 and 6 ~hen latch:while latch 5 unlatches, allowing the fourth data word to pass through to the output of latch 5. In a similar fashion, the fifth, sixth, seventh and eighth data words read ~rom memory array 1`6 are backed up in FIFO bu~er 100 at the inputs to latcheæ 5, 4, 3, and 2 respectively~
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When the buffer is ully loaded with eight words, all latch~ remain latchedO
At any time after the irst data word is read and stored in FIF0 buf~er 100, the fir~t word and any subsequently stored data words may be sequen-tially passed from the buffer, through mul~iplexer 80 to input C of rasterop combination logic circuit 82. Logic circuit 82 may, if programmed to do so, modify the data in ~ome way, and then the modified lQ or unmodified pixel data is passed ~rom output D of logic circuit 82, through multiplexer 64 and into register 66. If the data ~as unmodified by ~ rasterop combination circuit 82, it may be rewrit-: ten to some other address o~ memory array 16 cor-:` 15 responding to a higher or lower position of the di~play~ thereby vertically scrolling the display.
Alternatively, logic ~ircuit ~2 may modify the data in some way~ as ~or in~tance by changing a bit ;; controlling pixel brightne~s or some other at-20 tribute, and the data may ~e written bac~ to the ~; same or another memory location. Thus the use of : ~ the logic circuit 82, in com~ination with ~he FIF0 :~ bu~fer 100, and the tile arrangement of me~ory ~: array 16, provides rapid alteration o~ selectea u~ 25 attributes of blo s or windows of ~he display, or rapid simultaneous al~ering and scrolling o the ~: display window~
~ When data is to be unloaded from ~IF0 buffer : lOO:and wrltten into memory array 16, multiplexer 30 80 is switc~hed to pass data appearing at the output of latch ~ to input C of logic circuit 80 by the SCR ~ignal on one lin~ o~ control lines 26. This data may then be modified and written ~ack ~nt~ men~ry ~~ as described above. Another line of control lines ~ 35 26 carries a scroll Fl~0 unload ~SFU~ signal which is applied to FIFO cont~ol circ~it 106. This 5ig-nal is ~enerated on occurrence of each CAS signal during a buffer 10~ unloading operation. When a CAS signal occurs, indicating that the data appear-ing at the output of Latch B has been passed toregister 66 and wrîtten bac~ into me~mory array 16, the SFU signal goes low, te~porarily. On the next clock signal, latch 8 is unlatched allowing the data at its input terminals to pass to its output.
On the next following cloc~ cycle, latch ~ is latched and latch 7 i5 unlatched, permitting the ~` data at the latch 7 input to pass to the latch 8 inpu~. The proc:ess continues with eac~ clock cyc:Le until all of the data stored in buffer 106 has been lS shifted by one latch. In the meantime, once latch 8 has latched the second data word appears at its output an~ may also be passed to register 66 and : ~ written to memory on the next CAS strobe. The FIF0 control circuit continuously ~hifts data from la~ch : 20 to latch whenever the preceding data has keen shi ted.
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he ive latches preceding the barrel shifter 104 permit at least five data words to be read~in . ~ rapid succession and stored in the buffer 1()0 ~` 25 regardless: of the speed of the barrel shifter.
Similarly, the three latches following barrel shif-:, ter ~104 allow ~our data words to be unloaded from th~ :buffe~ and written in~co m~mory in rapid succes-ion as long as the b rrel shifter~ 104 can process 30 ~ the fourth word duri:ng the time interval in which the set of ~our words i~ written to inemory.
: Typically the time required for ~our data words to pass~hrough the relatively slow barrel shifter is ~- needed for: s:~ther purposes, such~ as: a screen refresh 35 : operation, and is ~here~ore nonlimi~ing, provide~
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that the barrel shifter is located in the middle of the buffer and ~ot at either end.
During a horizontal ~crolling operation, the barrel shifter 104 i6 set by the SB data in m~de register 84 to select one sixteen bit subset of the data appearing at the outpu~s of latch 4 and latch 5 as its sixteen bit output. Since ~he thirty-two : bits of the two input words correspond to thirty-two horizontaIly contiguous pixels of a display, 10 and since pixel data is read and written in sixteen pixel blocks~ it may be necessary to shift the position ~f each pixel within a word by so~e nu~ber ~: of bit positions after it i~ read but be~ore it is rewritten back to the memory array 16. This bit position shifting is required i the distance of the horizontal shi~t is not a multiple of 16. The magnitude of the bit position shift correspond~ to the number of bits o the aata word appearing at the output o~ latch ~ that are incorporated:into the data word appearing at the output o~ the barrel shi~ter 104 and is controlled by the SB control input to the barrel shifter. The direction of the it position shift dépends on whether the data in latch 4 is phy~ically to the left or to the right of ~he data in latch 5 with reerenc~ to ~he rela-tive positions of on the display of corresponding pixels.
The loading o the FIF0 buffer 100 during a :~ horizontal s~roll~ng opera~ion inYoiving a bit 30 ~ position shift is generally ~i~ilar to th~ loading o~ the ~u~fer wh~n no bit position ~hift i8 r~-~:: quired exce~ ~hat latch 5~remains latched until ~: latch ~ latches and la~h 6 won't latch until after ~ ~ latch 4 latches. This ensures tha~ two sequential-;~ 35 ly read data words appear at the outputs of latches :: , ~., . . . .
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4 and 5, the inputs of barrel shifter 104, before : the output of the barre~ shifter is latched into latc~ 6.
When horizontally 3crolling from left to 5 righl:, the fourdata words in a tile row are read in right to left order and loaded into the buffer.
Thus the X counter 30 i decremented after each CAS
signal. If the left to right horiæontal scroll involves a shift that is no~ an even multiple of 10 sixteen pixels, then ~he barrel shifter is set to ~- genera~e data words wherein the high order bits ~: (rightmost) compris~ an app~opriate number of low order bits of the word in la~:ch S while ~he low ;~ order bits comprise high order bits of the word in 15 latch 4.
~ hen horizontally scrolling from right to l~f'c, the four data words in a tile row are read in left to right order and loaded into the buffer.
Thus the X coun~er 30 i~ inoremerlted after each CP~S
20 signal. If the ~croll introlves a shift ~hat is not:
an e~ren ~multiple of sixteen pixels, then the barrel ~:~ shi Çter ifi set to generate data words w~erein the high order bits co~pr~ise ~ an appropriate number of low order bit~; of the word in:latch 4 while the 25 low order bits comprise high order bits of t~e word in latch 5 .
FIG~ 5 is a blocX diagram of an embodiment of the FIF~ control circuit 106 of FIG~ 3. ControI
ircuit 106 co~pri~es a set of eight D-type flip-30 flops, FFl to PF8, ~ach having a ~ out~ut (labeled ~:~ : Ql to Q8 ~ for ~lip-flop~ ~1 to FE?8 respec~tivel~r) ollpled 'c~rough a buf fer to a corresponding control line ~E:l-E8 to a~ corresponding latch 102 of the FIF0 buf ~er 100. Control c~rcuit 106 also c:omprises a 35 ~ read only memory ~oM3 112 having eight data output ,~
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lines, each one connected to a D input of a corres-ponding flip-flop 110. The D inputs are labeled Dl to D8 for flip-flops Dl to D8 respectively. The eight Q outputs of the eight flip-flops are also . coupled to eight address line inputs of ROM 112.
set of four control lines 26 from the display processor, also applîed to four other address line inputs of ROM 112, include the CAS line, a scroll FIFO load (SFL) line, a ~croll FIFO unload (SFU) line, and a scroll FIFO clear (SFC) line. The :~ five SB bits from ~ode register 84 are applied to the inputs of an OR gate 114 while the output of ~ the 0~ gate is applied to still another address :: line input of ROM 112. A clock signal CK carried on another control line 26 is applied in common to the clock inputs o~ all flip-flops 110.
The Q output o each ~lip-flop 110 changes state ts match the current state of its D input : whenever the flip-flop is strobed by a CLK pu~se.
20 ROM 112 in combination with flip-flops 110 com~
prises a state machine wherein the current state of the D input of each flip-flop can be made high or low depen~ing on the collective states of all of the fl;p-flop 110 Q outputs together with the states of the other addressing inputs ~o the ROM.
The rules of correspondence between the ROM inputs and outputs are established by ~he data stored in : the ROM. FIG 6 is a chart which expresses th2 relationsh~p bet:wes~ the Dl-D8 outputs of the ~OM
and all of the inputs therat~. For each output Dl-8, thére ls listed a Boolean express.ion indicating under which input conditions the D output will ~e : high. When the expression is true (a logical 1), `:~ he corresponding D output will be true, and when the expression is false, the D output will be low.
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With ~he data of ROM 112 adjusted to effect these expres~ions, loading and unloading of the FIFO
buffex 100 will operate as previously described.
To clear data from the buffer, the SFC signal is driven low. A~ all other time~ SFC is high. A
low SFC signal causes Q2, Q3~ Q4, Q5, Q7 and Q8 to go high on the next cloc~ C~ cycle. ~hen, on a second CK cycle, Ql and Q6 go h;gh. With all of the Q outputs high, the E control inputs to all of the latches of buffer 100 go high, maXing them all - transparent. Initially, when ~here is no data stored in FIFO buffer~100, all of ~he Q outputs of flip flops 110 are high ~o that all of the latches are transparent. The CAS signal is used in the expression for Dl to cause latch 1 to latch after each CAS signal. The SFL signal is normally low except when the display control7er wishes to load : data into the bu~er 100. In such case, SFL is :
driven high at the same ~ime a~ the CAS signal, and stays hi~h for one CK cycle the~eafter. The ZS~
signal from OR gats 114 of FIG. 5 is high if any :one of the SB bits~is high, indicating that the barrel shiter is ~hif~ing pixel bit posit~ons o~
the data pa~sing through it. The ~SN signal i~
used in the expresslons of D5 and D6 to prevent :
la:t~h 6 ~ro~ latching or ~latch 5 from unlatching u~til latch~4 lat~hes. The SFU ~ignal is high ex~ept~when the~d~splay con~roller;has rcad data : : from~:th~ bu~ferO~ Thèn the~.SFU signal is::driven low :: 30 for:`one C~ cycle to 1nitia~e a~shift~o~ data~
through ~he:bufe~ The~SPU signal i8~-there~ore :~
: :~u~ed in the ~xpression ~or:D8, causing DB to yo -- high when SFU goes lQw:su~h that on the nex~ CK ;
:~ cycle Q~ goes high :to unlatch latch 8~ ;
~ While it is Fssibl~ that FIFO buf~r 100 , ''.
: ' ., ~3 could operate asynchronously, passing data from latch to latch without regard to a sys~em clock, the synchronous FI~O buffer of the present inven-tion requires latching to occur in concer~ with ~he 6ystem clock. ~herefore the disp~ay c:ontrol~:er c~n keep track of where data is in the FI:FO ~uffer at any given instant and can access the buffer without requiring asynchronous control 6ignals such as input ready or output ready.
While a preferred embodiment of the present inYention ha~ been shown and described, it will ~e apparent to those skilled in ~he art th~t ~any changes and modifications may be made without de-parting from the invention in its broader asp~cts.
The appended clai~s are th'erefore intended to cover : : all such changes and ~odifications as fall within the true spirit and~scopeiof the invention.
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~: 35 Durin~ a scrol1ing opera~ion, where a sec:ion ~`''' .
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of the display is to be moved to another part ofthe screen, data is read from one area of the memory array 16 and rewritten to another area. In the present in~ention, th~ four words of a selected tile row or column may be read or written in rapid ~uccession by generating a single RAS strobe on all the RASC-RAS15 l ines followed by a series of four CAS strobes, with the appropriate two of four tile address bits being incremented or decre~ented by X
counter 30 or Y counter 34 of FIG. 1 prior tr:i the CAS strobes. For instance, whe~ scrolling the display horizontally, the twelve bit ~ddress o~ a particular tile, along with the four bit address of the first word in a selected tile row are generated 15 by the display ~rocessor. These sixteen address : bits are placed on address bus 24 and transmitted ~: to the display bu~fer 10 where they are stored as .~ de~cribed above in counters 30 and 34 and registers 32 and 36 and then applied to ~ultiplexer 38.
20 I~itially AQl and A00 are both O's. A07 or A06 may be any combination depending on which tile row is selectea. The first data word o~ the selected tile row is then read ~nd transmitted to the data controllers 20 after the ~irst RAS and CAS strobes.
The X counter 30 is pul~ed with a CNTX si~nal while the I~C~DEC signal is in a state indicating cre~ental~counting, thereby incrementing ~00 to a logical 1. A second CAS strobe is applied to the ;~ array 16 without an intervening RAS strobe such : 30 that the second word o~ the 6elected tile row is column addressed, read and then trans~itted to the data controllers 20~ Another ~AS strobe is un-necessary beca~se the row address of all words in the tile row is the same. The X counter 30 ~urther increments the two bit A01, A00 word a second time such that A01 is set to a logical 1 while A00 is set to a logical 0, and then a third CAS strobe is applied to the array 16 to address the third word of the row. The two bit address is incremented ~ 5 again so that A01 an~ A00 are both logical 1~9 : and a fourth CAS s~robe is applied ~o the RAM array 16 therea~ter so that the fourth data word in the selected tile row is read and transmitted to the data controllers 20. ~he four words thus read from 10 each plane are stored in the associated data con-troller 20 and may be later writ~en to a different tile of the array in a similar fashion, using a RAS
strobe followed by four CAS strobes.
A data read or write operation for a vertical : 15 scroll would operate in a similar fas~ion except - that th~ Y counter 34 increments or decrements the data bi~s A07 and A06 such that ~he four word~ o~ a selected tile column are successively read or writ-: ten utilizing one RAS stro~e:followed by four CAS
strobes. For:an upward scroll, data wsrds of a tile column are read and written from top to bot-tom. Therefore the Y ~ounter 34 is incremented after each C~S ~;~robe~ Fvr a downward scroil, ~ .
: Y counter 34 is~re~enbe~afber.eacK ~A5.signal.
When the left or ri~ht edge of a ~indow to be vertically scroiled doe~ not coincide with the irst or last bi~ of a data word, the RAM chips :~ storing pixels lying out:side the window bou~daries -~ are no~ RAS strobed. Therefore only the data sets ; 30 of a boundary~word;corresponding to pixel~lying in~id~ the wlndow area are read and rewri tten : ~ during a~vertical ~crolling operation.
: : Thus the~til~e arrangement~of the present : inven~ion per~its:access t~ four sUccessive ~emory words during a~single memory~read or~write cycle.
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Since the four memory words accessed correspond to either vertically or horizontally contiguous pixels on the display 22, and since counters 30 and 34 can either increment or decrement the address, the four data words can be read left to right, righ~ to left, ~op to bottom, or bottom to top~ ~his allows rapid scro:lling in any of four directionsO
The plane 0 data controller 20 of FIG. 1 is depicte~
in more detailed block diagram form in FIG. 3. ~he topology and operation of each of the other data controllers associated with RAM planes 1-7 is similar.
During a memor~ read cycle, single bit data read from e:ach : of the six~een RAMs of any plane passes over data bus 60, ; through buffer 62 and 32/16 bit multiplexer 64, and into lS data register 66. The switching position of multiplexer 64 is controlled by a read/write indicating signal R/W
transmitted over one control line 26 rom the display processor. Once stored in data register 66, the sixteen bit data w~rd from the plane may be transmitted to the 20. display processor through bufer 68 and over data lines 14.
:~ Du~ing a ~emory write cycle, data to be written in~o the plane 0 R~s is initially stored in data register 66 and then transmitted to the RAMs through buffer 70 and over the plane 0 data bus 60. Prior to storage in register 66, ~n preparation for a me~ory write operation, the data to be written into memory is generated At an output D oE a rasterop traSter operation) combination logic circuit 82 ~described here;nbelow) and applied to a second sixteen bi~ input of multiplexer 64. Lo~ic circuit 3Q 82 has three 16 bit inputs A~, B and C and is adapted to generate the sixteen bit output word D, each bit of which is some selected Boolean combination of the corresponding ~ - bits o~ the three inputs A, B and C. The particular ;~ logical combination of inputs to be performed by logic circuit 82 is selected by preloading a rule register 86 with an eight bit word which is then applied to an input ..
logic circuit 82. This eight bit data word is loaded into rule register 86 by transmitting it from the display processor over data bus 14 and through buffer 76 and latch 78.
Referring to FIG. 4, a preferred embodi~ent of rasterop logic circuit 82, depicted in b]Lock diagram form, comprises a set of sixteen 8/1 multiplexers 96, labeled MUX 0 - MUX 15. Eight data llnes ~R0 - R7), one bit each of the rule data stored by rule register 86, are applied to the eight input terminals of each multiplexer 96. The first bit ~A0, B0 or C0) of each of the sixteen bit words appearing at the A, B and C input terminals of logic circuit 82 is applied to a corresponding one of three control inputs to ~UX 0~ Similarly, successive bits of the A, B and C inputs of logic circuit 82 are applied to the control inputs of successive multiplexers 96. The single bit output D0-D15 of each multiplexer of rasterop logic circuit 82 comprises a separate bit o~ the sixteen bit output D of logic circuit B2.
Each multiplexer 96 passes a data bit (a 0 or a 1) ~-~ carried by one of the rule register ~6 output lines . R0-R7 to the associated multiplexer output line D0-D15, ~r the R0-R7 line bein~ selected according to the three bit code A0-A15, B0-B15, C0-CIS appearing at the control ~: 25 terminals of the ~ultiplexer. Each multiplexer 96 ~ay therefore be programmed to genera~e an output D0-D15 ~ state on occurrence of any combination of the correspond-:~ ing A0-~15, B0-B15, C0-C15 input states simply by storing the appropriate eight bit data in rule ', : ' :
reqister 86 to appropriately set the states of the R0-R7 1 ines.
Referring again to ~IG. 3, a sixteen hit data word may be transmitted from the display controll~r over data bus 14, through buffer 76, latch 78 and 32/15 bit multiplex~r 80 and into anput C of rasterop combination logic circuit 82. The switchiny p~sition of multiplexer ~0 is determined by a contxol bit (SCR) carried on control lines 26 ~ro~ the display processor. ~he sixteen bit word thus transmltted by th~ di6play controller to input terminal C of logic circuit 82 may thet~ be modiied i f desired by logic c:ircuit 82 and passed through output D and multiplexer 64 to data register 66 for 15 storage therein and subsequent writing to a selected address o the plane 0 E~AM chips.
The 16 bit data word at input A of logic circuit 82 may be read from the plane 0 RAMs ~nd ~ransmitted through buffer 62 and 32/16 bit multi-plexer 92 and latch 94 to terminal A, the switchangstate of ~ultiplexer 92 being controlled by the . same ~/W control signal on control lines control-ling the switching state of ~ultiplexer 64. Al~er-natively, the data a~peari~g at ~erminal A of logic ~ 25 circui~ 82 may, during a ~e~ory write operation, be :~ transmitted ro~ the external control system to terminal A o~rer ~ata bus 14, ~ and through buffer 76, ~- latch 78, ~ultiplexer g2 and la~ch 94. The si~teen bit~word stored in data re~ister 66 continuously : 30 appears at input B of logic circuit 82.
The loading of regis~e~ and latches 66, 70, 86 and 92 is co~trolled by strobe ~ignals generated by address decoder 95 based on register addre6s appearing in address bus 24.
; 35 Durin~ a scrolling operation, the data re~d ~, ' ,i :~ ' .
from array 16 is stored i~ a first in, first out (FIF0) scrolling buffer 100 comprising a set of eight sixteen bit latches 102 ~LATCH l - LATCH 8), barrel ~hifter 104, and PIF0 control circuit 106.
Latches 1~5 are connected in series between the output of bufer 62 and one input of barrel shifter 104. The output of latch 4 is also applied to another input of barrel shifter 104. Latches 6-8 are connected in series between the output of barr~l shifter 104 ~nd o~e input of multipLexer 80.
FIF0 control circuit 106 selectively enables LATCHES 1-8 by energizing control lines El - ~8 connected there~o. With the latch enabled, the data appear;ng a~ its input also appears at its lS output such that the latch appears transparent to : incoming data. When a control input is deener-gized, the associated latch "latches" ~o that the .
latch output is fixed at its last state and is unaffected by la~ch inpu~ changes.
~ ~0 D2ta words read from array 16 duriny a scrol-:~ . ling operat;on pass from latch to latch in FIF0 bu~er lO0. The sixteen ~it output word of latc.h 4 .
and the sixteen bit output word o~ latch 5 comprise a thirty-two bit circular input word ~o barrel ~ 25 shiter 104. Barrel shifter lO~ generates a six-: tee~ bit output word comprising any selected ~ix-teen consecutive bits of the thirty-two bit circu-lar input word. The outpu~ of barrel shifter 104 beeomes the input to latch 6~ There are thirty diferent sets of sixteen consecutive bit~ in a thirty-two bit circular word and ~he particular set 6elected and outputted by the barrel shifter 104 ifi determined by a five bit data word SB applied to a :;
: 6hift control input of barrel shifter 104. This word i8 initially stored in a mode register 84 ., -, ' ~, ' ,j ~
after having been ~enerated by the display proces-sor and transmitted to register 84 over data line 14, and through buffer 76 and latch 78. The SB
word is then passed from mode register 84 throuyh FIFO control cireuit 106 to barrel shifter 104.
During a ~ert~cal scrolling operation, sets of four pixel data words of a tile column are read sequentially from array 16 using the RAS strobes followed by four CAS strobes as described above.
The CAS signals are carried on control lines 26 to FIFO control circuit 106. A system clock signal i~
also applied to FIFO control circuit 106 over con-trol lines 26. Initially all of the FIFO buf~er latches 102 are unlatched such that they all appear transparent to input data. As each data word is read, it is applied to the input of latch 1 o~ FIFO
; bu~fer 100. On the ~irst system clock signal fol-lowlng he fir~t CAS signal, FIFO control circui~
106 deenegi~eæ line El to }atch 1 ~ausing latch 1 to latch. Since all of the other la~ches are u~latched, the first da~a word falls through the . buffer to the outpu of latch 5. For a vertical scrolling:operation, the data SB applied to barrel shifter 104 is set such that the barrel shifter 25 . does not "shift", or in other words, the sixteen ~bit data at the output of latch 5 i8 passed ~hrough to la~oh 6 while the sixteen bits in latch 4~are ignorea by barrel sh~fter 104.
The passage of data:through most commercially 30~ availa~ barrel fihi~ters i:s relativ~ly slow ~om-pa~ed to the passage of data through a latch. Thus the ~irst data word may no~ have time to pass through the barrel shifter:104 during the fir~t fiy~tem clock cycle. :On the:next sys~em clock : ~ 35 cycle, control circuit 106 latches latch 5 and :
. .
, '~''' .
unlatches latch 1. Thus, when the next data word is read following a second CAS signal and sent to the FIFQ buffer, it passes through latches 1-4, but not latch S. In the meantime, the ~irst dat~ word passes through the barrel shif ter and at least through latch 6. On the first clock cycle ~ollowing the second CAS strobe, control circuit 106 latches latch 6 and latch 1 and unlatches latch 5. The f ixst data word passes to the output of 10 latch ~ while progress of the second data word thrc>ugh the buffer is stopp d at the output of : latch 5. On the next clock cycle, latches 1 and 5 are unlatched while latches 5 and 8 are latched.
I a third data word is read on occurrence o~ a : 15 third CAS signal, it passes through latch 1. On the ~irst clock cycle after the third CAS signal, latches 1 and 6 are latched while latch 5 ~ unlatche~. ~atch 8 remains latched. A~ this poi~t ; the ~irst data word appears at the output of latch :~ 20 ~, the second data word is halted at the input to ~ latch ~, and the third data word is blocXed at the :~ input to latch 6. On the next clock cycle, latc~es ~ and 6 unlatch while latches 5 and 7 latch. At this point, the ~ir6t data word appears at the outpu~ of latch 8, the seco~d data word appears at the output of latch 7, and ~the third data word appears at the outp~t o~ latch 5.
If a four~h data word;is read ollowing a fourth CAS ~trobe, it pas~es to latch 1. Latches 1 and 6 ~hen latch:while latch 5 unlatches, allowing the fourth data word to pass through to the output of latch 5. In a similar fashion, the fifth, sixth, seventh and eighth data words read ~rom memory array 1`6 are backed up in FIFO bu~er 100 at the inputs to latcheæ 5, 4, 3, and 2 respectively~
.. .` ~
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When the buffer is ully loaded with eight words, all latch~ remain latchedO
At any time after the irst data word is read and stored in FIF0 buf~er 100, the fir~t word and any subsequently stored data words may be sequen-tially passed from the buffer, through mul~iplexer 80 to input C of rasterop combination logic circuit 82. Logic circuit 82 may, if programmed to do so, modify the data in ~ome way, and then the modified lQ or unmodified pixel data is passed ~rom output D of logic circuit 82, through multiplexer 64 and into register 66. If the data ~as unmodified by ~ rasterop combination circuit 82, it may be rewrit-: ten to some other address o~ memory array 16 cor-:` 15 responding to a higher or lower position of the di~play~ thereby vertically scrolling the display.
Alternatively, logic ~ircuit ~2 may modify the data in some way~ as ~or in~tance by changing a bit ;; controlling pixel brightne~s or some other at-20 tribute, and the data may ~e written bac~ to the ~; same or another memory location. Thus the use of : ~ the logic circuit 82, in com~ination with ~he FIF0 :~ bu~fer 100, and the tile arrangement of me~ory ~: array 16, provides rapid alteration o~ selectea u~ 25 attributes of blo s or windows of ~he display, or rapid simultaneous al~ering and scrolling o the ~: display window~
~ When data is to be unloaded from ~IF0 buffer : lOO:and wrltten into memory array 16, multiplexer 30 80 is switc~hed to pass data appearing at the output of latch ~ to input C of logic circuit 80 by the SCR ~ignal on one lin~ o~ control lines 26. This data may then be modified and written ~ack ~nt~ men~ry ~~ as described above. Another line of control lines ~ 35 26 carries a scroll Fl~0 unload ~SFU~ signal which is applied to FIFO cont~ol circ~it 106. This 5ig-nal is ~enerated on occurrence of each CAS signal during a buffer 10~ unloading operation. When a CAS signal occurs, indicating that the data appear-ing at the output of Latch B has been passed toregister 66 and wrîtten bac~ into me~mory array 16, the SFU signal goes low, te~porarily. On the next clock signal, latch 8 is unlatched allowing the data at its input terminals to pass to its output.
On the next following cloc~ cycle, latch ~ is latched and latch 7 i5 unlatched, permitting the ~` data at the latch 7 input to pass to the latch 8 inpu~. The proc:ess continues with eac~ clock cyc:Le until all of the data stored in buffer 106 has been lS shifted by one latch. In the meantime, once latch 8 has latched the second data word appears at its output an~ may also be passed to register 66 and : ~ written to memory on the next CAS strobe. The FIF0 control circuit continuously ~hifts data from la~ch : 20 to latch whenever the preceding data has keen shi ted.
~ ~ .
he ive latches preceding the barrel shifter 104 permit at least five data words to be read~in . ~ rapid succession and stored in the buffer 1()0 ~` 25 regardless: of the speed of the barrel shifter.
Similarly, the three latches following barrel shif-:, ter ~104 allow ~our data words to be unloaded from th~ :buffe~ and written in~co m~mory in rapid succes-ion as long as the b rrel shifter~ 104 can process 30 ~ the fourth word duri:ng the time interval in which the set of ~our words i~ written to inemory.
: Typically the time required for ~our data words to pass~hrough the relatively slow barrel shifter is ~- needed for: s:~ther purposes, such~ as: a screen refresh 35 : operation, and is ~here~ore nonlimi~ing, provide~
, ' : . .
. '.': ~ ": .
.
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1~
that the barrel shifter is located in the middle of the buffer and ~ot at either end.
During a horizontal ~crolling operation, the barrel shifter 104 i6 set by the SB data in m~de register 84 to select one sixteen bit subset of the data appearing at the outpu~s of latch 4 and latch 5 as its sixteen bit output. Since ~he thirty-two : bits of the two input words correspond to thirty-two horizontaIly contiguous pixels of a display, 10 and since pixel data is read and written in sixteen pixel blocks~ it may be necessary to shift the position ~f each pixel within a word by so~e nu~ber ~: of bit positions after it i~ read but be~ore it is rewritten back to the memory array 16. This bit position shifting is required i the distance of the horizontal shi~t is not a multiple of 16. The magnitude of the bit position shift correspond~ to the number of bits o the aata word appearing at the output o~ latch ~ that are incorporated:into the data word appearing at the output o~ the barrel shi~ter 104 and is controlled by the SB control input to the barrel shifter. The direction of the it position shift dépends on whether the data in latch 4 is phy~ically to the left or to the right of ~he data in latch 5 with reerenc~ to ~he rela-tive positions of on the display of corresponding pixels.
The loading o the FIF0 buffer 100 during a :~ horizontal s~roll~ng opera~ion inYoiving a bit 30 ~ position shift is generally ~i~ilar to th~ loading o~ the ~u~fer wh~n no bit position ~hift i8 r~-~:: quired exce~ ~hat latch 5~remains latched until ~: latch ~ latches and la~h 6 won't latch until after ~ ~ latch 4 latches. This ensures tha~ two sequential-;~ 35 ly read data words appear at the outputs of latches :: , ~., . . . .
~ ~ :
4 and 5, the inputs of barrel shifter 104, before : the output of the barre~ shifter is latched into latc~ 6.
When horizontally 3crolling from left to 5 righl:, the fourdata words in a tile row are read in right to left order and loaded into the buffer.
Thus the X counter 30 i decremented after each CAS
signal. If the left to right horiæontal scroll involves a shift that is no~ an even multiple of 10 sixteen pixels, then ~he barrel shifter is set to ~- genera~e data words wherein the high order bits ~: (rightmost) compris~ an app~opriate number of low order bits of the word in la~:ch S while ~he low ;~ order bits comprise high order bits of the word in 15 latch 4.
~ hen horizontally scrolling from right to l~f'c, the four data words in a tile row are read in left to right order and loaded into the buffer.
Thus the X coun~er 30 i~ inoremerlted after each CP~S
20 signal. If the ~croll introlves a shift ~hat is not:
an e~ren ~multiple of sixteen pixels, then the barrel ~:~ shi Çter ifi set to generate data words w~erein the high order bits co~pr~ise ~ an appropriate number of low order bit~; of the word in:latch 4 while the 25 low order bits comprise high order bits of t~e word in latch 5 .
FIG~ 5 is a blocX diagram of an embodiment of the FIF~ control circuit 106 of FIG~ 3. ControI
ircuit 106 co~pri~es a set of eight D-type flip-30 flops, FFl to PF8, ~ach having a ~ out~ut (labeled ~:~ : Ql to Q8 ~ for ~lip-flop~ ~1 to FE?8 respec~tivel~r) ollpled 'c~rough a buf fer to a corresponding control line ~E:l-E8 to a~ corresponding latch 102 of the FIF0 buf ~er 100. Control c~rcuit 106 also c:omprises a 35 ~ read only memory ~oM3 112 having eight data output ,~
`.
::
.
lines, each one connected to a D input of a corres-ponding flip-flop 110. The D inputs are labeled Dl to D8 for flip-flops Dl to D8 respectively. The eight Q outputs of the eight flip-flops are also . coupled to eight address line inputs of ROM 112.
set of four control lines 26 from the display processor, also applîed to four other address line inputs of ROM 112, include the CAS line, a scroll FIFO load (SFL) line, a ~croll FIFO unload (SFU) line, and a scroll FIFO clear (SFC) line. The :~ five SB bits from ~ode register 84 are applied to the inputs of an OR gate 114 while the output of ~ the 0~ gate is applied to still another address :: line input of ROM 112. A clock signal CK carried on another control line 26 is applied in common to the clock inputs o~ all flip-flops 110.
The Q output o each ~lip-flop 110 changes state ts match the current state of its D input : whenever the flip-flop is strobed by a CLK pu~se.
20 ROM 112 in combination with flip-flops 110 com~
prises a state machine wherein the current state of the D input of each flip-flop can be made high or low depen~ing on the collective states of all of the fl;p-flop 110 Q outputs together with the states of the other addressing inputs ~o the ROM.
The rules of correspondence between the ROM inputs and outputs are established by ~he data stored in : the ROM. FIG 6 is a chart which expresses th2 relationsh~p bet:wes~ the Dl-D8 outputs of the ~OM
and all of the inputs therat~. For each output Dl-8, thére ls listed a Boolean express.ion indicating under which input conditions the D output will ~e : high. When the expression is true (a logical 1), `:~ he corresponding D output will be true, and when the expression is false, the D output will be low.
,~
.
~ . :
'' ~.' ~ . ' .. . .
~2 Ei~
With ~he data of ROM 112 adjusted to effect these expres~ions, loading and unloading of the FIFO
buffex 100 will operate as previously described.
To clear data from the buffer, the SFC signal is driven low. A~ all other time~ SFC is high. A
low SFC signal causes Q2, Q3~ Q4, Q5, Q7 and Q8 to go high on the next cloc~ C~ cycle. ~hen, on a second CK cycle, Ql and Q6 go h;gh. With all of the Q outputs high, the E control inputs to all of the latches of buffer 100 go high, maXing them all - transparent. Initially, when ~here is no data stored in FIFO buffer~100, all of ~he Q outputs of flip flops 110 are high ~o that all of the latches are transparent. The CAS signal is used in the expression for Dl to cause latch 1 to latch after each CAS signal. The SFL signal is normally low except when the display control7er wishes to load : data into the bu~er 100. In such case, SFL is :
driven high at the same ~ime a~ the CAS signal, and stays hi~h for one CK cycle the~eafter. The ZS~
signal from OR gats 114 of FIG. 5 is high if any :one of the SB bits~is high, indicating that the barrel shiter is ~hif~ing pixel bit posit~ons o~
the data pa~sing through it. The ~SN signal i~
used in the expresslons of D5 and D6 to prevent :
la:t~h 6 ~ro~ latching or ~latch 5 from unlatching u~til latch~4 lat~hes. The SFU ~ignal is high ex~ept~when the~d~splay con~roller;has rcad data : : from~:th~ bu~ferO~ Thèn the~.SFU signal is::driven low :: 30 for:`one C~ cycle to 1nitia~e a~shift~o~ data~
through ~he:bufe~ The~SPU signal i8~-there~ore :~
: :~u~ed in the ~xpression ~or:D8, causing DB to yo -- high when SFU goes lQw:su~h that on the nex~ CK ;
:~ cycle Q~ goes high :to unlatch latch 8~ ;
~ While it is Fssibl~ that FIFO buf~r 100 , ''.
: ' ., ~3 could operate asynchronously, passing data from latch to latch without regard to a sys~em clock, the synchronous FI~O buffer of the present inven-tion requires latching to occur in concer~ with ~he 6ystem clock. ~herefore the disp~ay c:ontrol~:er c~n keep track of where data is in the FI:FO ~uffer at any given instant and can access the buffer without requiring asynchronous control 6ignals such as input ready or output ready.
While a preferred embodiment of the present inYention ha~ been shown and described, it will ~e apparent to those skilled in ~he art th~t ~any changes and modifications may be made without de-parting from the invention in its broader asp~cts.
The appended clai~s are th'erefore intended to cover : : all such changes and ~odifications as fall within the true spirit and~scopeiof the invention.
~:: 20 .- - , . ~ : :
: 35
Claims (2)
1. An apparatus for storing and bit shifting a sequence of data words comprising:
first means for receiving and storing first sequence of data words, and for outputting said first data word sequence in the same order as it is received;
means to store a next to last data word outputted by said first means;
means to output a second data word sequence, each word thereof comprising a selected number of bits of said last data output word and said next to last data output word;
and second means for receiving and storing said second sequence of data words, and for outputting said second data word sequence in the same order as it is received.
first means for receiving and storing first sequence of data words, and for outputting said first data word sequence in the same order as it is received;
means to store a next to last data word outputted by said first means;
means to output a second data word sequence, each word thereof comprising a selected number of bits of said last data output word and said next to last data output word;
and second means for receiving and storing said second sequence of data words, and for outputting said second data word sequence in the same order as it is received.
2. An apparatus as in claim 1 where said storage and said outputting of said first sequence of data words by said first means, said storage of said last data word and said outputting of said storage and said second data sequence by said second means are synchronized to a system clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000584636A CA1264494A (en) | 1985-04-05 | 1988-11-30 | Frame buffer memory |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/720,659 US4755810A (en) | 1985-04-05 | 1985-04-05 | Frame buffer memory |
| US720,659 | 1985-04-05 | ||
| CA000504401A CA1258716A (en) | 1985-04-05 | 1986-03-18 | Frame buffer memory |
| CA000584636A CA1264494A (en) | 1985-04-05 | 1988-11-30 | Frame buffer memory |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000504401A Division CA1258716A (en) | 1985-04-05 | 1986-03-18 | Frame buffer memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1264494A true CA1264494A (en) | 1990-01-16 |
Family
ID=25670940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000584636A Expired - Fee Related CA1264494A (en) | 1985-04-05 | 1988-11-30 | Frame buffer memory |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1264494A (en) |
-
1988
- 1988-11-30 CA CA000584636A patent/CA1264494A/en not_active Expired - Fee Related
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