CA1257004A - Parity integrity check logic - Google Patents
Parity integrity check logicInfo
- Publication number
- CA1257004A CA1257004A CA000505952A CA505952A CA1257004A CA 1257004 A CA1257004 A CA 1257004A CA 000505952 A CA000505952 A CA 000505952A CA 505952 A CA505952 A CA 505952A CA 1257004 A CA1257004 A CA 1257004A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- data
- parity
- error detection
- check bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims abstract description 38
- 238000012795 verification Methods 0.000 claims abstract description 15
- 230000004044 response Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 3
- 238000012545 processing Methods 0.000 claims description 18
- 238000012546 transfer Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101150114656 DPOL gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/734,295 US4670876A (en) | 1985-05-15 | 1985-05-15 | Parity integrity check logic |
US734,295 | 1985-05-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1257004A true CA1257004A (en) | 1989-07-04 |
Family
ID=24951089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000505952A Expired CA1257004A (en) | 1985-05-15 | 1986-04-07 | Parity integrity check logic |
Country Status (9)
Country | Link |
---|---|
US (1) | US4670876A (no) |
EP (1) | EP0201907B1 (no) |
JP (1) | JPS61265641A (no) |
AU (1) | AU589616B2 (no) |
CA (1) | CA1257004A (no) |
DE (1) | DE3678751D1 (no) |
NO (1) | NO170113C (no) |
SG (1) | SG17293G (no) |
ZA (1) | ZA862885B (no) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2179179B (en) * | 1985-08-12 | 1989-10-18 | British Gas Corp | Improvements in or relating to burner control systems |
JPS63102517A (ja) * | 1986-10-20 | 1988-05-07 | Nec Corp | 機器障害信号伝送方式 |
GB2200476B (en) * | 1987-01-29 | 1991-02-06 | British Gas Plc | Monitor system |
US4809273A (en) * | 1987-01-29 | 1989-02-28 | International Business Machines Corporation | Device for verifying operation of a checking code generator |
US4817095A (en) * | 1987-05-15 | 1989-03-28 | Digital Equipment Corporation | Byte write error code method and apparatus |
JPH01201736A (ja) * | 1988-02-08 | 1989-08-14 | Mitsubishi Electric Corp | マイクロコンピュータ |
US5107507A (en) * | 1988-05-26 | 1992-04-21 | International Business Machines | Bidirectional buffer with latch and parity capability |
EP0348240B1 (en) * | 1988-06-24 | 1996-05-08 | Nec Corporation | Microprocessor equipped with parity control unit on same chip |
US4962501A (en) * | 1988-09-13 | 1990-10-09 | Unisys Corporation | Bus data transmission verification system |
AU628971B2 (en) * | 1989-05-22 | 1992-09-24 | Tandem Computers Incorporated | Sequential parity correction |
US5195093A (en) * | 1991-02-14 | 1993-03-16 | Motorola, Inc. | Method and apparatus for ensuring CRC error generation by a data communication station experiencing transmitter exceptions |
JP3241110B2 (ja) * | 1991-12-26 | 2001-12-25 | 株式会社東芝 | 半導体記憶装置 |
US5612965A (en) * | 1994-04-26 | 1997-03-18 | Unisys Corporation | Multiple memory bit/chip failure detection |
US5515506A (en) * | 1994-08-23 | 1996-05-07 | Hewlett-Packard Company | Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle |
US6393385B1 (en) * | 1995-02-07 | 2002-05-21 | Texas Instruments Incorporated | Knowledge driven simulation time and data reduction technique |
US5701313A (en) * | 1995-02-24 | 1997-12-23 | Unisys Corporation | Method and apparatus for removing soft errors from a memory |
US5666371A (en) * | 1995-02-24 | 1997-09-09 | Unisys Corporation | Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements |
US5511164A (en) * | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
US5872910A (en) * | 1996-12-27 | 1999-02-16 | Unisys Corporation | Parity-error injection system for an instruction processor |
US7127646B1 (en) * | 2000-06-07 | 2006-10-24 | Lsi Logic Corporation | System and method for generating real time errors for device testing |
US7447948B2 (en) * | 2005-11-21 | 2008-11-04 | Intel Corporation | ECC coding for high speed implementation |
US8612834B2 (en) * | 2011-03-08 | 2013-12-17 | Intel Corporation | Apparatus, system, and method for decoding linear block codes in a memory controller |
US10522237B2 (en) * | 2015-08-07 | 2019-12-31 | Mentor Graphics Corporation | Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5283046A (en) * | 1975-12-30 | 1977-07-11 | Fujitsu Ltd | Check system of error detection circuit |
JPS5441497A (en) * | 1977-09-07 | 1979-04-02 | Hitachi Ltd | Piezo-electric porcelain composition |
US4223382A (en) * | 1978-11-30 | 1980-09-16 | Sperry Corporation | Closed loop error correct |
US4360917A (en) * | 1979-02-07 | 1982-11-23 | The Warner & Swasey Company | Parity fault locating means |
US4360915A (en) * | 1979-02-07 | 1982-11-23 | The Warner & Swasey Company | Error detection means |
US4327408A (en) * | 1979-04-17 | 1982-04-27 | Data General Corporation | Controller device with diagnostic capability for use in interfacing a central processing unit with a peripheral storage device |
US4295219A (en) * | 1980-03-31 | 1981-10-13 | Bell Telephone Laboratories, Incorporated | Memory write error detection circuit |
US4359771A (en) * | 1980-07-25 | 1982-11-16 | Honeywell Information Systems Inc. | Method and apparatus for testing and verifying the operation of error control apparatus within a memory |
US4531213A (en) * | 1982-03-03 | 1985-07-23 | Sperry Corporation | Memory through checking system with comparison of data word parity before and after ECC processing |
JPS58198935A (ja) * | 1982-05-15 | 1983-11-19 | Sony Corp | デ−タ伝送方法 |
US4561095A (en) * | 1982-07-19 | 1985-12-24 | Fairchild Camera & Instrument Corporation | High-speed error correcting random access memory system |
-
1985
- 1985-05-15 US US06/734,295 patent/US4670876A/en not_active Expired - Lifetime
-
1986
- 1986-03-17 NO NO861012A patent/NO170113C/no unknown
- 1986-04-07 CA CA000505952A patent/CA1257004A/en not_active Expired
- 1986-04-08 AU AU55750/86A patent/AU589616B2/en not_active Ceased
- 1986-04-17 ZA ZA862885A patent/ZA862885B/xx unknown
- 1986-05-13 DE DE8686106457T patent/DE3678751D1/de not_active Expired - Fee Related
- 1986-05-13 EP EP86106457A patent/EP0201907B1/en not_active Expired - Lifetime
- 1986-05-14 JP JP61110434A patent/JPS61265641A/ja active Pending
-
1993
- 1993-02-17 SG SG172/93A patent/SG17293G/en unknown
Also Published As
Publication number | Publication date |
---|---|
SG17293G (en) | 1993-04-16 |
US4670876A (en) | 1987-06-02 |
EP0201907A2 (en) | 1986-11-20 |
AU589616B2 (en) | 1989-10-19 |
NO170113C (no) | 1992-09-09 |
JPS61265641A (ja) | 1986-11-25 |
DE3678751D1 (de) | 1991-05-23 |
NO861012L (no) | 1986-11-17 |
NO170113B (no) | 1992-06-01 |
ZA862885B (en) | 1986-12-30 |
EP0201907B1 (en) | 1991-04-17 |
EP0201907A3 (en) | 1989-04-26 |
AU5575086A (en) | 1986-11-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry |