CA1235821A - Data processor having module access control - Google Patents

Abstract

DATA PROCESSOR HAVING MODULE ACCESS CONTROL

Abstract of the Disclosure A data processor (12) cooperates with an access controller (14) to control access to a module stored in a storage device (20). In response to receiving an instruction which requests access to the module and specifies an address within the storage device (20) containing an access request, the data processor (12) retrieves the access request and provides the access request to the access controller (14). The data processor (12) will then initiate the requested access.
However, the access will be faulted if the access controller (14) decides to deny the access request.

Description

~3~
DArrA Pl~CESSOR lHA~l~NG I~QDllLE ~CC~SS SO~ L
~1~ .
The ~re~ent ~nvel~tqo~ re~t~ ~ener~ to a d~t~
~roce~or~ arld " ~ore ~articulas~ to ~ data proce~or 11~Y1 a~ ~c>dule ~cce~ ~ontrol ~Dechani~O

In ~Dan~ data ~r~ce~ors9 t~e ea~e¢l~tlng program ha~ the ablllty to ac~e~ any ~d~res th~n the ~d~re~ 8~ e ~,enerall~ ~Y~ila~Dle to the proces~ob~. ~n IDany ot~er dat~
~proce~or~ " ~cce~ llmitatlon~ ~re l~posed upor. ~ u~er pro~,ram~ lbut not ~p~n the supervl~or ~rogram. Typie~lly, the ~ce~s li~itatlons ~re ~n the form of addre~ ran~e or ~pace liwlt~ ignp~sed by hard~are. Another oommon li~itatlon 1~ the i~sDp~ltion o~ wrlte ~rotecti~n upon certaln deslgn~ted addre~s ranges which ~re otherwl~e ~2cessible to the user lpro ra~.
In ~ome other ~y~tem~ ~ the a~3pervi~or progra~ incll~des number of' ~service rol~tine~ for performing input/oul~p~
operatioDs and other neces~ary ~ystem functlon3. ~n g~neral, ~uch routi~e~ are con~ldered t3 be privileged ~ ~d ~11 acce3~e~ thereto b~ u~er programs typic~ resul~3 in traps to an approprlate prlv~le~e violat~on ~andler ~itbin tlhe ~uper~risor pro~ra~0 ~n ~5UC~ imple~entationsD t~e handler 1~
r esponsible î or deciding 1~ the reque~t ~hos~ld be tlonored ., II
the decislon ~B sfrir~atlYe, t~e handler enable~ the reque~ted ~ærYice tr be perforsDed bef~re eontrol i5 tran~ferred b~ck to the u~er ~rogr~D ~ile tlhi~ ~ofk~re l~plemented ~ece~s control ~ech~n~3~ qullte ~er~stile, the o~erhe2d ass-~ciated ~th ~uch a ~Inechanls~ i3s îar ~rom ~nsignif'~cant~
In ~me other data ~roce~or~, ~ucb ~ the DlBital Eq~ipment Corporatio~ ) and the National Semiconductor ~SC16000 l!Dîcrcproces~or,l a prog~ a~ be ~onfl~ured a~ t d~ka~code ~u~d~le~ ~hich ca~n be l'Galled'5 a ~ppropr~t~ by ~L2 othe~ e~ nd ~ a~le~ ~o~ul~ q o~ i~
~e~urne~ u~ lowe~ t~e~2 ~ e~
pro~de oo ~ec)~an~s~ ~or ~ontrollqrl~ ~ccea~ to ~l3eh Dod~e~.
Th~ the ~D~dule s~all ~n~trll~ti~n 18 ~o~p~rable to ~
con~eDt~onal brarlch'60- ubr~utine ~n~tr~t~on ~here~n tbe d2ta ~roce~or uould ~i~Dpl~ ~tack a~a~ oD&o ~ er st~X cert~ln retur~ ~n~or~at~on before bran~hing ~o the ~ppro~r~al~e ~rt~g ~r~ ule O ~ f ~he~ 7 thl~ ~t~rtin~ ~d~re~s ~8 ~rt of ~ dule de~crlpt~ hioh 1~ c~nstructed b9 the co~pîlerJa~sem~Dler ~Dd linker ~D the pr~e3s of ~reatln~ ~n e~ecl~table lo~d module. Other ~nf~r~nation r~l~tln~ to the ~od~le ~s3ay ~l~o be ~roYlded q n t~e ~d~ïe descr~pt~rD
~ n t~e General Electric GE645 ~hULTICS~ ~) machine, and, more recentl~r9 in ~ome of the IDachlne~ o~fered co~lDerclall~ b~
~r~e Co~Dputer~ and D~ta Gener~l, each ~p~ge~ of the ~vailable ~ddress ~pace ~ithln the ~sy~tem ~e~ory h~s ~s~oclalted ~lth lt an aoce~s le~el ~ ~reatin8 ln effect ~ ~et of conoentrlc " rin8s~ of protect~on . ~lthough the l~umb~r of rlng~ may ~ary, the mo~t ~en~itiYe data/code loodule~ are typlcally ~tored within t~e innermost rin8 and the u~er ~dule~ are b~ithin the outer~nost r~n~9 tlhe b~lance of the ~u~erYi~or program ~.,n ~oclsted ¢ompiler~/a~sembler~ bein6 approprlatel~
dl~stributed alDong tbe Y,everal a~ ble r~3. In order to obtain ~cceJs to data~code ~odules stored withln the inneral~o~t rin6, the calling llDodul~ IIDU~t haYe been granted the ~ighest acce. s l~el~ ~hile oe~en tho~e ~Dodule. haYlng the lo~1est ~cce~s le~el can ~ccess module~ ~tored is~ lthe o~ltermo~t rlng.
In th~ re use~ul for~, the call ~od~e in~tructlon ~llo~s a u~er ~progra~ corltrolled acce~ to d~tR0cod~ ~Dodule~ ~hlch t~e ~y~te~ lhe~ to ~roltect again~t u~authorized ~e~
In ~ t~pical d~ta pr~c~slng ~yste~ cb ~plements a~
02~5 c~ntroî ~Declhanl~D; tbe ~uper~ 3r progra~ ~as the responsib~lity of ~a~n~n~ ~cce3~ el~ to eac~ OI the ~er ~ro~,r~ms ~hich are lost~lled ~ th~ ~gs~se~O For ~e~a~Dple 9 ~OIDe r~ ,, b~au~e ~ g`n~ De ~s ~ d ~ h~ r ~ce~ ~r~lege than o~her U~el'8 of t21e ~a~e progr~
~lEnllarl~r " di~erent pro~ram3s, be~u~e o~ thelr na ~ur@ 9 ~ay requlre ~i~her $¢~eS2s l~V~ S than other ~rogram~. On ~he otlher barld ~ all ~ t~e pro~ram~ ~11 t~plcally req~lre ~c. e35 to those ~l~dule~ o~ tlhe ~upervi~or program e~hicb perfor~
QolDmori ~npllt/out~ut ~nd related 8er~ice fun~tlorl~ The c~ll IllOe~Ule l~lleCh~ilni8~ ac1li~ate~ Ju~t ~u~ a dynaD)~c ehange 1D
~c~e~ le~
During the co~pilatlon~assembl~ and lînk~ng proce~ the ~upervisor proglo~m ltyp1cally 1n1t1al~ze~ the ~odule de~crlptor~ metl~e3 referred to a~ ~egmenlt de3cr1ptor~3 to contain lnformatlon relat1ng to the address of the re~pect1~e ~odules and to the ~cce~s level thereof. Depend1r~g UpO~l the requirement~ of the ~ystem ~ the~e de~cr1ptor~ ~a~r be ~kored e~ther ~ilthin or b~ithout tltl2 ring contalnlng the respectlve ælodule~,, The addre~es of the~e de~crlptor~ are there~fter ln~erlced lnto the appropriate call ~odule 1nstruction3 ln the r.a~ llng ~nodule and the linked pro~ram in~talled lnto an appropriate ~torage Dlledlum ~ithln the 3y~tem re~ourcesO Thus~, ~hene~er the pro~,ram i~ eReouted, t~le ~upervisor program can be 3ure t;bat all Dl~odule ~119 ~ade by that progra~ ha~e previously been approved~ However~ the pr~ram mu~t ~till be prevented froDI e~tendlng the hi~her le~el acce~s pri~llege be~rond the authorized module. This dynaml~ access contl ol flan~tlorl i~ typl~ally handled by an acce~s controller DplemeDted ~ilthin the dat~ proces~or lt~elf or ln a a~lemory ~anagemeDt unit ~3hical i~ tig~tly coupled t~ the data proce~sor. Ia~ ~seneral " the ~c~e~s co~troller ~oD~.tors each a~ces~ to t~e ~y~te~ $torage to determine that th~ acsess le~rel of the currently e~ecutlsl$ ~oodule lS greatel than or equal to the aocess leq~l of the a~ce3~ed pageO If ~o, the acce~s i~ allo~ed; lir n~t, the acee~ aulted to îorce the ter~lnlnation oiE the ~alllD8 m~dule~ ~heneYer ~ ca.l ~nodule lnstFu~tion 1~ ea~ecuteB" tt3e data pro~e~sor notlf~e~ t~e ~cce~ c~ntroller t~at the ao~e~s le~gl ~ust be ~ha7~ged to higher le~¢l9 ~ n~ce~ary~ to @nable t~le ¢alled sDodllle to ea~ecute. The ~cce~ ~ontroll2r ~aould therea~tcr allo~
~cce~se~ to pa~e~ b~ g tbe hl~sher ac~e~ leovelO Up~n e~ce~util~g ~ ~orr~spondlslg ~retur~-fro~D ~odule~ lnskructlon, the d~t~ F~roce~oro order~ the ~ce~ ~ontrol to change the ~o~e~ let~el back to the orl~lnsl leYel vf the calllng aDodule~
ID ~O~e 8y~Stel~8 j~ each accea~ le~el ha~ a ~ lt of ~gate~
as~ocl~ted lthere~lth~ each of whi¢h oan bg ~openW or ~closedll ~t the d~3cretion o~ the superYi30r progra~D0 Xn general 7 if a particul~r module ls ~oing to be made acces~ible to user pr~grams h~vlng ~ ~artieul~r acce~s leYel~ the ~upervl. or program ~ill open a 8ate ~o that ~Dodule by torlng ~he de~crlptor ~or that ~odule ~lthirl a partlcular Bate 1;able at that aocess le~rel; wlthout ~uch an entry, ithe Bate ~ill be efg'~cti~el~r clo~ed. Thereafter, a oalling ~odule ~an request acce~s to a ~odule by spec~ying the nu~ber of the gate ~ithin the calling modul~s access le~el ~hich controls acce3s to tlhe ~esired ~odule, together ~ith the index int~ ~he re~pectiYe gate table ~t which lthe modul~ descriptor is ~toredO If the ~cce~s ¢ontroller ~rif`ie~ that ~uch an entry actually esi~ts, the processor i~ allo~ed to establi~h the approprlall;e acce~s le~rel ~nd pathway to the ~alled ~Dodule u~in~ the lnformalt ion contained in the IDodule descrlptor ld~ntifi~d in the c~ll module in~tru~t~on; other~ se the acoes~ aulted lto f~rc~
t~e ter~inatlon Or the callln~ ~odule . Upon egi tlDg fro~ the called D~dule" th¢ prs~e~sor ree~tablishe~ the orîglnal acce~s le~el o~ the ¢~llin$ ~odule before returnln~ ~ontrol theretsl.
I sddltioll to dedlcatlng ~i~nific~nt ~tora~e ~pace for the gate t~le~, thiC tec]hnlque require~ a ~i~n~flcant amc>unt of ratber co~Dple~ c~ r~ try to lmplelDent t~e t~ble l~okup ~unctlo~ ~, 5~o~
~ccordi~ " it ~ an obgect of t)le presenS lnYentiol~ to ~ . d ~L
pro~ld@ ~ d~.a pro~e~oY h~in~ ~n llnpro~d ~Q~ule ~CCC5 ~ n6:sther ~ect ~ to prov~dle ~ ~Qdule 8:~:ce~3 con~rol ~echani~ ~h~ch doe~ Dot reql3ire the dalta ~roce~r to be concerned ~i'ch thQ crlteria ~lnder ~hlch accc~ gr~ntedO
lret ~notlleP ob~e~t ~B tiD ~r~lde a data proce~or ~hereln an acoe~ ntroller lndependent of the data proce~or declde~
~or the dat~ ~roce~0r ~hether a re~uested acce~ ~hol31d ~e Still ~nother ob,~ect i~ to pro~de an e~iclellt mech~nls~
for a data ~rocessor to ~ooper~te ~dlth an 1DdePendent access eontroller ln She ~ontrol of 8CCe~S tO a ~od~le ~tored ln ~y3tem $1torage.
One other obJect of the present in~rerltlon i~ t~ proYide an lmproYed ~ate mechanlsm for an ac~e~s corltroller to dlrectl~
co~ltrol ~cces~ to the ~y~em ~torage by module e~eout1ng in a data proce~or.
These ~nd ot21er ob~ect3 are achleYed ln a d~ta processor whioh ha~ been ad~pted in acoordance with the pre~ent lnvention to co~perate with an acoes~ oontroller ~o r:vntrol a¢cess to n module ~tored in a ~tora~ deYice. In the IDO~t ba~lc fvr~ clf the pre3ent ln~ent1on9 the data proce~30r 1~
~on~tructed to recel~e ~n lnstructlon b~hich re4ue~t~ acce~s3 to the oodule, the ln~truction ~peclfylng an aàdres~ ~ithin the ~tora~e deYice containlng an accesss reque~tO U~ing the ~ddres~ ~peclg`~ed ln the in~tru~tlon5, the data proce~or retrie~?es the acces~ reque~t and ~roYlde~ the acce~ reqoe~t to the ~cce~s c~ntroller. The data proce~or then inîtlalte~
the re~uest~d aC~e~s to the ~odule O ~]o~ever ~ the acce~s b~ill be fsult,ed lf the acce~ controller deslde~ to den~ t~e ~ccess request .
In tlhe preferred for~n of O~e pre~nt i~entlon " the data proce~sor requests lthe decl~ion of th~ ac~ess controller to the ~cce~ re~ues'6 before ~tt~a~pt~ ;he re~ue~ted a¢~e~sO If the decl~loll of t~e ~ece~ ntroller 18 sf~ tl~re 9 the data ~L~3~
proce~s~r allo~7~ acce~3 t~ the Do~lul/e. Ho~e~eP~ ~ tlne de~l~ion o~ k~e ~ce~ ntroller i~ neg~tl~re, l~he d~ta pr~ o~ ~en~ o l~h~ du~
In eltlh~r ~ t'ln9 tlhe data proce~or need not be a~ar2 of lt))e aC:Cæ!55 crlteri~ being i~3po~ed b~ the ~ ce~ con'croller.
~hus 9 the form and content ~f the acee~ re~uest sDay be changed to slilt 8pe8~1~1c r eQulrement~ ~lthout ch~nglng the data pr~ e~os and the ~Danner in ~hic~ t~e ac~ess ~ontrol echanl~ implemented thereln,, Fl~llre 1 l~ a bloclc dla~rasD of ~ data proces~lng ~y~tem ~uitable for prac~lclng t~e pre~ent inventlon~
Figure 2 l~ a block dla~ram of the ~ata pr~cessor of Figure 1.

Sho~rl in Flg~re 1 i3 a data prooessing ~3y~1;em 1C ~herelr~
loglcal addres~ LI~DDR) is~ued by a data proce~:~or (DP) 1 are mapped by a memory manaBement UDlt tMMU) 1~ to a corre~po~dlng phy3ical addre~s tP~D~P~) for output on ~
physi~al bus t PBUS~ 16 0 Slmultaneou~l~, the varlous loglcal acce~ control ~ignals (LCNTL) provided by DP 12 to co~trol t~e ~cce~ss are converted to approprlately timed physlc~l acoe~ co~'crol ~i~nal~ (PCNTL) by a modifler unit 98 u~der the control OI ~SMU 1~ D the preferred for~, DP 12 i. adapted ~D
accordsn6:e ~ith the pre~ent lnverltion to c~operate ~lth an acce~s controller lmplellDented, for ea~ample1 ln ~5MU 11~ ~o con'cr~P acce~ to data ~nd code ~ tored as ~odule~ the memory 20 Ill respo~e to a particul~r r~nge of phy~lcal addre~e~
~P~DDP~) " ~emory 20 ~ operate ~ith an error detectlon and corre-~tion circuit (EDAC) 22 to ~chang,e data ~DI~T~ ~lt~ DP
1? ln ~ynchro~l~atioll ~dith the ~h9r~lc~l acce~s ~olltrol slgn~l~
(PC~aT.Y_~ on PlBllS 16. Upoal detecti.ng ~ID error lo th~ data9 ED~C

d r ~7o

2~ tlher ~i6r~ bu~ error ~l~ERR) or reque~t D~ 12 to a~try gRETR~ t~e ei~har~eg dependl~ upor~ the t~e ~i` erro7.
pon~e ~ d~ r~ ph~ l add~ 8 ~or~e înterf~e 2~ operate ~rl1;h ~lP 12 to tran~fer dats3 g~ ~r ~rom ~nas~ ~tora~e 261~ n error oc~u~ dunln~ the tran~fer7 lnterf~9ce 2a~ ~a~ nal a lbsu~ ~rror tBERP~) OrD l~f approprlateg r~q~ t ~ ET~
In t~se ev~nt 1;hat 9the MMll 9~ l~ unable to m~p a ~rticular loglc ~ddre~ (LADD~ lnl;o a corre~p~dirl~ physlcal addres~
(P~DD~ 9 the HMU lb, ~7ill ~slgnal ~rl scce~ ~al~lt ~IILT~ s c:heck ~or MMU 1~ atchdog, ti~@r 28 ~ay be proYided to ~ignal ~ bus error ~BERR) 1~ DO ~hysgc~9 de~ice has resp~nded tl~ a ph~ lcal addre~ (P~DDR~ ~ithin a su~table tl~e ~erlod relatlve lto the phy~i~al ~ce~s ¢ontrol ~ignal~ ~ PCNTL) O
If ~ durlng a data acce~s bus ¢ycle, a RETR~ i~ re~ue~lted 9 OR 8atæ~ 30 ~nd 32 ~ill respecti~ely act~ te lt,he BERR and HALT lYIput~ o~ DP 12. In re~pon~e to the simultaneou~
~sctiYation of both the BERR and H.4LT input~ thereof duning a DP-contrc>lled bu~ cycle, DP 12 ~111 abort th* current bu~
oycle ~od 5~ upon the termln~tlon of the RETR~ ~lgnal, retry the ~yole O
If desired, operation of DP 12 m~ be e~ter~ally col~trolled by Judi~lous u~e of a lH.ALT ~igr~al. In re~ponse to the ~cti~tlon of only the ~lALT input thereof via OR g9te 32 "
DP 12 wlll halt at the end oi` tlhe curr~nt bu3 ~ycle 9 ~nd ~ill resull3e operation only llpon the ter~inatiorl of the HALT ~lgnal.
In respon~e to the activ~tion o~ onl~ the BE!R}'~ lDpUt thereof during a ~rvce~or co~trolled b~ oycle" DP 1? ~irill abort tbe ¢urrent bu~ cyc~e~ int~rnall~ sæve the ~ont~nt~ vf tlh~ ~tatu~ regi~terD ~nter the ~per~visor ~tatet turn off lthe ltra~e ~tate îf on " and generate ~ bu~ error ~ector rlumber O DP
he~ ~tac~ to a ~uperYi~or ~aclc ~rea ~n meDl~ry 20 a bla:~ck o~ ~n~or~atlon ~hloh re~l~ct~ the el~rrent lrlteri,al a:onte~t IDf the proce~sor 5, ~nd ICheD u~e lthe ~ect3r numher t~
branch lto an ~rror haDdllllg port1on of the ~uper~or progra~n.

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IDur~n~ t~e ~t~ck~ n~ oper~tlon, DP 12 ~ t3~k ~rt~ln ~nfor~D~ t~o~ en~ Dl n~tur~ ¢l~d~ d re6~t~r, ~e ~rr~n~ ~n~ pro~ t~
~ontent~ o~ the ln~rl3~tion re81ster ~ahlch IB 1) EilL~
~r~t edord o~ tlhe currentl~ esecl~t3.n~ strllct n~ tlhg 910~
~ddre~ ~hich b a~ beln6 ac~es~ed by the ~borted bu3 ~cl~ d ~h~ r~ct~ o~ ~e abo~ d l~ yc~l@ ~ . s~d~r~e, instruct~on/dat~ and ~n~tlon 60d~ add~tlon to t~e ~bo~e in~r~Dati~n, 1DP 92 1~ ¢~n~tr~cted to sta~k ~uch çDore ~nfor~atlon a~Dol3t the ~tern~ï ~ac~ine ~t~te. If lt,be e~cepltlon handler ~ cGes~ful in re~ol~ing the erlor, th~
l~t lrl~tructio~ thereof ~11 ret~rn ~ontrol o~ DP 12 to tbe aborted Ipr~ra~. During the e~cecutlon o~ tlli~ ln~truct~o~"
the addilt~or~ tacked ~nfor~atioPl ~ retrleved ~nd loaded lslto the appropri~te p~rtlorl~ o~ DP ~2 to re3tore the ~tate ~hl~h e~lsted at lthe ti~e the bu~ errvr occurred"
The pref erred operat~on of DP 12 ~ill be de~cribed ~ith reference to Flgure 2 ~lhich lllu~trate~ the lnterrlal orgar~zatlon of a mlcroprogrammable embodlment o~ D~ 12.
S~nce tlhe lllustr~ted for~ o~ DP 12 i3 Yer~ slm~lar to the ~torol~ ~ MC68000 microprocessor described in delail in the ~e~eral IJ.S. Patents clted heres~ter" the ~om~oon oper~tl~:>n aspects ~111 be descrlbed ratlher lbro~dly. Once a ¢e~eral snderstandlng of the internal archi1;ectl~re of DP 12 ~3 e~tsblished, the di~cussion eaill focu~ on tlhe ~cce~ co~trol aspect of the present ln~2ntionO
Tlle DP ~ 2 ~s ~ pip~lined ~ ~icroprogram~ed data ~r~cessor .
In ~ pi~ellned proce~or ~ ea~b înstructi~ typicall~
fetcbed durlng the ~ecutlon o~ the ~recedi-ag instructi~a ~nd the lDterprelt atlon ~f the ~etched la~trlactlo~ usually begln~
before th2 end ~f thc ~recedgLng ~tructlo~.. In ~
~iGr~programmed data ~ro~e~or8 ~ach i~tru~tion 1~ t~pi~ally get~hed d~rîng the ~ecutlon of the ~recedir~ ln~tru~tlo~ ~nd t~e 1~t~erpretstiorl of the fet'cbed 1n~tru~t10n ~sua11y lbcg1 before the end o~ O~e pr@eedl~lg ~Dstructîo~S In 8 ~, r~ ~ r~
~lcn~programDled data lpro~e~or~ each in9trl35~ti~n i~s e:~e~l3ted eq~ r~ e~on~ ~h~ p~r~o~la B~ 2C~
of the operation deflned by the ~n~tnu~tlon. I~ desîr~d ~ er ~n~trl~ctl~Dr~ a~ be t3 ou~ht o~ a~ ~acr~ln~tr~ctio~s to a~oid confu$10D ~ith the sZi~rolnstruction~ In the DP 12, e~ch ro~ tructlon co~nprl~s a ~nlcroword ~?hlGh ~o~trol~
îcro~nstructlon ~equerlclng and f~netion c~d~ ~encratlon, ~nd a ~orre~ondln8 n~no}~ord ~hl~h control~ the ~etual ro~3tlng of 1n~or~tlon bet~een ~unctio~al ult~ and the a~t~atlon of ~pe~ial fuDetlon unlt~ ~71thin DP 'i2q ~lth thiS in alllnd 9 a typlc~l iD~tructio~ e~ecutlon cycle ~111 be de~r~bed, llt ~n ap~ropl^late t~me duri2lg the e~ecut~n og eaclh ~truction ~ a pre~etclh Eni~roîn~truct~on ~111 be exeo~ d .
The ~icro~ord portion thereo~ upon be1ng loaded fr~m ~icro ROH 3~ 1nto micro ROM output lat~h 36, enab12 function ~ode bufgE ers 3B to output a ~unct10n code (FC) portion of the 10g1ca1 addres~ (LADDR~ ind1cstirl~ an in~truct10n cyc1e. Upon beln~ ~1~u1t~neou~1y lo~ded ~rom ~no ROM ~0 1nto ~laDO ROM
output latch ~2, the corre~ponding n~noword requesks bu3 coeltroller ~1~ to perform an in3truct10n fetch bu~ cyc1e J and in~tructs exeoution unlt 46 to pro~r1de the 10sica1 address of the first ~ord of the ~ext in~truction to addres~ buffer~ ~8..
lJpon obta1n1n~ oontl ol of the PBUS 167 bu3 contro11s~r 11~ wi11 enaD1e addre~s buffer~ ~8 to output the ~ddre ~ porltion of the 10~1ca1 addre~ (L~DDR). Short1~ therea~ter, bu~ contro11er prov~de appropriate dats ~tr3be~ ( ~ome of the l.CNTL
as1gna1~9 to act1~r~te ~eiDory 200 WheD ti e ~nesDory 20 ha~
pro~ided the reque~ted infoa~Dat10n ~ bu~ csntro11er 44 ena'D1cs io~tralction register capt~re (IRC~ 50 to 1nput ltbe f~r~t ~ord o~ t~e ~e~t 1~tr~ct10n from PBllS ~6. At a 1ater po1nt in the e~ecut10n of the ~urrerit in~tructlon9 ~llother ~cro1D~tr1actio~
k~i11 lbe ~a~ecsted t~ ltran~fer tbe ~ir~t dord of the ~est D3tructlon frolD IRC 50 1~to ~nstruct~n regi~ter (I~) 52, ~nd t~ load the ~e~t ~dord rrO~ l~ell~D19 20 into I~C 501~ Depea~ding upo~ the t~e o~ in~tr~t10D i~ 2 " tlhe klord i~ C 50 ~a~

be lDmediate ~t~ 9 t~e a~dre~ o~ ~n o~er~d 8 a: r ~he ~lrat e~ord of' ~ ~ubseq~q~nt In~tructloD~, ~ n ~m~le o~
~n3tra2~tio3- ~et wh~ enerall~ ~laltllble ~or DP 12~ ~nd th~
~cro~n~u~ e~l~@~s ~h~h ~y ~ 'bed ~ le~e~t ~ch an lnsltr I~CtiOII ~et" ~re set ~ortal ~ully ln lJ,S,, ~atent ~oO 4 ,~3259121 entitled ~T~o Le~el Contro~L St~re ~or l~lcroprogr~ed lDat~ ~roce~or~ ued 13 ~pril 1g~2 to Gunter A~ S~DO~n a~ the flr~t ~ord o~ t~e ~e~l; 1n~tru~t1on ~a~ been loaded lnto IR 52 ~ ~ddre~ t dec~der 5~ ~e~lD~I decodi~g certa~n g~ntrDl field~ 1n the 1~jtructl~ to d~ter~îne the~
o~Lcro ~ddre~s o~ the f~r~t ~icro1r3truct~on in t~e l~itial EDicro~e~uence o~ the part~cul~r ir~truct~n 1n ~R 52,, .
Simult~neo~sly, illega1 lnstruct1o~ decoder 56 ~lll be8in e~ a~inin~, lt,lhe for~at o~ the in3truction ~n IR 52 ~, ~f tbe forllna~ deter~ined to be 1noorrect, ~llegal iD~truct~o~
decoder 56 ~ll proYide the xicro addres3 of the f1r~t ~icro1n~ltruct1on o~ an illegal 1n~tru~tloD ~1cro3eque~cer In re~pon~e to t~le rormat errorS ex~eptlo~ log1~ 58 ~ orce ~ultiplexor 60 to ~U~titl3tl! the ~1cro addre~ pro~l1ded by ~llegal instr~3~tion decoder 56 for th~ ~lcro addre33 pro~ide by address 1 de~oder 5~O Thu~ upor~ e~ecutloD o~ tbe la~t Dlcroln~trllction o~ the currently e~ec~ ;lng ln~trl3ctloD, th¢
nlcrow~rd portlon thereof ~ay enable ~ultlple~or 60 to proY~Lde to arl appropriste mlcrv addre~ to ~lcro ~ddres~ latQh 62 "
~hil~ tlle nano~ord portio~ thereof en~ble~ ts~u~tlon regî~ter decoder ~IRD) 6~ to load the ~r~t ~ord of the ne~t î~trlu~tion fr~ IR 52D l1pon the selected ~lcro ~ddre~ beirlg loaded into ~cro ~ddre~s l~1seh 62,, ~cro ROM 3~ ~;ill outp~t a re~pective ~ ro~ord to lDicro ROM o~tput lat~h 36 and ~ano ~RûM
~O ~lll c>utput a correspondlng ~no~ord to r~ano ROtg out,put lat~ 420 Generall~ ortîoD of ea~h 1Initro~ d ~7hlcb ~ load@d lrlto O;iCI~O RO~ output Iateb, 36 ~pec~fies the ~ ao ~ddre~ of ~e g~e ~ r~ t~u~o~ ~;o ~e e~ 9 ~h~e aa~ e1~

~3~
~ 'I ~ nD
~ort~or, de~er~lre~ o~ t~e altern~tl~e ~cro ~ddre~a ~11 &>e æe lected b~ oultl~le~or 60 ~r înput to ~ ro ~ddre~
l~cb 620 1~ r~ r~ n~ n os~g sD~cro3c~lJen~e ~u~t l~e e~e~ulted to ~c~pli~lh the a~pe~ ed oper~tlon~ The~e t~3k~" ~IIDC~l 1118 ll~d~re~t ~ddres~ re~o~tion9 are ~e~e~a1~ ~pe~fled ll~in~ ~dd1tiora1 c~ntro1 f1e1d~ v~thin the 1n~truct~0 Tlhe 8~ ro ~ddre~gs of t~e f~r8~
îcro1n~tru~t~on~ ~or ltlhe~c ~dd1t10na:1 ~1cro~eque~3ces ~re de-le1s~ed by ~ddre~ 2~3 decoder 66 us1ng ~ontro1 ~ or~ on ~n IR 52,. I~ the ~i~pler for~n of 81UC~ trl3ction~" the fir~t ~cro3e~uence ~lïl ty~lcall~ per~orm ~ome preparatory ta nd ~en en~ble ~Dultlple~or 60 to ~elect the ~icro ~ddress o~ th~
~icro~eque~ce b~hlch ~111 per~or~ the actual operatlon as de~eloped by t~e sddress 3 portion of address 2/3 decoder 660 ~n ~ore co~ple~ for~s o~ ~uch ln~tructiona ~ the ~lr~t ~icr~eq~er3ce will perform the f~rat ~repsratory ta~k a~d ther Mill enable ~ultiplexor 60 to ~elect the ~icro ad~re~ of the next preparat~ry m~crosequence a~8 de~leloped by the ~ddre3~ 2 portion of ~ddre~ 2/3 decoder 66. Upon performing thl~
~ddlt~onal preparat~ry ta~k0 the 3econd ~lcro~equence the enalDles multiple~or 60 to ~elect the ~icro addre3~ o~ l~he ~icrosequence ~hlcb ~111 perfor~ the ~3ctual operatlon I~S
de~eloped by the addre~ 3 ~ortion o~ address 2/3 decoder 66.
In ~y e~ent9 the last ~lcroin~truction ln the la~t ~crose~u2nce of e~ch lrstruct~o~ ~111 en~ble ~ultlple~or 60 to ~e~ect tlle zDicro addre3~ of the fir~t æD~croin~trl~ctio~ o~
the De~lt, in~tructlon Za~ de~eloped b~ ~ddre~ 1 de~âer 5119 In th:Ls ~anner9 e~ecutlon of e~clh i~truction ~11 proGe~
th~ o~b ~n approprlate ~equence o~ ~Dlcrolll~tructlo~s~ nore thoro~glh e~plarJation of a ~ultable ~inicro addre~s ~e~ueDce ~e~ection ~echanls~ e~ .50 Patent ~o c, ~ ~3~2 9 078 e~tltled ~In~truc~ ion Regl3ter Seql~e~e Decoder ~or roprograllnmed D~ta Proce~sor'~ ue~ 27 3ul~ ~932 to Tr~den~ick et al.

~23 ~12-~ r~ c~ntr~lt to the sDlcro~srd~" tbe r~no~onds 3dblcb ~re lo~ded lnto r~Dno ~OM ol~tput l~te~ ~2 ~directly ~ rol the r~uti~3B o~ operar~d~ ~nto ~n~, lf ncce~ ry~, bet~een tbe ~e~eral ~e~ister~ t,he e~ecut,~o~ urlt ~6 bg e~er~l~lng ~:onltrol o~er re~ager ~ontrol thl~h) 68 ~nd regl~ter co~trvl (lo~ ~nd d~3t~) 70. In cert~n o~r~u~st~noe~ t~e Dano~ord enable~ fleld ~ran~l~t~n u~lt 72 to e~tr~ct ~rticul~r ~olt ~ield~ fJ'QII~I ~he ~nstrl30t~0n ~n I~D 611 for ~LDpUt to the ~ cutlo~ unlt ~6. The ~ano~ord~ al~o ~odlre~tl~ ~o~trol effectlve addre~ lculatlofl~ ~nB ~ctu~l operand c~lcul~tlon~
~ithln the *~ecutlon ~nit 46 by ea~rci~ing conltrol over dU ' ~ontrol 7~ ~nd llLII control 76 . In approprlate ~lrcls~stances the nanoword~ enable ~LU cont-ol 76 to ~tore lDto :st~tu~
reglster (SR) 78 the ¢ond~tior~ codes ~hlch roesullt ~rom ea~l~
operand calcul~tlon by e~ecutlon unlt 46. ll more detailed e%planatlon of a ~ultable for~ of Al.U ~ontrol 76 ~8 gi~en i~
U.S. Petent No. 41312,034 entitled 'iALU and Cond~tion Code Control llnit for ~ata Procesaor" l~sued 19 Januar~ 1982 to Gunter 9 et ~ ther details relating to the construction and operation of DP 12 may be found in U.S. Patent Number 4,493,035 entitled "Data Processor Version Validatj.on" issued January 8, 1985.
Since DP 12 ~3 a ~lcroprogrammed ~achlne,, the ~plement3tion of addlti~nal instructlons ~ prlmarlly ~altter of pro~ldlng appropr~ate micro~eauence3 for the r,e~
~ tructio;-~, pro~lded, o~ csl~r~e, that ~ll o~ t~e re~ource~
and control path3 are ~vallable to ~upport the funct~onall~cy of the D~ tructions. Such i~ th~ c~e of tbe ~dule ~all ~CALI.M~ ~nd ~D~dule return (RTH~ ~n~ltructlo~s ln acoordanee ~ith the ~re~enc ~nYentl~n" ~ @ the onl~ l~ard~as~e re~.u~re~ent llDpo~ed upon Dl~ 12 b~r th~ trllclt io~ l~ the e~lstlng ablllt~ to read frolD and ~rite to ~peclîic ~ddres~es ~lth~Ln tl~e o~rerall addre~ ~pa~e alread9 ~ llable ~o DP 120 Oal the othes ~an~; ~lt~lD the co~tr~lnlt~ ~po3ed by ltl~e ~

C~LLM~RT~I lnterfa~e, I;he læ~pl~ nt~ltlon ~I t~e Ell~ 85~
s~ontrollær ~unction ~ totall~ ~t the dl~cret~on o~ the ~Iy3~em des~ner . Thu~ a ~r the plarpo~e~ o~ de~ribln~ the operatlor of DP 12 in the execls~ion o~ the C~LLM ~nd RT~ ln~tru~t~on~, ~h~ e~ ~o~ rolP~r 9 l~JhlQlh ~Ou~ b~ ~on~ n~ly ~ r~ed ~nto the ~M11 1~, for e~a~ple9 ~ill be as~u~ed to e~sist ~ a ~bl~:k ~o~ 13P ~12 p~ Y~ o~ r~l re~l~ter~ IElCC~e3~ E! 8t rg~p~tl~le predeteroin~d addre~e~
t~e ~ ti~B ~ ¢~-In t~e preferred ~orm, the C~LLM ln~trll~tion ~on~ts ofan ~ffe~ti~ e ~ddress g?hi~b ~pe~if`le~ the ~ddre~ ~ltbln the ~e~ory 20 ~ ich a des~riptor ~or t~e called modl2le ~ag be found 9 ~nd an argl~ment count ~hich indl~lte~ the number of argu~aents " lf any, 1;1he calling ~Dodule i5 pas~lnl3 to ~he called mod~le~ In preparation ~or the CALLM lnstrll~tlon,~ the ~odule ~e~criptor ~111 ha~e be¢n initlalized at llnk time by lthe ~upervl~or prt gram to contaiN the entry addres~ o~ the called Di~odul~ snd the ~ddre~ of the data area ~3socl~ted ~lth that ~oduleO The ~odule de~riptor may al~o contaln the address of a ~t~k upon klhlch the module exp~ct~ to find the ~rguments.
In ~ddilt 10D p t~e Ynodule de~rlptor b7ill oontalll an a~¢es~
req~e~t o~ a ~pecl 1'1~ fcrmat ~ppropri~te for the parli~ular ls~wel of access control de5ired by the de~lgner o~ the ~ste~,. For exa~p~e" iE~ the preferred e~bobi~ent7 the ~cce3 request ~on~ of an ac~ess t~pe code ~hlch lndlcate~
whetlher the ac~e~ le~el ~u~t be changedl~ ~nd, lf 2309 ~hat ne~
acce~s level the called ~odule s~equire~O
IJpon recel~ing the CALLM lrlstructio~ ~or ~ecutloD" DP 12 b~lll f irst eYaluate the e~fecti~e addre~s arld then retrlevc fro~ talat addres~ the acoe~ r eque~t, the qnod~le ~ddre~s a3~d the ~odule data area address. DP 112 the3l te~3t the ~cces~
req~est to deter~ine the ty~e o~ acce~ ~hlch is to be ~nade"
that iS9 ~hether ~n acce~ le~el c~ang@ 1~ requlred or the ¢urrent acce~ le~el i~ ~dequ~te for the called ~odule. In ~dditioDa the preferl~d for~ of ~h~ ~cce~s req~e. t ~l~o ~ndlc~gæ~ &~het~er the c~lled ~D~dule ~ jpeGtls to ~ ld t1he ~r~u~ent~ oP~ tl~e call~n~ ~odul@~s ~ta~llc or o~ the ~alled p9~ h~ ~cQe~ yp~ s~
le~el n2ed ~ot be ~haFI~ed ~ DP 12 wlll b~ild a ~Dod~Le ~ck ~r~ae at ttle top of the current a~t$~:kO If the ~alled ~Dodul~
~e~p~ ind ~ r~eD~ o~l ~h~ lng ~d~ t~
DP 912 ~ ta~k the callin~ 3Dodule~ ~tack ~olnter o~ the ~odu~e ~t2s~k fra~e 80 tlhat the ~lled ~dule ~111 kno~ &Ihere to f lrld the ar~uDIents ~ If the ~lled m~dule e~pect~ to ~lnd the ar~u~ent~ on ît~ own ~tackp DP 11~ doe3 Dot st~ck the C~ D~ ~odulei~ stack ~olnlter, but ~lmply ad~anQe~ the ~odule ~tack fra~e polnter to c~mpen~te for the short ut~, DP ~2 then ~rite3 tlhe curs~enlt ~r31l2e of the oal:lin~ module ' ~ pro~r~m counter on the ~odule ~tack ~rame ~ followed by the ~ddres~ o~
the ~odule de~criptor"
In the pre~erred form~ the fls ~t &~ord of the cslled ~odule 3p~clî ies a partlcular one Or the ~veral regis~er~ ~ltbin D~
12 which that ~Dodule e~pect~ to contaln the addre~ Qf the data area Or that ~odule~ l~t thi~ pol~t :ln the e~ecution of the C~LLlP~ ln.~trucltion9 DP 12 wlll retrieYe tbi~ reai~t~r ~peclfier 7 ~nd lthen ~tore the current content~ of tlhe speci~ted reelster on the ~odule stack grame. DP 12 complelte~
t~le lDodule ~taclk ~raD~e lby ~torlng the ~rgumer31t count ~pe~lfîed b~ the CQILL~l in~tru~tlon and the acces~ re~ue~t r¢trge~ed froliD
the ~odule descriptor 0 DP 12 the~3 begi n~ 2Yecution or the mvdule 8 ~ tlhe i~`ir~ tru~tion follo~,?ing the regi:ster ~p~ci~r n ~ f, on the other hand ~ the ~¢ces~ type lndlcate~ that the acce~ level ~u~t be ~harlged, DP 12 ~ill flr~t determiDe lf the ~alllng module 1~ pa~ing arg~Dents to tlhe ealled ~odul2 and9 ~f ~o" DP 12 b?111 ~erl~y that all Or tl~e argumeDt~ are it~i~ the l~itl~ate ~ddre~ ~pac~ of the calling ~odule. If an ~ccess3 Yl~la~slon gl~ detected, DP 12 ~ill force the lt,erlDlnation of ltbe ~alll~g Inodule 1b~ ~eetol in~ to ~ e~eept1o~

~3 ~lS~
BlerO lf n~ ~cce$~ t~on ~s ~lete~ted, DP 12 ~dill reZ~d ~h~t ~ t bel ~eve~ to be ~he ~cce~ level of the call ~ng ~o~ule ~r~m ~ ~rur~ent ~cce~s level ~eg~te~ known to the DP 12 only ir~;t predet~Eimil edl a~dre~s w~tlhin tlhe ~ddre~s ~pa~e~, DP
lZ w~ll then w~ite th~ ~dress o t~e c~lled module ~o ~
Q'~no~lule adldl:e~ regi~te~a' known to the DP 12 only a~ a ~e~ond predeter~ined a~dres~ in the ~va~l~ble ~d~re~ cpaceO ~nd ~be ~aew~ ac~e~s level to a ~increa~e ~ICCe6~; leYel ~egi~ter~ lcnown to tlhe iDP 12 only ~ ~ third predeterm~ned ~ddre~ with~n the a~dres~; ~;pace. DP 12 t~len readl~ w~t ~t b~lieve~ to be tbe decision of the acce~ contEoller to the ~c:ces~ req~e~g from a~ "access ~tat~ re9i~'cer~ knowrl to the DP 12 only ~s fourt~ predetern~ined ~ddre5s within the ~ddres~ ~paee~, lf t~e deci~iorl ~s negative ~at lea~t what DP 1~ perceaves to be neg~tive), DP 12 will ~orce the termination of the calling ~nodule by vectoriD9 to the exs:eption handler. On t~e other ~and, if th~e decision i~ perceived by DP l2 to be aff:irmaltive~ DP 12 w~ll insert the "old~ access level into the acce~s Ee~Ue~;t being maintained within a temporary reyi~ter within DP 12 in place of the "new" acce~s level origi~ally c3ntained thereinO
lf the call~d module exp~cts to ~ind the argument~ on the calling ~lodule~ ~tack or ~t lea~t a pointer to ~he ~rgument~
wilthiD t:he modul~ ~tack frame, DP 12 procedes to comple~e the Dnodule ~tack frame just a~ in the ca6e de~cribed ~bove when there wa~; no acces~ level change. 0~ the other hand, if the calle~ ~nodule expects to f ind the arguments on its o~ ~taclc, I)P 12 will retrieve the called module'6 st~ck poil)ter fro~Q the ~o~uls~ ~e~criptor, and trall~fer all of the arguments from the calli~g module' ~ ~taclc to the ~alled ~odule' ~tack~, DP 12 t~E?n builds tlae module ~tack grame as descr~bed ~bove bu~ on the called module's sta~k ~atber than Q~ tlle calli~g J~odule'ai sta6~ either case, after the Imo~ule ~ta~k frame i~ -s:omple~ec DP 12 then beg~nR execution of t~e m~dule ~ the f ir~;t iD~;tru~tio~ ollowing the re9isl:er ~peci~aer,.

IJpon 2ec~ n~ the RTM ~n~truction ~or execution ae the end of t~ae called ~odulæ, DP 12 w~ll retr~eve tl~e ~c~ess ~request, tlhe ar~ument count, the ~rogr~ ~ounter for t~e c~ ~odule ~nd the v~ue which w~ n the regi~ter used by the c~llæd ~odule ~ the po~nter to its d~t~ the ~cce~ type ~n ~e ~e~ reQue~t indicates ~hat ~lo acce~
ch~nge was madeO DP 12 ~djusts the current ~ta~k pOiDter to di~c~ræ tlhe module ~tack frame alnd any æ~sosi~ted a~r~ument~, re~tore~ the ori al value of the re9~ster u~e~ by the c~lled module, al)d ttlen re~tore~ the pr~gram counter to resume esceeutio~ of the calli~g module., If, however, the acce~s type i~dicates that an ~¢e~ level cl ange was ~ade~ DP 12 ~etrieves the ~old~ stack poin~er from the ~alled module' 5 ~tack, before writing the ~oldU acce~ le-~el to a ~decrease acce~ level ~cegi~ter~ knowD to DP 12 only ~s ~ f lfth pl~edetennined addre~ within the address ~pace. DP î2 then reads the Uaccess ~tatus r~gi~ter~ a~ain to ~ee what the ~lecision of the ~cces~ controller i~ to the acce~s level decrease requestr lf the decisiion is negative, DP 12 will ~orce the termination of the calling module by Yectoriog ~o tbe exception handler. I the de~ion i~ ~ffirmative~ DP 12 will adju~t the ~old~ ~tack pointer to di~card the ~odule staclc ~rame and the as~ociated arguments to derive the proper curren~ stack pointer. DP 12 will then procede ~s de~cribed above to re~tore the ori~inal value of the regi~ter ~sed by ~he callea module, and tllen the program counter to re~ume execution of the calling anodule.
A~ explair~led above, DP 12, in the ~our~e of proce~ing the C~L~i al~ RTM in~truction~, ~,7ait~ ~Eor the deci~ i~n of the acces~ controller before proceeding with the execution oiE t~he called ~odule. However, i~ de~ired, I)P 12 could simply proceea with tbe reilaue~te~ ~cce~ ~fter pa~in~ tbe a~ce~s request to the acce~ ~ontroller. If the acces~ ~ontroller ~ecide~i to ~eny acce~, the acce~ controlle~ l:an ~ ply fault the ~cee~is eycle,, thereby ~orc~g DP 12 into the ex~:ept~

-17~
~n~loer ~nyw~yO ~hu6~ the pre6ent ~nYent~oal, in ~ gener~l ~ense, ~glstes to a ~ech~n~m for a ~t~ pr3ce560E ~uch ~ DP
12 ~o ~d~e aln lndependent ~ce~ controller that ~n ~CCeB6 reqlJe~t ~ goir3g to be la~de unle~ t1he ~ccefi~ ~o~troller prevent~ it. How the ~cce~ ~ont~oller dec~e8 whether or nst tc~ allow the ac~e8 ~ tot~lly out~de the ~cope of the dat pr~ce E;60rO
ll~ing t~e ~ui~e ~how~ ~n Appendi2~ I ~ the detailed ~icro~equence ~hown in Appendix II for a preferred imple~en~atiOIl of the CA~t.M ~nd RT~ lnstruction~ ~n a modaf ied ~orm o~E DP 12 ~a~ be under~to~d. For a 9ener~1 under~tanding o ~ul:h ~i~ro~e~uence6~ as well the ~icro~e~uence~ ~or all of the inst~uGtio~s ln DP 12, refererlce ~ay be ~ade to US ~atent ~umber ~ "32~ ,121.

:1 ~ 2~
APPENDIX I
MICROINSTRUCTIO~a LISTING

CO-ORDIN~TE OF BOX PSICRO SEQVENCER
L~-BE:L OE BOX INFOP~MATION
~-- MICP~O ADDRl~SS
I ~- 0~3:GIN
1 r ~ ~ V Y Y
¦ AAl ~ EXa~ 0 ¦ EXAMl ( 15I~E ¦PADB¦ ~S¦ RYSI R/b~ TIME TYPE
'lCOMMENTS " AY
TRA~ SFI~P~S Al.13 Tl DESTINATI0N CC
T3 D~STI~3ATIO~ S31FTO
SHFTC
FTU
PC
P~PE
. DATE
. ._____._________ ______ __._______~_____~
ORI~;IN~ if ~hared, co-ordinate of origin if o~igin, ~ of boxes ~haring with this box D~TA ACCE~S INFORMATION:
~/W TIME
- no access X ~ no timing a~ociated wr i te Tl - wr i te to aob in Tl <> - read T3 ~ write to aob in T3 SPC - special s~gnal T0 - aob writen before Tl EXl:~ ~ latch exception TYPE
o y ~ <~> on R/W
,. - normal acce~s UN~C - prog~am~data acces CNORM - cssndi~oD21 n~rmal CUL~ conditional prog,~data LS - slter~ate addres~ ~pa~:e CPal - s:pu acce~ - dif~erent bu~ error ~Prl2 - cpu acce~ - normal bus er~or P~ - rea~ modify-write acce~
SPC ~D R~W
~STl - re~gore ~tage 1 }~S 9r2 ~ re~tore ~tage 2 i~ALT - hal~ pin active RSET - re~eg pin ~cti~e C - 6y~chro~ize mac~ine ~XL O~
8 error PRIV pr~vilege ~ol, - aæ~R .a~dre8$ ~r~or ~E3ac ~ e : . , . . - .
.. .. . - , .- . , ~ -I.lNA 1 ~s~e ~ TRAP - tr~p LINF - l~ne ~ COP - proto~ol v~ol .
ILL - ~ llegal FOR oraat erYor DVlBZ ~ vide by æero IN~ nte~rupt l~t ~tack B5~CK - bad checlc INT2 - lnterrupt 2nd 6tack TRPtr - ~ap on overflos~ I~OEX ; ~o e~ceptit~n MICRO ~E~UENCER INFO~ATION:
D~ - direct branch - next m~croaddre~s in microword BC - conditio~aa~ b~anc~
Al -- u~e the Al PLA ~ample interrupt~ and tr3ce AîA - u~e ~he Al PLA ~ample interrupt~, do not sample trace AlB - u~e the Al PLP~ do not 8ample i~terrupt~ or trace A2 ~ u~e t~e A2 ~
A7 - f unction~l collditiona~ br~nch ~DB or A2 PL~3 - u~e the A~ l~tc~ ~ next ~icro addre~s A5 -- use the A5 PLA
P,6 - use ~he A6 PL~
SIZE:
~ize ! lbyte nano spec~fied constant value size ~ word nano specifîed constant value size ~ long nano specified constant value si ~:e ~ irc~z irc llll ~0/l e> word/long ~ize ~ ir~z ird decode of the instruction ~ize ~by~e/word/long)~, Need to have fîle ~pecifying resîdual control ~ixe ~ ze ~bifter control ~enerates ~ ~ize ~alueO The latch in which thi6 value is held has the iEollowlng encodiDg 000 ~ byte OOl ~ wo.~d 010 - 3-b~lyte lon 100 ~ 5~ yte h*~ mu~t act a~
' ~r~lg sized RXS - RX suBsTI~ TIoNs:
RX is a ~eneral re~i~ter poînter.. It i~ u~ed to poant at either special purp3~e regi~ter~ or u~er registers.
~aX generally is u~ed to translate a regi~ter pointer ~ield within an in~tru~ltion into the c~ntrol required to ~elect the the appropriate Eegi~tOE!rO
r:~ rz2d~r~d conditionally ~ubs~itlate tz2d u~e ræ2d and force r~ 13~ ~
.1 Ql~ 0~ x~ atxx di~r.l 0l00 ll~ 001 a~

Iq ~x ~ rx i~d~ 9] Duxed nnto rxl2~0]
ra~ l31 ~ 0 tdata reg . ) ~unles re~idual po~nt~) rx~ then ~x l31 - 1 kesidu~l def ined in opmap) rx ~ rz2 ir~2115:121 r~uxed onto rsl3:0]
rx 131 i6 forced to 0 by residual coTItrsl div.l 0100 110 IID01 9SXX ~xx bi~ f ield reg 1110 1~ 111 xxx ~xx rac ~ rp rx 13:~1 c ar l3:al T~ e ~alue in the as: latch mu~lt be inverted lt>efore go~g onto the rx lbus for ~ove~ rl~-~ry) . 01~ 100 01x 10~ xxx rx ~ rz irc:ll5.121 muxed onto r~l3:~1 ~cannot u~e res idual contr~l ) rx ~ ro2 rxI2:01 c irc2l8:61 rx 131 ~ 0 ~data reg. ) U~ed in Bit Field, always data reg rx ~ car point~ @ cache address register rx ~ vbr points ~ vector ba~e regi~ter rx = vatl point~ Q vatl rx ~ dt points @ dt rx ~ crp rxl3:01 ~ arl3:01 The value in ar point~ at a ~ontrol register ~ i ~e. not an element of the u~er visible regi~;ter arr~y) rx ~ usp rx l3: 01 ~ F
~Eors:e eiEfect o$ psw~ to be Dega~ed (0) r~c ~ ~P rXl2:o] ~ F, i~ p~w~ then address u~p i~ p~ws~l & pswm~0 then isp i f pswscl & p~wm 1 then ~sp P~S RY sussTI~llT~oNs:
ry ~ ry irdl2:0] muxed o~to ryl2:~l ryl3] G l (addr reg.~ u~le~ residDal point~
ryd then ryl31 ~ 0. ~residual defi~ed in opmap) ry ~ ry/dbin Thi~ i~ a ~:oY~d~t~3nal ~ub~titlltio~
ry~o~ ~or the nQr~al ry selectior~ ~w~ h - . . ~ . , - . - - . . .. :

~T~clude~ t~e ~idual ~ub~titution~
l~e dt~ w~tb db~s~ or dob. ~he ~uboet~ution ls ~na~e t~sed or~
re~idu~l control de~ined ~n opmap ~about 2 ird line~) w)~ich ~elect$ t~e dbin/aob ~nd inhib~tg ~11 a~tl~n to ry ~or the re~idu~lly def ~ned ry~ .
D~pending upon 1:he direction to/ro~
the r~ db~n or dob i~ selected.
If tlhe transfer i~ &o the rails then dbir~ ub~tituted while if the tran~fer ~ frolD the rail~ d~b ~ub~tiltute~ ..
Spe~ial case: IRD ~ 01~ 0xx Oss 090 8XX
~clr jneg ,,negx,laot) where if driven onto the a-bu~ ~ill al~o drive oa~
the d-bu~.
ry ~ rw2 irc2~3sO] muxed onto ryl3:03 u~e rw2 r~ovem ea, rl ~1~0 110 01J~ 7CX8 X:I~X
r. 1 0100 ~ 001 ~XX S~X
bf i~l~ 1110 xxx xxx xxx x~
cc~p 1111 x~c~ xxx ~ t x~ix aO rJot allow register to be writ~en 39iv.w 1090 xxx xll :KXX x~
force ry 13]
div . l. 0100 110 OO~ ~xx azx~
bf ield llla l~lx ~11 xxx x~x ry = rw2~'d~ ~onditionally sub~titute rw2 or dt uæe rw2 ~nd force ryl3]-~
r~ul . 1 1110~ 110 ~00 xxx ~xx and irC2 l1 diV . 1 0100 110 001 XXX X~
~nd irC2 l101 - 1 rY - Vdt1 POint~ @ VirtUa1 data temPOrarY
rY ~ Va~2 POint8 @ VirtUa1 addre8S temPOr~rY 2 rY ~ dtY POintS @ dt AU -- AR1THMETIC UNIT OPER~TIONS a ~SDEC ~ddJ~Ub 3~dd/Sub baSed On reSidUa1 ~Ont~O1 SUb i:E ird ~ ~XX:I~ X~ XX% 1~0 ~XX
1- ASXS add~ b add/~Ub ~aSed o~ re~idUa1 ~U~e ~1U
a~d~ Ub). DD DVt extend db entry ~d ~ a ~ xx ~ xx~ adld ... . - ., . -.. .. . . . . .
~t or ~lOl ~xx ~xx xxx ~x addq 2- ~UB ~ub subtract A~ from DB
- DIV add/~ub do add ~f autl3l] ~ l, ~ub if ~utl3l] 8 0; take ~b ~p~rt rem) shif~ by l ~hiftlng in ~lutl3l] then do the add/~ub.

- S~BZX ~ub zero e~tend DB according to ~ize then 8ub AB
- ~DDX8 add ~ign extend DB 8 -~ 32 bit~ then add ~o ~B
9 ADDX6 add 8i~n extend DB 16 -> 32 bit~ then , add to AB
10- ~DD add add AB to DB
ll- MULT add ~hift DB by 2 then add con~tant ~ign~zero extend based on residual and previou~ aluop mul~ ~ alway~ ~xtd mulu ~ sxtd when sub in previous aluop 2- ADDXS add ~ign extend DB based on ~ize then add to A~

3- ADDSE ~dd ~ign extend DB ~ased on ~ize tben ~hift the extended re~ult by 0,l,2,3 bits depending up~n ircll0:9J.
Finally ~dd this to AB
~- ADDZX add zero extend DB ~c~or~ing to 6ize then add to ~
5- ADDSZ add zero extend DB ~ccordin~ to ~ize, ~hift by 2, then add CONSTA~TS
0~1 1 elected by:
~div * ~llzero) ~ (~ult ~ alu carry ~ ~) l~2g3~4 ~elected by ~ize byte ~ P
word ~ 2 3-~y ~ 3 lo~ Y 4 =2~

(Rx~S~ or Ry~SP) a~nd (~RyYRy or Rx~Rx) ~nd ~Rx or 2y 1~
~ource and de~tlna'cion) ænd (au con~tant ~ 1,2~,3,4) ~nd e ~ byte) then ~:on~tant ~ 2 r~ther th~n one.
A~U - ARlTHMETIIC AND ~.OGIC UNIT OPERATIONS:
X, lll i 8 and ~:ol2 ~ Ul ~ ~ i Y ~IIIUl t " sr col3 G alu2 ,~ub row col î s: ol 2 eo~ 3 ADI)RO~ and ~dld 2 ADDXIROW ~nd add~ add 3 SUBROW and ~ub

4 SUBXP~OW and ~ubx addl S DIVP~OW and div ~ub 6 MIJI,TRS)W ~nd mult ~;ub 7 ANDROW and and 8 EORROW and eor 9 O~OW and or add NOTROW and nct 11 CHGROW and chg 12 CLR~OW and cl r 13 SETP~OW and 6~t cin add db ~ ab addx ~b ~ ab x addl db ~ ab and ab ^ db c:~g ab xor k~
clr ab ^ k~ -eor ab xor dl~ -not ~ab v db or ab v db ~et ab v k~
sub ~b + ab ~;ubx db ~ ~b ~
D~ult ~db 6hifted by 2) add/l;ub ~ab l;hifted by 0,1,2 giiE ~ then add/~;ub ID) ) control for add/~ub and $hift amount come~ from reglb. D~n~t ~ssert atrue iEor mult cin - ~
div build part., g,uot ;~nd ~d~van~e part. remainO 1 ab (pr .1: p~) ~h i f ted by 1, ~dd0, value ~hiftea i~ U carry (quot bit) ~u~t a~ ert atrue :EOE diiv ~3 7 ~L~3 The ~ond~tion code~ ~re up~ted during l~te T3 ba~ed upon t~e d~t~ in ~lut ~nd~or reg~. She~e ~ceg~ter6 ~:an be wr~tte~ to dur~ng T3. In the e~e o~ rega, tl ere are t~es s~hen the r~lue to be tested i~ the re~ult of ~n in~ertion from regb.
CC - CO~DI TION CODl~ IJPDATE CONTROL:
~w ~ol 1 s41 2 col 3 ___ _~___ _~___ _____ add r~nzvc ddddd ddddd 2 addx enzvc ddlcdc ~bcdl) edzdc ~bcd2) 3 ~ulb cnzvc lcnzv~ ~mp) ddddd 4 ~ub~ C-IZVC ddlcdc 5b~dl) c:dzdc (bcd2 div knzvO (~iv) d~ddd ddddd 6 mul l lcnzv0 ddddd ddddd 7 rotat 3cnzlac ddddd ddddd 8 rox ~nzOc knz00 lckkvk g bit,bitfld lckzkk tbit) lcnz00 ~bfldl) kkzkk (b~ld2) log knz00 ddddd ddddd ~tandard rl c a~ut msb (by size~
z ~ ;~lut~0 ~by ~ize) non~stan~ard Eldd c ~ cout v s= vout addx.1 c ~ cout x ~ p~wz ^ locz v ~ vout bcdl c ~ ~out bcd2 c ~ cout v pæwc z ~ pswz ~ lo~z ~fldl n ~ sh~iftend z ~ all xe~o bfld2 z ~ p~w~ ^ allzero bit z - allzero div V G au carry out ~ull n ~ (shitend ^ irc2 llO] 3 v lalut 13ll ~ -irc2 ll~] ) z ~ lu'c~0 ^ ~hift ~llzero ~ irc2 1101 ) v ~ a~lut~0 ~ c2 1lOl ) v ~ ~rc2llOl ~ ~ir~21lll ^ I~allzero ^
~alutl3ll) v l~allone ^ ~lutl3l]~ v ~ ~~rc2 ~ ^ ~all2ero) ) ro~a~ c ~c ~hift~Dd ~ (~c~ ;C6~0 end) ro~c.l c ~ iftend ~ (~c~ p~w~ ~cC~0 end~
~ a~ o thi~ iD t~o ~teps as knz0c w~ere 1 c~ p~w~ and s:nz0~ where c=~ifltend (IIO~
~ ~ith ~are ro~ ~ith 6hift~
ro~..3 v ~ ~;hif'c overlo~ ~ l~~allze~o ~ ~c>~z) v llzero v allo~e~ c~z)) .- . . ~ , ; . . . .
2y 8 :~3 ~ can ~mplify thiB ~ we don'~ ~haxe I row~ bu~ ~t ~11 co~t ~no~her bo~
sub.1 c~ csut v ~ vout ;;ub o 2 ~ ~c ~c~u~
V ~ Y t~ t E;ubac . l c ~ out z ~ psw2 ^ l~:z ~r ~ v~s~
~;ub~ . 2 c 8 ~cout ~;ub~c.3 c ~ -coult v p~wc p~z locs~
~he ~eaning and source of signal~ whic~h ~re u~ed to ~et the co~ad i t i on code~ i ~ 1 i 5 ted bel ow ~
allzero ~ ~very bit i~ rega faeld ~ 0 where the field i~ defined as starting at the bit pointed ~o by ~tart and ending (int:luding) at the bit pointed tc~ by endD
lsee 8hift control) allone G every bit in rega iEiell9 ~ 1 where the f ield i~ def ined as startin~ at the bit pointed to by ~tart and e~ding ~including) - a~c the bit pointed to by end~
~ee fihi~t control) shi~tend ~ the bit in re~a pointed to by eTld = 1.
(~;ee shift control) loc2 e ~ lut for the applicable ~ize ~ O.

SHFTO -- SHIFTER OPERATIONS:
ror value ial rega is rotated right by value io s~ift count reg;slter into regb.
t;xtd value in rega def i~ed by 6tart and end regi~ters i~ ~ign e~t2nded to fill the undefined bit6 and that value i6 rotated right ~y the v~lue il~ the shit count regi~ter. The re~ult i~ in regb~
xxtd value in ~ega def ined by s~arl: and end registers PS~ extended to f ill tlhe undef ~ned bit~ and thst val~e i~ rotated right by the value in the ~shaft ,I:ount re~E;ter. ~he re~ult ;.5 in regb~, zxtd value in rega defi~ed by ~t~rt and en~ register~
i2; zero e~ter3ded to fill the undef~ned bits and that value i~ gotzlted ~iglbt by tbe ~ e iD the ;E;hiftc ~ount ~egi~ter. The ~esul5t ia; i~ regb.

9 ~L~3~
~ns t~e ~ralue ~n regb i~ ~ot~ted lef t by the v~lue in 'c counit regi6ter ~nd then ~n~er~ed in'co t~e :~eld def ined by the ~t~rt andl ænd register ~n reg~ t~ ~n rega that ~re not ~ef ined by ~tar~
and ænd ~re no'c r~odified,.
~off~ provides the byte offs2t ~n regb. If irc2~1l]~l ~hen the offæet i~ contained in E~O and ~ such rega E;hould be ~gn extended rom rega to regb using the val~ae~ establi~he~ in s~r1:, elld, ~nd ssbi~t co~snt of 3,,31,3 reæpectively. If irc2 lllJ~
t~en the of~et i~ ~ontained ~ t~e immediate 9Eiel~ and ~hould be loaded ~rom ~rc2 110:61 or probably more convenienl:ly o$r 14 :0] . Thi~ value ~owever ~130uld ~e ~hifted by 3 bit~ ~uch ~hat o~;rl4:3] ~re lnaded onto regbll:0] with zer~
zero exten~ion of the remaiI~ing bits.
c>ffs proYides the of~set in regb. If irc2111]Gl lthen the of~et is contained in RO and as such DB>RE(;B
~hould be allowed to take place. If irc2 111]
tllen the offset i~; contalned in the immedi~te ield a~d o~rl4:0] ~ould be loaded onto regbl[4 wi t~ ~ero exten~ion of t~le remaining bit~.
SHFTC -- SHI~TER CONTROL:
{ ~;bml} {sbm~}
BI~ st ~ t ~ wr - 8 bit en ~ -1 (31) en - wr - 1 mvp sc ~ wr ~16,32)sc ~ wr - 8 ~wap wr ~ BCll2:71 ~16"32) wr ~ wr - 8 callnn Ofir ~ X osr ~ x ~nt G X cnt D X
g ~;bm3 } { ~bm4 3 ~it ~ DB 15:~1 m~d ~z st ~ 0 æn ~ DB 15:01 mod 6Z en - -1 t31 sc ~ 0 ~c ~ wr w~ ~ DB ¦ 5: 01 w~ - w~
osr ~ ~ osr ~ x ,c nt c x cnt - x I sbmS } ~ bm6 ~
s~ ~ x ~t ~ 16 en ~ ~ en - 31 ~ = x ~c 16 wr ~ DB ~7:21 ~r ~ wr - 1 6:1S~ ~ ~ o~
s:nt 11: 0J ~ DB t 1: ~] cr~t ; t ~

1~
e aE ~L~3~i~

Z:nt ~ ~
l~Ull~ {~uu12}
MUI, 8t ~ wr 6t ~ wr - 2 ~ulw en ~ -1 mod ~z (15,,31) en ~ wr mul 1 ~;c ~ ~r ~c ~ wr 2 Wr Z EIC[l2:7] ~ D3~ ~r ~ wr - 2 o~r ~ ~ o~r ~ x cnt ~ ~ cnt ~ x ~u13~ ~u14 3 E;~ '' ~ st ~ ~
en ~ 1 (31) en ~ en c ~
q~r l= x wr ~ a~
osr G X o~r ~ x cnt ~ ~ cnt x ~mul6}
~t ~ x st ~ 16 erl ~ x en ~ 31 ~c~ ~ x ~c ~ 16 wr ~ x wr ~ x o;r ~ ~ osr - x cnt ~ a~ cnt - x ~}
~;t 11: %
en ~ x SC ": X
wr - x o~r ~ x cnt ~ x ~divwl) {~ivw2 d ivw l;t ~ 0 ~t ~ 0 en ~ 31 en - -1 m~d ~z ~lS) ~sc ~ wr (16) ~c ~ 16 wr - BC~12:7J (16) wr - wr - 1 0~ o~r cnt 8 ~C cnt ~ 2 ~divw3] ~[divw0.]
t ~ wr ~ ~6 ) ~t ~ 0 en ~ 31) en ~ 31 ~I;C ~ ~r (16~ ~c e wr wr ~ BCI12:7] (16~ wr ~ ~c o~r - ~ o~r ~ a~
CD~ 8 ~n~c - x ~divw5~ ~div~6~
4 ~ ~ 16 .- - : . . . . .

en ~ no~ s~ze ~7) en ~ 31 ISC ~' 2~ 6C ~ 16 3~r ~ x wr ~ x ~nt ~ x cnt ~ x ~vw7) ~;t - 6t t 3 1 ~c 0 o~r ~diYll} {div12 ~livl st ~ wr - 1 (31) ~ ~ O
en ~ 1 (31) en -1 (313 ~r ~ BC~1207] (32~ wr ~ wr - 1 osr - x o~r ~ ~
cnt ~ nt ~ x ~div13} {divlg }
en ~ 1 (31) en ~ 31 sc - ~ sc s ~
~r ~ x wr ~ x 05r ' X o~r - x cnt ~ x cnt = x {} {di~16}
~t c x st o 16 en - ~ en - 31 s~ ~ x ~c ~ 16 wr Y x wr - x osr ~ 5c osr s x cnt ~ ~ cnt ~ x ~t ~ x en ~ x 6C ' a~
~r ~ x c~sr ~ ~
cnt c x ~E~ {}
unk ~ t ~ x en ~e x er~
~;~ = x s~ -- ~
wr ~ r - a~
o~r ~ ~ os~ ~ x cnt ~ ~ ~nt ~3 ~) l) ~ t ~ x en ~ ~ en ~ x l~C ~ x e X w~r fR X
~r e X ID;E;~ C X
Cllt ~ ~ cn~c ~ x unk6 ~
t ~ 16 en ~ ~ en ~ 31 ' ~ E;C ' 1 6 ~r ~ x wx - x 05r ~ 0l5r - x cnt ~ x cnt G
~}
St e X
e~
~;C T= 3~
wr - x osr 9 a~
cnt -~a~ll} {asl21 asl st w 0 ~t ~ x en ~ osr + ~wr en = ~ (wr-l) mod ~z sc ~ ~wr ~ 1 8C ~ X
wr l= DB 15:01 or Bctl2:7~ (Q) wr ~ wr o2~r - BC[S: 131 (8"16,32) osr = o~r cnt ~ x cnt -{asl3] {~sl~ ~
~t ~ 0 st ~ o~r ~ wr en ~ osr - 1 en ~ ~1 mod ~z ~c -- ~ ~c -- x wr ~ wr wx ~ wr o~r ~ ac o~r ~ x cnt - 9~ cnt ~ x {} ~asl6}
st ~ x ~ - 16 en ,c ~ en - 31 8C 3' 5~ 15C ~: 16 wr ~ ~ wr ~ x Ofi~ C OiCx ~c ~
n~

~t en ~ s~
x ~r G X
oE;r ~7 cnt ~ x la~xl3 ~a~s2}
a~r ~ wr st ~ wr ~ 1 en e o~r - 1 en ~ twr 1~ ~Dod E;Z
~1;~ ~ wr ~c e 5t wr ~ DB ~5:01 or BC~12:7~ (Q) wr e wr osr ~ BC:15:0] ~8~16,32) o~r ~ o~r cnt ~ x C~l~t 8 la~r3~ ~ }
2;~c ~ o~r - 1 st ~ x en z o~r - 1 en ~ x c c x wr ~ wr wr c a~
~sr lc o~r c~t - x cnt -I } la~63 ~;t ~ t - 16 en ~ x en ~ 31 16C ~ X l;C D 16 wr x wr ~ %
o~r ~ x o~r - x cnt ~ x cnt ~ x g}
;t e X
en ~ x sc s x wr c x osr ~ x cnt - x trotll} {rotl2}
rotl st ~ o~r E;t ~ x en ~ -1 (31) en ~ ~ ~wr ~ 1) mod ~z sc ~ o~ ~c ~
wr ~ DB lS:Ol or BC[12:7] (Q) wr le wr osr ~ BC15~ 8716,32) o~r = oEr CDt ": :IC cnt - x tl3~ 1[}
$t ~ st en ~ 31 en - 8 sc - ~ ~wr - 1) ~od ~z sc wr ~ wr wr G
08r ~ o~r o~r z :~
G X
~[} . ~o~l~}
~t 8: J~ Bt 5 16 en ~ sz erl ~ 31 ~;c ~

3.
wr ~ x wr 8 51:
O};~ ~ X OISIC es X
~t .c 9~ ~:nt ~ '.1 en ~ x ~sc ~ x ~irr ~ ss ~s~ ~ x t ~ ~t ~ko~rl~ lrotr2}
rt3tr ~;t ~ 08r ~t ~ x en. ~ ~1 (31) en ~ (wr - 1) mod ~a:
~ISC ~ ~r ~c ~ ~
wr ~ D~ [5:0J or BC~12:7] IQ~ wr ~ wx o~r ~ ~CI5:0J 58tl6,32) o~r ~ o~r cnt ~ x Cllt ~ x I rotr3} ~ }
st ~ 0 ~t ~ x en G 31 en ~ 8 ~;c - wr mod ~ ~c ~e x wr ~ wr wx ~ 2~
o~r z o~r o~r ~ x cnt ~ x cnt ~ x f } { rotr6 ~
st ~ x st ~ 16 en ~ x en ~ 31 2;C = ~ sc ~e 16 wr ~ x wr ~ x osr ~ x osr c x cnt ~ x cnt ~ x l~
st ~ x en ~ ~c 8C ' ~
wr ~ x o~ ~ x cnt ~ 8 Iro~ll} ~roxl2 ~oxl . ~ ~ O ~t ~ ~
en ~ osr ~ ~wr ~14) en ~e (osr - wr) moa ~z 31) ~c - ~
wr ~ BCI12:7] ~1) wr ~ ~7r osr ~t ~CI~ 163 o~r ~ o~r :nt ~ n~
~[~oxl3} ~Io~1~3

5~ lQd ~ E;t " ID

~5 en ~ d ~z en - o~r ~ ~wr ~3 ~;c - ~- lwr~ z ~c ~ -wr ~ 1 ~r ~ DE~ 15:~1 or BCI12:7] (Q~ ~r ~ ~r osr ~ BCI5:~] ~8~16,32) o~r ~ o~r c~t 8 X cng e ~c ~oxlS} lroxl6~
~t c ~ iwr~ 1) mod ~z ~t ~ 16 e~ 1 mod ~z en ~ 31 X;C 8 ~ r~ aod $Z 8C 9s l~Ei wr wr ~ wr - 1 - osr ~sr ~ o~ r cnt ~ x ~nt a ac ~o~17~
~ t e wr - 1 en c o~r - 1 ~r - wr oE;r ~ osr c~t ~ x lroxrl~ ~roxr2?
roxr $t - wr st ~ 0 en ~ osr - 1 en ~ (wr ~ od sz æc wr ~c ~ ~
wr ~ ~CI12:7] Il) wr ~ wr osr c BC15:0] (16) osr 8 nsr cnt s x cnt = x trox~3} { roxr4 11 st - ~ 6t ~ w~
en ~ (wr~ 1 en - csr - 1 $C ": (wr~ 24 ,16, ~ sc - wr wr ~ D~ l5:0] or BC[12:7] (Q~ wr -- wr osr ~ BCI5:0] ~8,16,32) osr - osr cnt ~ x cnt c x IroxrS~ {roxr6~
~;t ':: 0 51t ~
en - ~wr-l) - 1 ell ~ 31 ~c - Swr~ 24 ,16, 0 6c c 16 ~rr ~ wr wr c wr - 1 - osr o~r o~r o~r - osr cnt ~ ~ cnt lroxr7}
st c 0 e~ osr - wr ~;c ~ 1~
~r G W3~ -osr ~ o~r ~:nt ~

3~

(~f rgl ~ lbf rg2 ~f~ 6t ~ ~ I;t ~ ~
en o 31 en ~ wr ~ 1 ~;C " 06r + wr ~C ~
~r ~ DB~4:0] or IRC2[~:~] e.Jr ~ wr o~r ~ REGBt4:01 or IP~C211~:6] osr ~ o~r ~nt ~ nt ~ x {brg3¦ l 3 ~ ~ 0 ~t ~ a~
en ~ 31 en ~ x 8IC ' o~r ~ wr ~c ~ x wr ~ wr wr ~ x osr ~ osr osr ~ x cnt ~ x cnt ~ x ~bfrg57 6~frg6}
E;t ~ 16 en ~ x en ~ 31 sc - ~ sc ~ 16 wr ~ wr wr ~ wr o~r ~ x o~r ~ osr cn~ 0 ] ~ D~ 0 ] cnt lb~rg7 }
en ~ 31 ~c = ~5 wr ~ x osr ~ x s::nt ~ x {bfmtll ~bfmt2}
bfmt s;t ~ 3 ~t ~ 00:
~(o~rl2:0]~(wr-1)) en ~ -1 t31) en ~ (osrl2:0]~wr-1)) [4: 31: ~osr 12: 01 ~c ~ 3 ~c ~ 0 wr - DBl4:0] or IRC214:91 wr ~ wr o~r ~ RE~BI~:0] or IRC2~10:6] osr ~ osr cnt - x cnt ~ lo~r 12: 0] ~
(w~-l) ) 15:31 bfmt3 ) ~ bfmt4 }
G 0 ~i ~C $ 0 0 .
~(osrl2:0]~wr~
~n ~ o~r 12:0] en - -1 mod ~;z (7) ~1;C 0 ~C G ~j3 wr ~ ~12- Wl~ r o~r ~ ~r o~r ~ a~
cnt ~ x cnt lbfmt5~ ~bfmt6J

~3 ~n ~ x en ~ 31 SC ~ 16 wr ~ x wr e wr o~r ~ x 08r '' o~;r cnt ~ x snt ~ x ~bfmt7 }
~it o x en ~ x ~c ~ x wr IY x os~ ~ x ~r2g ~ ~
~bfmiî~ ~bfmi2}
bfmi ~;t ~ 3 6t ~ 00:
~ ~08r t 2: 0] ~ (wr-l) ) en ~ 1 (31~ en ~ ~osrl2:0]~(wr-1)) ~4 :3] :~osr 12 :~
~;c = 3 ~c ~ 1a0:
~osr12:01~wr~
wr c DBl4:01 or IRC2 l4:~] wr ~ wr osr - REGBl4:0] or IP~C2~10:6] o~r c osr cnt ~ x cnt ~ ~osr l~o0~
(wr-l) ) 15:31 ~ bfmi 3 } { bfmi 4 }
st ~ 0 st - 00:
~(osrl2:0~(wr-13) en ~ ll:~oærl2:01 en - -1 mod S2 67) fiC G ~ osr12:0]~(wr-l)) 8C c 0tl ~ 50sr 12:01 + (wr-l) ) wr ~ wr wr - wr osr ~ osr osr - x cnt c x cnt ~ x {bfm.~ 5} {bfmi6 ~
St ~1: 11 Bt ~: 16 en ~ 00: (osrl2:0]~(wr-1)) en ~ 31 ~c~ 25~(a0: sc~ 16 (osrl2:0]~(wr 1~)) wr ~ wr wr ~ wr osr c x osr ~c osr cDtl1:0] ~ DB 11:0] c~t x {~i 7 }
5t e la en ~ 31 $C = 25 o~g ~ , cnt ~ ~

~y l[c~pl~ ~op2}
cop 61~ ~ x ~t ~ ~
en ~ ~ es~ ~ x ~c ~ x ~c - ~
wr ~ x wr ~ wr - 1 o~r ~ ~ o~r ~ x cnt 8 9~ cnt ~ x ~p3 ~ ~ csp4 }
X fi t 8 X
en ~ x en ~ x ~iC ' X $C ~ X
wr c ~ wr ~ x o r ~ x 08r ~ X
Crl SC 2 9~ t ~ cop~ } { c~p6 st ~ x st ~ 1~
en ~ ~ en ~ 31 ISC C X ~C ~ ~6 wr ~ DB 17 o 21 wr ~ a~
osr - x osr ~ x cntll:0] DB 1~1:01 cnt ~ x { c~op7 ~
X
en ~
~c = x wr ~ x osr c x cnt ~ x ~1~ loaded ba~ed on ird l5~ if ird l5] = ~ then b~r value comes from BC bus else value is loaded from regc.

FTU - FIELD TRANSLATION UNIT ûP~RATIONS:
3- LDCR load the control regi~ter from regb. The ~egister i8 ~elected ~y the value in ar ll:01, this ~an be gated onto the rx bus.
4- DP~ load the psw with the value ~n regb~ Either ~he ccr or the p~w i~ loaded depend~ ng up~n ~i ze ~ I f ~ ~ ze ~ byte then only load the ccr portion O
).4- CLnEP clear the f-trace pending 12tcho (f~end2 only) ~;.7- L~S~2 load the conter~ts of lthe ~hifter control ~egi~er~ from regb~, The~e ~nclude W~C, O~ E t count ., 9~ S~B load the ~nternal bu$ reg~ter rom regb.
Thi~ ~s composed of bu~ contr~llex ~tate ~nor~on which inust ibe acce ~ed by the user in iEault 6itu~ion~ .
1- LDS~I loa~ the ir~t wQrd oiE s~wi (internal ~tatus word) from regb. ~bis i~ c!omposed of tpend, iEpeDdl ~ fpend2, ar lateh 3-- ~DSIil loa~ the content~ of the shi~ter c~ontrol regi~er~ from regb. The~e include st~n,~c"
5- LDr)PC load mi~ro pc into A4 from regb and check validity of rev ~.

6- LDPER load per with the value on the a-bus, ~hould be a T3 load3. ab>per 8~ LDARL load the ar latch from regb. May be able to share with ldswi or ldswj 9- 0PSWM clear the psw master bit.
33- RPER load output of per into ar latch and onto bc bu~u There are two operation~ which use this ~unctiont MOVEM a~d BFFFO. MOVEM
require~ the ~east significant bit of the lower word (16-b~it~ only) that is a one to be encoded and latclhed into tne AR latch and onto tbe BC BUS ~inverted) ~o that it can be used to point at a register. If no bit~ are one then the end ~ignal ~hould be active whi(:h i~ routed to the branch pla.
A~ter doing the encodiDg, the lea~t ~gDif i~ant bit sboulâ be cleare~ .
~or BFFFO it i~ nece~sary to find the most signifi~an'L bi~c o~ a long w~rd tbat i~ a one. This value is encoded into 6 bit~
where the mo~ ~ignif icant bit ~i~ the 32-bit all zero ~gnal. Thu~ the following bit~ would yiela the corresp~o~ing encod i ng .
mo~t ~i9 bit ~et per out onto bc bu~
31 ~ 0 16 ~! 10~00 1111~
y ~000~ 1111 1~11 NONlE 1 11111 ~000 O000 The ou~put i ~ thleD gate~ ont~ the BC bu~
where it ~ n e~te~aded to ~n 8-bit 35;~
~lueO It doe$ not hurt ~nyth~ng ~ the ~FF~O ~:~se to load the other latch (i.e.
lBFFFO ~an lo~d 1:he ~ tch)~
~or 113FFFQ it doe~ not m~tlter ~f ~ bit clearea O
~- STCR store the ~ontrol ~gi~ter in ~egb. The regi~ter i~ selected by the value in ar ll:0J, this can be g~ted onto the rx bus~

7- STP5W ~tore the p~w or the ccr ~ r~gb ba~ed on size~ If ~ize ~ byte then s'core CCE only with ~it~ 8 15 ~ 2ero6.,

8~ BPEND ~tore the psw in regb then ~et the ~uper~risor bit and clear the tr~ce bi~ in the psw. Tpend and ~pend are cleared~ The whvle p~w i s ~torea i~ regb,

9~ lPS~S ~tore the psw in regb then ~e~ the super~ or bit and cle~r both trace bit~ in the p~w . The ~hole psw i ~ 6tored in regb .
0- STItaST ~tore IRD decoded information onto the BC
bu~ and into regb. Thi~ data can be latched from the ESC bus into other latc~hes ~i.e. wr & 08r) by other control.
1- STIRD ~tore the ird in regb,, 3- STINL store the new interrupt level in pswi and regb. Th~ three b~t~ are loaded into the corresponding p~wi bit~ The ~ame thre~
biks are loaded onto bc bus 13:ll with bc bu~ l3l:4] 1 and l01 ~ l, which is loaded into regb. Clear IPEND the following Tlo 4- STY~ store the iEormat & vector n~mber as~ociated with the exception i~ regb.

:K ¦ X ¦ FO~M~T ~ YECTOR MUMBER 3 15 14 13 12 ll l~ 9 ~ 7 ~ 5 4 3 2 l ~
7-- STCRC ~tore the contents of the CRC: regi~ter in regb. Latch A4 with micr.oaddre~s.
48 STSH2 ~tore the content~ of the ~ifter ~ontrol regi~ter~ into reglbO Th~e inc:lude ~r,os~,count. ~tore hig1~ portion o~ shlft control 50- STSWB ~t~re the ~nterrl~l bu~ ;cegi~ter i~ regb~.

3~7 21 ~3 ~his ~ c~mpo~ed of ~u~ ~ontroller ~t3te ~nformation wl~ch mu~t be ~cce~ed by the user ~n iE~ult ~ituation~, 52- ~TS&aI ~toYe $swi ~ i~ternal ~t~t-as word) ~n regb.
~he ~swi i~ composed of tpend, ar l~tch, pendl, fpend2 5~- STSHl ~tore the ~ontent~ of the ~hifter control register~ into regb. The~e ~Dclude 6t ,en, ~c .
:~ 56- ST~PC ~tore the ~icro pc in regb5, REV N~MBER ¦ CPcC ¦ MICRO PC
15 1~ 9 ~ 7 6 5 ~ 3 2 1 0 63~ STPER ~tore the per onto the a-bu~ hould be Tl transfer). per>ab PC -- PC SECTION OPFRATIONS:
AOE~P l l 3 31 - 3P~ V3FI ¦ OD3FI
30 -- 3PFF ¦ TPF I E:V3~I
a- ~IF
2~obpt>db>$a~
tp2~ab>sas 1-- ~PF
aobpt>~b> tpl aobpt>db~aup>aobp* ,aobpt ~2>aup tpl>'ltp2 tp2~ab>~a~

~p2?ab>a-~ect ( if ry~pc then conr~ect pc and addre~s ~ection aobpt>db>~a~

aobpt>db>tpl aobpt>db~aup~aobp~ ,a~bpt ~2~aup t~tp2 tp2~ s~ct (~f ~y~pc the~l ~onnect pc ~n~ ~ddre~6 ~ection) 4 JMPl tp~ e~
t>ab~aobpt aobpt~db~tpl ~pl> ~p~
tp2~ab9sas aobpV db~tpl*
~obpt3db~aup~aobpt ~4>aup tp2~ab>~a~

~obpt>db~aup>aobpt,tp2 ~2>aup tp2>ab~sas tp2>db>a-sect pc>ab~sas ~- TRAP2 tp2>ab~a sect aobpt~db>sa~
9- JMP~
a-sect~ab>aobpt aobpt~db~sas PCO~T
pc>ab>a-sect aobpt~db~$as 11- NPC Cond~tional update ba~ed on cczt/f tp2>db>aup~a-~ect a-sect>~b>aup~aobpt a-~ect>ab>tp2 aobpt>db~a~
13- SAV~l pad~aobp aobpt>db~sas tp2~ab>~a~
15- SAV~2 ~o~p>db>tpl tp29ab>$a~

'~

37 ~3 4- ~X
alolbp1;~db~ tpl tp2>ab>~c~bp~
~t~l> tp~

~p2>p~
aobpt~t31b>sas tp2>ab>~a~
PIP~ - PIPE OPE~R~TIO~a~
De~cr~ptioD o bit encodings.
161 ~ use ir~:
5] ~ change of f low 41 ~ etcll in~truc~iorl 3:0] ~ previously defined pipe control f unct ional ity .

AOBP ll 0 1 1 3 - 3UDI ¦ EV3Fa I OD3F
1 0 1 7 - 3UDF O TfUD ¦ EV3Fb -- EV3F~
chrl>irb cl~rh~pb> imll, iml J i rc chan~e of ~low fe~h in~tr -- EV3Fa:~
chrl~irlb chrh>pb~imh, iml D i rc irc>ir I implie~ use irc ~se pipe fetch i~str chrl>pb~irc ~ force mi~;s regardle~s of whether odd or even cha~39e of rlow :Eetc~ i~str 0 0 ~ UD

1 ~ 0 11 -- ~IPE
u~e pipe lil 1~ 1 1-- FI5C2 ~lways tran~Eer irb up p~pe ~D

2~ 2~L
b ~o ~rc t ~m ~ b ~eed i rb~pb> l~h, iml 1~ i rc to be repl aced ~ d~ ~c~e~s ~nd ~r2n~;fer c~r to irb.
~ fo~l:e mi~ regardle~s of whet~er odd or even chanse of ~low"
fetc:~ ~n~tr db>ird el~e load irb from d-bus.
irb>pb~i~h, iml, irc c~ange o~ ~Elow fe~ch iD~tr iF~d~
0 0 0 ~ TOD
ir~ i rd 0 1 5 -- Fl:Xl chr~irb if irc need~ to be repl~ced, do accesfi and trarF, f er chr to irb, else no activity.
I force mi~s regardle~s of whether odd or even change of f low :Eetch instr 0 6 ~ 2 TOC
irc2`-irc ixc> ir u~e pipe 0 0 0 8 -- C1.RA
clear irc2 1141 ira>ab zxtd 8 -> 32 0 1~ 0 9 -- srIRa~
db~ira ira~pb>irc2 0 O ~ ATOC
db i r~
~ra>pb>irc 0 0 1 13 - I:UD
chr> ~rb i rb>p~ imh ~ iml ilEetch in~t~
14 - C~OD
irc~ r,ird irb~ ~.re ~se pipe ~hr~irb i ~b>pb~ h ~, irnl, i ~c irc~ ~
u~e p~pe c~ str ~hr> i rb i rb>pb~ imh, iim~ ~ i rc irc~r cllange nf flow ~Eetch in~tr Y~

APPENDIX I I ~3~
MICP~OINSTRUC~ION SEQUENCES
CALLM E:A
A~
¦ FA5 ¦ C~D01 ¦ 36e 1 ¦ DB
X ¦ DATA ¦ l~)T ¦ RI ¦
_*____~_~ +
n PT @ NJ3W PC~ ADD
AOB>DB>AU>AOE~ NIL
4~AU X
~ STORE EVAL EA" X
AOB> DB~ > REGA SBM2 ~'STORE MMU DESCRIPTOR ADDRESSq' NONE
REGB>AB~AT jDT NF
"ST=24 ,,EN=31,SCS24" NUD
"CLEAR BAD IRB"
AOB~ DB~ I RB 3,~31 + ~
¦ FB5 ¦ CMD02 ¦ 36f ¦ ¦ DB
+_ +___~_+____+________+_~
LONG ¦ DATA ¦ RX ¦ RY ¦ C> T0 UNK
"READ NEW PC" ADD
~'PT @ MDP" AND
AOB>DB~AI)~AOB X
4>AU X
"TEST TYPE" X
D~I N>DB> ~ I RA, REGBNON~
"BUILD 0 IN REGA" NF
0 ~ ALU > REGA tlATOC
"STVRE DESC~ ADD~Rn REGA~AJ3>AUT 2/25 +___~_________~_____+_____________~..____+
¦ FC5 ¦ CMD03 ¦ 3c0 ¦ ¦ BC
-- t------_~________~___ LONG ¦ DATA ¦ SP ¦ RY ¦ C> T0 UNR
+_____~____.~______*______+_.._ ____~_____~
~ READ MDP n S llB
"STORE NEW PC~ NIL
DBIN >AB~AOBPT X
~PT ~! STACK SP~ INS
SP>I:~B>AU~AOB X
4 > AU NONE
~B13 I LD TYPE ~ JMP2 REGB>DB>SAD NUD

~_________-______________ _____ ___~_____~
FD5 TYPE0 OPT0 -$ cMDa5 1,FF5) TYPEO OPT4 --~ CMD04 (FES) TYPEl --> CMD13 (FE6) I LLEGAI.FORMAT --~ XFEA ( FE9 ) 2~
TYPE 8 13 ~ SAVE STACI~ (CMDa3 ) ¦ FE5 ¦ CMD04 ¦ 69f ~ B
_ + _ ~
LONG ~ :1i35T I SP ¦ IRY ¦ <W~ T0 + ~
';W~RITE STACK ID~l) SP" X
SP>AB>~DOB NIL
% Al)T>DB>SA X

NONE
NF
NUD

. ._.__~. ________~__. __+________ ____~____ ~
¦ FF5 ~ MD05 ¦ 49f ¦ ¦ DB
BYTE ¦ DATA ¦ SP ¦ RY ¦
~_____+_~_ ~____._~______~________~_____~
'nPT @ 5TACR OLID PC"SUB
SP>I:lB~AIl>AOB, SP NIL
0C>~V X
~'STORE OLD PC" X
TP2>P~B>AT X
~STORE PSW" STPSW
~6 REGA::~AB>SAD TRAP2 % REGB>DB>SAD NUD

¦ FG5 ¦ C:1`5Dl!l 6 1 3cl ¦ ¦ DB
+___+~ +___-~_~____~__ ____~_____~
LONG I DATA ¦ SP ¦ RY ¦ ~:W> ~0 +_____~____+______~______~________+_____~
"WRITE STACK OLD PC" SUB
AT> AB DOB N I
"PT @ STACR DESCPcIPTOR"X
AOE~>DB>AU>AOB, SP X
4>AV X
% REGB~DB>SAD NONE
TPF
TOAD

. . _ _ ~

¦ FH~ ¦ C~D07 1 3c2 ¦ ¦ DB
+_ ~
Lt)N~; i I NST ¦ R~ ¦ RY ¦ <W> T0 +-~___ ~______~ _- _____~_____-~
"WRITE STACI~ D13SCRIPTOR~ADD
AllT~AB'">DOB !NIL
"PT ~! STl~ MDP" X
AOB>DB>AU>AOB X
3>AU X
RF,GB> DP, > S AD NOM E
~PP
TUD
11/~
¦ F~ 5 1 CPSDli58 ¦ 3c3 ¦ ¦ DB
X¦DATA¦ RZ¦ RY¦ SPC X SYNC J
+_____+____~______~______~________+~___._~
~ rS TORE OLD MD P " X
RZ>ABDOBNIL
"LOAD NEW MDP" X
DBI N>DB> RZ
" SYNC TO E:NSURE NO STACR" X
~'ON MDP"NONE
NF
NUD
../a +__ +_________~ ____+_____________+__~
¦ FJ 5 ¦ cMDa 9 1 3c8 ¦ ¦ DB
+~ +_~_+~ +___ -___~_____+
LONG ¦ INST ¦ SP ¦ RY ¦ <W> T0 +_____+~ +_____~
"WRITE STACK MDP" SUB
"PT @ STACK ARG CNT" NIL
AOB>DB~AU~AOB, SP X
0C>AU X
% REGA>AB> SA X
% REGB> DB > SAD NON E
l[PF
TllD

¦ ~K5 ¦ CMD10 ~ 3c9 ¦¦ DB ~ ~f~
_+ _ ~
BYTE ¦ DATA ~ Y ~ O
"E~UILD TYPE:OPL0:ARG CNT" X
PER>AB:~ALU>REGA AND
-l>ALI~ X
REGA> DB>FOOIJ I T X
% AT>DB~SAA X
STPER
TPF
TUD
11~0 _ _ _ _ +
¦ Fl-5 ¦ C~SDll J 3ca 1 ¦ DB
+ ___~__~___+_~__ _+_~
WORD ¦ DATA ¦ SP ¦ RY ¦ <W~ T0 +_____~,___+_____-+______+____~
"WRITE 0 :ARG CNT" SUB
P~EGA>DBDOB AND
"BUILD TYPlE:0-CCRJTYPE:OPL:PSW" X
REGB>AB>ALU~ALUT X
REGA> DB~ FOOL I T
-l>ALI~l NONE
"PT ~ STACK TYPE: t:)PL: 0: CCR" NF
AOB>DB>AU>AOB, SP NUD
4>AU
% AUT>AB>SAA 11/0 ~___~_____ ._ ._~_____~_______ ._____+_____~
¦ FM5 ¦ CHD12 ¦ 3cb 1 ¦ Al ~___+_+~ +_~____~_ ______+_____~
LONG ¦ INST ¦ ~Y ¦ RY ¦ <W~ Ta "WRI TE TYPE: OPI.: PSW~ X
ALUT>DBDOB NIL
% AT>DB> SAA X
% AUT>AB>SA X
COLl STINS
NF
WUD

+______________________r___________~__~__+

5~ ~ ~3;
INVALID FORMAT (CMD~3~
¦FE4¦ XFE~ ¦ 49e ¦ ¦ DB
I XII~STl RX¦ RY¦ EXL X FORE ¦
+______~______~________+_____, n STORE REAL PC~ X
PC>AB>AUIT NIL
e~ PSW>REGB ~ l~PSWS t li5> PSWT~n X
"~9>TPEND" X
% AT~DB>SA X
% REGA>AB>SAn o PEND
PCO~T
NUD

. ._~ -----¦FF4¦ XFEA2 ¦ 36d ¦ ¦ DB
X~INsTl RX¦ RY¦ o ~_____~____~__ _~_+______~________~_____~
nCQRPcECT REAL pcn SUB
AUT ~DB~AU>AUT NIL
2>AU X
% REGA>AE?,:~SA X
% RE:GB> DB> S i~D X
NONE
NF
NUD
. 12/20 . .___________________._____________~_____+
FG4 TRAP2 (IJ5) TYPE c 1 (CMD03) +_________+__-___+____ ________~_____~
¦~E6¦ CMD13 ¦ 79f ¦ ¦ DB
_+___*_~____+-_______~_____~
i IR5Z¦DATA¦ RX¦ RY¦ r +_____~__: ~______~______~________~_____+
~PT @ DESC. NPL" ADD
AVT>DB>AU>AOB COL2 l>~U X
~TEST ARG CNT" ~l PER>~B~AL~T
~FORM STAC~ PROBE~ STPER
PER>AB>A~>REGB NF
-l>ALU NUD~
REGA>DB>YOOLIT
12~16 -6~ 3 ¦ F3?6 ¦ CMD14 ¦ 481 ¦ ¦ BC: ¦
IRSZ ¦ I~Sq' I SP ¦ DTY I ~> T0 UNlt ~ _ _ _ _ _ + _ ~
"FlEAD !DESC. NPL" X
"STORE ~EW MDP~ AND
DBI ta~AB>ALllT X
~ BU I LD MMU BAS E Al)DRES S ~ X
0>ALU>DTY SBM2 AT>DB>FOOLIT NONE
STORE STACK PTR" NF
SP>AlE~> :~ AOB NUD

. .__________________ _____________--~_____+
FG6 LOCZ -> CMD18 ~FH6) I~OCZ -> CMD15 ~FH7) ARG t::NT <> 0 - MAKE STAC~ P~aOBE ~CMD14 ) _ +
¦FH7¦ CMD15 ¦ 551 ¦BFME3 ~EK5) ¦ DB
~___+_+~ +________~_____~
WOP~D ¦ D~TA ¦ RX ¦ RY ¦ l ~_____~____+______~______+________~,_____~
n PT ~ STACK PROBE" ADDXS
AOB>AB>AU>AO13 NIL
REGB>DB> AU X
% REGA>AB>SAD X
X
NONE
~F
NUD

. .___+_________+_____~_____________~_____+
¦ FI7 ¦ CMD16 ¦ 4a7 ¦ ¦ DB
~___~_~____~__~___~_~____~________+_____+
¦ IRSZ¦DATA¦ DT¦ RY¦ ~> T0 ~-------- +----~
'MA~RE STACK PROBE" X
nPT ~ MMU CPLn NIL
DT>DB>AOB X
n STOlRE NPL" X
DB I ~> AB:~ > REG13 X
% AUT>AB> SAA NONE
NF
NllD
12~

. ,___+__._______~_____~__ __________+_____+

4~

~ j >?3--¦~J7I CMD17 ~ 52e ¦CMD37 ~PS8)¦ DB
¦ IRSæ¦DATA~ RX¦ RY¦ C> T~ CP~1 1 + + .~ t ~READ MMU CPL~ X
~PT ~ MMU DESC" NIL
AT~D~ AOB X
% AUT~AB>SA X
% REGB~DB>S~D
NONE
NF
NUD

. . . -- ~ ~
F~7 GMD2~ (FJ6) ARG CNT = ~ - NO STAC~ PROBE (CMD14) + ~ + ~ ~
¦FH~¦ ~MD18 1 ~50 ¦FERI1 (~F2)¦ DB
+ ~ ~ ~
X ¦ DATP~ DTY ¦ ~ l +_____~____~ _.~__~______+________+_____~
nPT ~ MMU CPL X
DTY>DB~AOB NIL
% REGA>AB>SA X
x x NONl:
NF
NUD
, 1/11 . .__._~_____ ___+___ _+_____________~_____+
¦FI~¦ CMD19 1 483 ¦ I DB
~ + + ~ + + ~ .~ + ~
I IRS~¦DATA¦ XX¦ RY¦ <~ T0 CPU1 1 ~ + ~ + ~ . ~ +
~READ MMU CPL" X
"PT @ MMU DESCRIPTOR" NIL
AT>DB>AOB
nSTORE NPL" X
DBIN~DB>~REGB X
% AUT>AB~SA NONE
NF
NUD
12~16 ~,9 ¦ FJ 6 1 ~ MD2 lil ¦ 4 8 9 ~ ¦ DB
I~ONG ¦ DATA ¦ DT 3 RY ¦ <W> Tli1 CPUl + ~ _ + _ ~ _ _ _ ~
~RITE DESCRIPq'OR ADDP~ES5'9 ADD
;AUT>AB~>DO8 NI L
mPT @ MMU IPL" X
DT>DB>AU:~AOB X
8>AU X
NONE
NF
N~D
12/1~;
. ~ _+_______ _____~_____~
FR6 ~~D21 i Ds8b ~ ¦ DB 3 ----+--~ +--------+----------------~ --------t szll)ATAl RX¦ RY¦ 6W> T0 CPUl ¦
+ _ _ _ ~ _ +
"WRITE NPL TO IPL" SUB
REGB>DBDOB NI L
n PT ~ MMU S TATU S " ~K
AOB>DB>AU::~AOB X
4~a~u X
% AUT>AB>SA NONE
NF
NUD

. .___~_________+_____+~
¦ FL~i ¦ CMD2 2 ¦ 4 8d I ¦ DB
+_-__~_~____+__~___+_~ +
¦ IRSZ¦INST¦ SP¦ DTY~ T0CPUl ¦
_+______+______+________~_____~
R13AD MMU STATU S ~ X
n~ LD TYPE:CPL:0:0n NIL
DBIN~D13>~REGB X
nSHUFFLE NEW MDP~' INS
ALUT>AB>DTY X
"STOP~E OLD SP" NONE
SP>DB>AT NF
% AUT>AB> SAA NUD

. . ._ _ _ + ~ + _ ~

- 9~ -¦ ~M6 J CP~D23 ¦ 4al ¦ ¦ DB I ~L~ J~

¦ ~RSZ¦I~ST¦ R~¦ RYI .
n l; TORE ~SI) S TATU S ~ X
DB I N > D~B> RE:(;C N I L
DBI N>DB>ALUT X
~SHUFFLE ARG CNT" X
PER>ABREGB SBM5 STPER
NF
NUD

. ._____~ .
¦F~6 I CMD24 ¦ 4a3 ¦ ¦ BC
¦ IRszlDATAl SE~I RY¦ . l ~_____~____+______+______~_~______+__ __~
"PT @ 5TACK SP" SUB
SP~D8>AU~AOB NIL
4~AU X
~ S TORE OLD S P ~ X
AT~ABDOB X
"STORE ARG CNT" STPSW
REGB>DB I RA NF
"0 :CCR IN REGB" STIRA
1~/21 + ___ _______ _ ., .__ _ _ _ _ _ _ _ _ __ _ _______. _____ . ~
FO~ WR~0 -> CMD26(FP6) WR=0 CNT~0 -~ CMD27 ~FP5) WR-0 CNT-~ -> XFEA (FE4 ) VALID -- SP CHANGE ~CMD~4) +__ ~_________~_____~__________ __+_____+
¦ FP6 ¦ CMD26 ¦ 59f ¦¦ BC
~___~_+____+__~___+_~____+________+__ __~
LON~ aST ¦ RX ¦ RY ¦ <> T3 UNK
~_____~____+______~_____+________~_____+
"READ N~W SP" ADD
A~T>DB>AU>AOB NIL
0C>AU X
~STOR~ DESCRIP~R ADDRES5" X
AUT~DB>ALUT
% REGA~AB> SA NONE
~aF
NUD

~_____.____ -_ ~ ____ __ ____ .__________. ._____~ .

FQ6 OPT4 ~ MD29 (FR5) OPT0 -~ CMD3 0 ( ~R6 )

-10-VAt.ID - NO SP CHANGE (CMD2~ ) ¦ FP5 ¦ CMD27 ¦ 5~e 1 ¦ DB
~___*_~ +_+____~______ _~_____+
LONG ¦ DATi~ ¦ SP ¦ DTY ¦ ~W> T0 +~ __+______+~
~WRITE STAC~ ~P~ SUB
WPT @ STACR OLD Pl:" NIL
AOB>DB>AU>AOB, SP X
8>AU X
" STOPcE OLD PC~ X
TP2>AB>AT NONE
"POSITION NEW MDP" TRAP2 lDTY~AB~DBI N NUD
% REGB>DB>SAD
. ._____________ ___-------------------------- ----~-----------t FQ5 CMD~6 (FG5) NO STACK COPY (CMD26 ,CMD28) ~___~_________~_____+____________+_____~
¦ FR5 ¦ CMD29 ¦ 69c 1 ¦ DB
_+_~__+_~+___~_+____+________+_____+
X¦DATA¦ RX¦ RY¦ ~ l ~____~+____+_ ____~______+________+_____+
nPT Q STACK SP" SUB
DBIN>DB>AU~AO~ NIL
4>AU X
% AUT>AB~SA X
X
NONE
. NF
Nt~D

. _________________________________~_____+
FS 5 CMD2 7 (FP5 ) S~

STP~C~ COPY (CMD26) ~ ~ .
¦FR~ I CMD3~ 1 49~ 1 I D~
., ~ + ~ +
X I INST I SP I RY ¦ I
+~_~ +___:~
~STORE OLD SP" X
SP~AB~:~AOB, REGB ~IL
SP>AB~AUT X
9~ SHUFFLE ARG CNT~' X
I ~>DB>REGC SBM5 NON E
NF
I RAD
1/~5 . . .
¦ FS6 ~ CMD31 ¦ 4a5 ¦ ~ BC
. _ _ _ + . _ _ _ ~
X¦DATA¦ SP¦ RY¦ l ~_~___~____+____0_~
"PT ~ TOP OF NEW STACK" ~UB
DBI N>DB~AU~AT, SP NIL
I RA> AB> AV X
"IR~ ZXTD 8-~32 ~ X

NONE
NF
CLRA

. . . .
FT6 WR< ~ 0 -~ CMD3 5 ( FS 7 ) WR~0 CNT<~9 ~> CMD37 (FS8) WR=0 CNT=~ -> CMD39 (FS9) TYPE 1 - COPY LONG ~CMD3 1, CMD3 6 ) ~ + + ~ ~ ~

~___~_~____+__+___~_+--------~-----------------t----------+
LONG I DA~ I RX I RY I <> T0 ~READ OLD STACR" ADD
q~PT @ NEW STACK" NIIJ
A~ DB~ ~ AOB X
"PT ~ NEXT NEW STACK ENTRY" X
AT> DB>AU~AT X
4~AU NONE
% REGA>AB>SA NF
REGB~DB>SAD NUD
1~05 + ~ ~. ~ . + . ~ ~ .

5~

~12- ~ 8~
1~71 CMD36 ¦ 4a9 ¦ I BG
¦ L~N~¦DATA¦ RX¦ RY~ ~W> T0 _ _ + _ _ ~
~WRIT~E TO NEW SP" ADD
DBIN~DB>~DOB NIL
~PT @ NEXT OLD STAGK ENTRY" X
A~T>DB>AU>AOBoAUT X
4>AU SBM6 % AT~AB~SA NONE
NF
NUD

~ ______ _____ ________ _ _________ _ __. ._____. .
FU7 WR~0 -> CMD35 (FS7~
WR~a CNT<>0 -> CMD37 (FS8) WR=0 CNT=~ -> CMD39 (FS9~
TYPE 1 - COPY LAST PIECE (CMD31,CMD36) ~ _ _ _ + _ _ _ _ _ _ _ _ _ + ~
¦FS~¦ CMD37 ¦ 528 ¦ 4 WAY SHARE ¦ DB
~___+_+____~ _+_____~
iSSIZE¦DATA¦ RX¦ RY¦ <> T0 +_~___.~____~___~_~_____--~________+_____+
"READ OLD STACK"X
~PT @ LAST NEW STACK" NIL
AT>DB AOB X
AUT~AB>SA X
% REGB>DB>SAD X
NONE
NF
NUD

+_________+_____~_____________+_____. .
¦FT8¦ CMD38 ¦ 4f0 ¦ 2-WAY SHARE ¦ DB
+___+_~____+__~ _+_____ __~_____~
¦SSIZE¦IWST¦ RX¦ RY¦ <W> T0 + + ~ ~ . + +
~WRITE NEW STACK" X
DBIN>DB DOB NIL
AT>DB~SAA X
AUT>AB~SA X
X
NONE
NF
NUD
1/0~

~__________________. _________ ___,_. ____ .
F~8 CMD39 (FS9) TYPE 1 -- NONE LEFT T~ COPY (CMD31 ,C

~___+~ +___---____~_____+
X I INST~ VDT11 . I
~Pl' @ TOP OF OLD STACR" X
% ALUT> DB>AT N I L
% AUT~AB>V~I'l X
X
X
NON E
NF
NUD

+ _ ~ . . _ _ _ _ _ . .
¦ FT9 ¦ ~MD4 0 1 4b5 ¦ ¦ DB
_~+___+_+____~________~_____+
BYTE ¦ DATA ¦ S E~ ¦ RY ¦ j n PT @ S TACK S p n S UB
SP> DB~ AU >AOB N I 1.
4>AU X
"SHUFFLE DESCRIPTOR ADDRESS"X
ALlDq~>AB>AUT X
"STORE OLD SP~' STPSW
REGE~> DlB> DOB NF
NUD

~ _________ __ _ ___ ___ __.__. ___ _ _____. .__ _ __ .
FU9 CMD2 7 ( FP ~ ) RTM RY
~1 ¦ FA8 ¦ RTM01 ¦ 4aa ¦ ¦ DB
~___+_+____~__+___~_~____+________~_____+
LO~G ¦ INST ¦ SP ¦ DTY ¦ ~> Tl +_____.~____~_~____~___.___~________~_____+
5' READ TY PE: OPL: P SW" X
SP:~DBAOB NI L
n S TORE D E S CRI PTOR AI~DRE S S n X
PtEGE~>DB> DTY X
~ST=24 ,EN-31,SC=24" SBM2 ArlT>AB~ SA INONE
N~
NUD

+_________ ___. . ____. .

~S

~FB8¦ R~M0~ ¦ 4ab I ¦ ~B i ~ i8 ¦ BYTE¦D~T~¦ DT¦ RY¦ l + ~
"PT @ STACX ARG CNT" ADD
AO~>DB>AU>AOB AND
4~AU X
hEO~M MMU BA5E ADDRESS" X
0>A W >DT X
REGB>DB>FOOLIT NONE
% AUT>AB>SA NF
NUD

. ._ _~ +__ ___~______~_ ___~
¦FC8 I RTM03 ¦ 4ad ¦ ¦ DB
+ _ ~ +_~____~_______+_____~
¦ WORD¦DATA¦ RX¦ RY¦ ~3 T0 +_____+____~______~______~________+___ _+
"READ STACR AR GNT" ADD
nPT @ STACK PC" NIL
AOB>DB~AU>AOB X
8>AU ZXTD
n STORE TYPE:OPL:PS~"SBM2 DBIN>DB REGA NONE
"ST=16,EN=23,SC-16" NF
% AVT>AB>SA NUD
12/0~
. _ +_.________~_____+__ _ _.-_____~_____~
¦FD8¦ RTM04 ¦ 4a~ DB
¦ LONG¦DATA¦ ~X¦ RY¦ <~ T0 +_____~____~______~______~________+_____~
n READ STACK PC" ADD
nPT @ STACK MDP" NIL
AOB>DB>AU>AOB X
4>AU ZXTD
"STORE ARG CNT'I X
DBIN>AB>AT NONE
"LOAD TYPE FOR BRANCH" NF
REGB>DBIRA UATOC

. ._ _~_ ______~_____+ -------------------- -- t~

5~

~___~_~_______~_____~_____________+~
¦FE8 ¦ P~TM05 1 4a ¦ ¦ BC
~ONG ¦ DA~rA ¦ RX ¦ RY ¦ <~ T0 ~___._~____~______+___. __~________+_____+
~READ STACi~ MDP" ADD
"PT ~? STACK SP~ INIL
AOB>DES~A~>AOB X
4>AU X
n STC)RE NEW PC~ X
DBIN>AB>AOBPT NONE
"SHUE'FLE OPL~ JMP2 REGB>DBDOB Nl)D
12~21 ~__-__ _______,_________________ ___+_____~
FF8 TYPE0 -> RTM06 (FG8~
TYPEl -~ RTM09 ~FG9) I LLEGALFOP~MAT - > XEEB ( FE7 ) TY PE 0 ( RTM0 5 VALID TYPE 1 (RTM13) +_ _______+_____+_____________+_____~
¦ FG8 ¦ RTM06 ¦ 48f ¦ ¦ DB
+----~ ----+--~ +____+________+_____~
¦ E~YTE¦INST¦ R~¦ R~
+_____~____+______~______~__. _____+_____+
"PT 1~ SP AFTER STRIP~ ADD
AOB>DB>AU~AOB NIL
4>AU X
"RESTORE MDP REG~' X
DBI N>AB :~ RY X
n 5TORE NEW PSWII LDPSW
REGA>DBREGB NF
NUD

+___+_________~_____~_____________~_____+
.

s 7 ¦FH81 RTM07 ¦ ~2a ¦JMPl(ES2)i DB I ~23~82~
~ ~ +
~¦INST¦ SP¦ RYI . I
+
~PT @ 'IFINAL STACR VALUE" ADDX6 AOB>AB~AU>SP NIL
AT~DB>AU X
R~GA~AB>SAD X
REG~>DB>SAD
NONE

1/~8 ~_________._______________________~_____~
FI8 DBCC5 ~EU73 TYPE = 1 (RTM05) ~___~__~___~__~___~_____________~_____~
¦FG9¦ RTM09 ¦ 78f ¦ ¦ DB
~-t-___~
¦ LON~¦DATA¦ DT¦ RY¦ <> T0 ~_____~____~______+______~________+_____~
"~EAD STACK SP~ ADD
nET @ MMU DPL" NIL
DT>DB>AU>AOB X
0~.>~U X
"STORE NEW MDP" X
D~IN>AB REGB NONE
% AUT>AB>SA~ NF
NUD

+___~__.______~_____~_____________~_____~
¦FHS¦ RTM10 1 4bl ¦ ¦ DB
~ ~ -t-~____+________+__ ¦ ByTElDATAl DT¦ RY¦ ~W> T0 CPUl ¦
~_____+____~______-~______+---- ----------t----------~
V'WRITE OLP TO DPL" SU13 "STORE NEW SP~ NIL
DEsI N>AB>DT X
nPI' @ MM13 STATUS" X
AnB>DB>AU>AOB X
8`A~ NONE
% AU~>AB>SAA NF
% REGB>DB>ShD NUD

~___~_________~_____+____________.~ ____+

~5~

I FI9 ¦ RTMll ~ 4b2 ¦ ~ DB ~ 3~8~ ~
E~YTE ¦ INST ¦ RX ¦ lRY ¦ ~> T0 CPUl ~_____+~ +___~
1 RE~D S TATU S ~ X
4 AT> D13> SA N I L
% AUT~AB> SA X
X
X
NONE
NF
NUD

+ _ ~
¦ FJ9 ¦ RTM12 ¦ 4b3 ¦ ¦ DB
+ _ _ _ ~ _ + _ _ _ _ + ~ _ ~ +
¦ BYTE¦ INST~ RY¦ l +_-____~______+________~_____+
7' TEST STAT~S w DBIN>DB>P~1UT NII, % AT>DB> SAA X
% AUT~AB> SP~ X
X
NONE
NF
NUD

+___~_________+_____~_____________+_____~
¦FK9¦ RTMl~ ¦ 4b~ ¦ ¦ BC
t--~+-~ -+----~-___~___~_____+
xl INST¦ DT¦ RY¦ l ~_____~____~______~______~________~_____~
nPT @ STAC~K spw SUB
DT>DE;~AU>AOB NIL
4>AU X
a S11UFFLE NEW MDP" X
REGB~AB>DBI N X
% AUT~AB>SAA NONE
NUD

.1._________________.____.____._ ___~_.___+
FL9 LOCZ --> XFEB (FE7) LOCZ -> RTM06 gFG8) c~

I13VALID TYPE (RTM0~) ~ r 3 IN~ALID STATUS (RTM13~
+ ~ + _ ~
¦FE7 ¦ XFEB ¦ 48e 1 ¦ ~)B
X ¦ I NST ~ RY I EXL X EOP~E
,___~____~______+_~ ------+----------+
~BACR UP PC:' SUB
TP2>DB~AU~AUT NIL
2>AU X
~ P SW> REGB , l > P SWS ~ 0> PSWT " X
~ 0~TPEND" X
% AUT>AP,~SA 0PEND
% RE(;B>DB>SAD TRAP
~UD

. . ___ _ _ __ _ _ _ _ _ _ ._ _ _ . _ __ _ _ _ __ _ _ _ _ _ _ _ + _ ____ +
FF7 TRAP 2 ( I J 5 )

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1 A data processor adapted to cooperate with an access controller to control access by a first program module executing in the data processor to a second program module stored in a storage device, the data processor comprising:
first means for receiving an instruction of said first program module which requests access to said second program module, said instruction specifying an address within said storage device containing access request information which characterizes said requested access;
second means for retrieving said access request information from said storage device;
third means for providing said access request information to said access controller;
fourth means for receiving a decision from said access controller indicating whether said requested access by said first program module to said second program module is allowed or denied; and fifth means for allowing said first program module to access said second program module in response to said decision from said access controller indicating that said requested access is allowed, and denying said first program module access to said second program module in response to said decision from said access controller indicating that said requested access is denied.

2. The data processor of claim 1 further compris-ing:
sixth means for vectoring to an exception handler stored in said storage device if said access request is denied by said access controller.

3. The data processor of claim 2, wherein the second program module specified by said instruction is a code module, said instruction also specifying a selected number of arguments to be passed to said code module, and wherein said fifth means passes said arguments to said code module before allowing said requested access.

4. The data processor of claim 1, wherein the second program module specified by said instruction is a code module, said instruction also specifying a selected number of arguments to be passed to said code module, and wherein said fifth means passes said arguments to said code module before allowing said requested access.

5. In a data processor adapted to cooperate with an access controller to control access by a first program module executing in the data processor to a second program module stored in a storage device, a method compris-ing the steps of:
receiving an instruction of said first program module which requests access to said second program module, said instruction specifying an address within said storage device containing access request information which characterizes said requested access;
retrieving said access request information from said storage device;
providing said access request information to said access controller;
receiving a decision from said access controller indicating whether said requested access by said first program module to said second program module is allowed or denied; and allowing said first program module to access said second program module in response to said decision from said access controller indicating that said requested access is allowed, and denying said first program module access to said second program module in response to said decision from said access controller indicating that said requested access is denied.

6. In the data processor of claim 5, the method comprising the steps of:
vectoring to an exception handler stored in said storage device if said access request is denied by said access controller.

7. In the data processor of claim 6, wherein the second program module specified by said instruction is a code module, said instruction also specifying a selected number of arguments to be passed to said code module, the step of allowing said access further comprising passing said arguments to said code module before allowing said requested access.

8. In the data processor of claim 5, wherein the second program module specified by said instruction is a code module, said instruction also specifying a selected number of arguments to be passed to said code module, the step of allowing said access further comprising passing said arguments to said code module before allowing said requested access.