CA1212730A - Extended reference range, voltage-mode cmos d/a converter - Google Patents
Extended reference range, voltage-mode cmos d/a converterInfo
- Publication number
- CA1212730A CA1212730A CA000445397A CA445397A CA1212730A CA 1212730 A CA1212730 A CA 1212730A CA 000445397 A CA000445397 A CA 000445397A CA 445397 A CA445397 A CA 445397A CA 1212730 A CA1212730 A CA 1212730A
- Authority
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- Canada
- Prior art keywords
- vref
- switch
- agnd
- voltage
- vdd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for Vref and Agnd respectively. The "ON" gate voltage of the Agnd switch is adjusted in accordance with the value of Vref, to give switch VGS equality and therefore "ON"
resistance matching with the Vref switch over a wide range of reference voltage. Circuits are shown for developing the Agnd gate voltage varying with Vref.
A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for Vref and Agnd respectively. The "ON" gate voltage of the Agnd switch is adjusted in accordance with the value of Vref, to give switch VGS equality and therefore "ON"
resistance matching with the Vref switch over a wide range of reference voltage. Circuits are shown for developing the Agnd gate voltage varying with Vref.
Description
~2~7~
EXTENDED REFERENCE RANGE, VOLTAGE-MODE
CMOS D/A CONVERTER
BACKGROUND OF THE INVENTION
Field of the Invention . .
This invention relates to digital-to-analog (D/A) converters. More particularly, this invention relates to D/A converters using complementary-driven CMOS switches to produce a voltage-mode output signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 shows basic elements of a conventional CMOS D/A converter;
FIGURE 2 shows a known switch pair configura-tion fox adapting a conventional current-mode converter to voltage-mode operation;
FIGURE 3 shows a known switch-pair configuration for use in a voltage--mode D/A converter, and providing "ON" resistance match at one value of reference voltage;
FIGURE 4 shows a switch-pair configuration in accordance with the invention;
FIGURE 5 is a block diagxam of a gate-voltage generator for the Agn~ switch of Figure 4;
FIGURE 6 illustrates one gate-voltage generator circuit suitable for fabrication on an integrated circuit;
FIGURE 7 shows a switch-driver circuit;
FIGURES 8A and 8B are block diagrams illustrat-ing an alternative gate-voltage generator;
FIGURE 9 shows one circuit schematic for a gate-voltage generator of the kind shown in Figures 8A and 8B; and FIGURE 10 shows a switch driver circuit for use with the generator circuit of Figure 9.
.~ ~
~2~3~ .
Description of the Prior Art Referring to Figure 1, the basic voltage-mode (or voltage-switching) CMOS D/A converter includes a thin-film R/2R ladder network 20 and pairs of n-channel MOS switches generally indicated at 22. Each complemen-tary-driven switch pair consists of a Vref (reference voltage) switch and an A d (analog ground) switch, the "ON" switch being determined by the corresponding input code bit to the converter. The ladder network termina-tion is connected to A nd via a permanently "ON" Agndswitch.
Because of the nature of the R/2R ladder net-work and the fact that switch "ON" resistance (RoN) is finite (i.e. r >0), the RoNIs conventionally are binarily weighted. This is done by weighting the device geometries, of both the Vref and Ag d switshes, in a binary fashion.
3~
Also, it is important that switch pair "ON" resistances match as closely as possible, i.e. ideally:
ONVref ONA d' for a ~iven switch pair Referring now to Figure 2, there is shown a known switch pair arrangement 22A, 22B sometimes emp~loyed when a conventional current-mode D/A converter is used in the voltage mode. Important characteristics of this con-figuration are:
( ) tL)V (L)A (L)- The Vref and Agnd switches are the same size: (Subscript V identifies the Vref switch~
and subscript A identifies the Ag~ld switch.) (b) Both devices occupy the same p-well, which is con-nected to A d.
(c) Both devices have "ON" gate voltages of VDD.
Assuming non-saturated device operation, expres-sions for the "ON" resistances of the switches can be developed from the basic current equation:
IDS = (L~ ~( GS T) VDs ~ VDS ]' Where ~'n = COX ~ = oxt o ~ , ox ~ ~ Effective channel mobility, VT = threshold voltage, W = effective channel width and L = effective channel width 73~
(i) This relationship can be developed for the Vref Switch as follows:
DSv ~ n (L)V [(VGSv Tv) VDSV - ~ VDSv ]
= ~'n (W) [( DD (Vref DSV) VTV) VDSv ~ DSV]
= ~'n (L) DD ref TV DSy DSV
R ~ = ~ n ( - L) [(VDD ~ Vref - VT ) + VDs ]
~ RON = W
(ii) A corresponding relationship can be developed for the Agnd Switch as follows:
IDsA ~ n (L)A [( GSA TA) DSA ~YDSA ]
~ (L) [(VDD ~ VTA) VDS ~ ~VDS 2 ]
RON avDs ~ n (L) [VDD ~ VT ~ VDS ]
A ~n (L) [VDD ~ VT ~ V ]
~4--At the drain of each device, the threshold voltage is given by:
f ! (i) Vref Switch: VT ~ VTo + M[ J Vref 20F ~ ~ 2~F~
, (ii)Agnd Switch: VTA = VTo '~ VDSA + 20F ~ ~F]:
Where the body effect factor, tox ~ ksi q NB
ox J o - and 0F is the Fermi potential.
From the above expressions, it is apparent that in the known switch configuration of Figure 2 there exists an inherent switch RON mismatch (i.e. RON > RON ) due to discrepancies between the VGs, and VDs values of the Vref A~nd devices. The fact that this RON mismatch worsens as Vref increases, results in a restricted reference voltage range for the converter.
On the other hand, the Figure 2 arrangement has the advantages of: (i) Relatively small die area, since all the switches can be contained within one p-well con-nected to Agnd, and (ii) ease of adaptabilit~ to current-mode operation since the configuration is originally de-signed for use in that mode.
Figure 3 shows another known swi-tch pair con-figuration di,rected to achieving RON matching in a D/A
converter designed specifically for use in the voltage mode. This switch pair arrangement 22C, 22D has the following important features:
73~
(a) (LW) > (W) . This (Lw) mismatch is deliberately introduced.
(b) The Vref and Agnd devices occupy separate p-wells.
(c) Both devices have "ON" gate voltages of VDD.
5In this case~ the "ON" resistances expressions are: .
(i) Vref Switch V ~ n (L) ~VDD - Vref - VT + VDs ]
(ii) Agnd Switch:
10RON = , n W
- A ~ (L)A ~VDD T~ DSA]
The drain threshold voltages are.
(i) Vre~ Switch:
TV To M [ r--DSv + 2~F ~ ~2~F]
(ii) Agnd Switch:
VTA VTO M [¦ VDSA ~F ~ ]
~ J~
h,~æ~
Because the V ef devices have individual p-wells, their threshold voltages a.re now lower than the correspond-ing threshold voltages in Figure 2 (due to reduced body effect) and they match theix A d counterparts more closely.
Equating RoN's shows that a (L) mismatch can be deliberately introduced to give a first order compensation for the inherent switch VGs mismatch, at a given value of Vref:
(L-)V A A
(W) VDD - Vref TV D~V
The advantage of this arrangement over that of Figure 2 is an increase in the upper limit of the value of the reference voltage which can be employed. Disadvan-tages include: (i) A relatively large die area, since each Vref switch requires its own separate p-well; and (ii) a reference voltage range restricted to values close to the particular value of Vref which satisfies the above equation.
SUMMARY OF THE INVENTION
In order to optimize the accuracy of a CMOS
converter operated in a voltage mode, it is important that, for a given switch pair, the "ON" resistance of a Vref switch matches that of the corresponding Agnd switch as closely as possible~ The present invention is directed to an arrangement for achieving such a re-sistance match over a relatively wide range of refe~encevoltages. In a preferred embodiment of the invention to be described hereinbelow in detail, this result is obtained by adjusting the gate voltage of the A d switch 3~) in accordance with the value of Vref to give switch VGs equality and therefore "ON" resistance matching over a wide range of reference voltage. This result advanta-geously allows the voltage-mode D/A converter to nave multiplying capability.
DETAILED DESCRIPTION OF PREFERRED
EMBODI~ENTS
Referring now to Figure 4, there is shown a basic CMOS switch pair arrangement 30A, 30B in accordance with this invention. This configuration comprises the following characteristics:
73~
( ) (L)V (L)A (L). The Vref a~d Agnd switches are the same size.
.f. (b) The Vref and Agnd devices occup~ separate p-wells.
(c) The "ON" gate voltage of the A d switch is VDD -Vref/ whereas that of the Vr f switch is VDD.
The relevant RON expressions are:
(i.) Vref Switch:
ON~ ~'n (L) [VDD ~ Vref - VTV VDSV]
(ii) Agnd Switch:
R
ONA ~ n (L) [VDD Vref VTA ~DSA]
The drain threshold voltages are:
(i) Vref Switch:
TV VTO M[ ~ VDSV ~ 20F - r0F]
(ii) Agnd Swi-tch:
yTA VTO [ ~ S~ ~ ~ ]
It will be seen from the above RON expressions that both the Vref and the Agnd switch RoNIs are a function of V
and provide a close match for a wide range of Vref.
f,. .
'73~
g-- .
Figure 5 shows in block format an Agnd switch "ON" gate voltage generator circuit for use with the Fig-ure 4 configuration. The output voltage of this generator circuit provides the positive power supply rail for all the hgnd switch drivers.
Figure 6 is a schematic of a particular circuit, suitable for fabrication on an integrated circuit/ which implements the required gate-voltage function. This VDD -Vref generator circuit provides the positive power supply rail for the Agnd switch driver shown in Figure 7.
The operation of the generator circuit in Figure 6 may be explained as follows:
The input voltage, Vref, is applied to the emi-t-ter follower formed by Ql and Q2. The emitter follower output is Vref - Vbe. ~evices Q3 - Q6 form a double cur-rent mirror which reproduces Vref - Vbe at the source of Q4, thereby setting up a current ~ref ~ Vbe)/R through the resistance R. This current is mirrored b~ devices Q7 - Q9 into an identical resistance R, resulting in a Qll base voltage of VDD ~ Vref ~ Vbe which appears as VDD - Vref at the output of the emitter follower formed by Q10 and Qll. It may particularly be noted that the Vbe term, inevitably introduced by the emitter follower at the output, is compensated by the introduction oE a similar Vbe term by the emitter follower at the input.
.
Figures 8A and 8B show an alternative arrangement for providing Vbe compensation~ This approach uses both a Vre~ and an Agnd switch "ON" gate voltage generator cir-cuit. A particular circuit schematic is given in Figure 9, ~l21;273~
for use with the corresponding switch driver arrangement of ~igure 10.
Some important aspects o~ the basic generator circuit design are:
(~) Because the most significant D/A converter linearity error, due to switch pair RON mismatch, occurs when Vref is a maximum, the Agnd switch "ON" gate voltage generator circuit preferably is designed to be most ac-curate at this particular value. Typically, for a ~DD
of 15V, the VDD - V f generator circuit in Figure 6 can be designed to handle a reference of 10V.
(B) A design trade-off exists in the choice of a value for R in Figure 6. The resistance should be rel-atively large in order to minimize quiescent power supply current, whereas a small value is desirable to decrease the significance of the base current transients during driver switching.
(C) In order that the particular RON equations, given previously, remain valid, it is necessar~7 to ensure the non-saturated operation of the A d switches. The ladder network -termination Ag d switch, with all the Vref swltches "ON", represents the worst case.
The following inequality should be considered:
VGs _~ YT > VDS
DD reE VTA VDsA
This means that IDS must be sufficiently small so ~ max.
that:
A Imax DD Vref - VT ~I
One method of ensuring that this inequality remains true is to select a sufficiently large value of R in the R/2R ladder network. The problem does not arise ~2~730 in the case of the V ef switches, where the correspond-ing inequality ls independent of VDS:
`` ..
V DSV
=> VDD - (V f ~ VDS ) - V > DSV
VDD Vref Tv DSv DSv Vref¦max (VDD VTV~ Imin Although several preferred embodiments of the invention have been disclosed herein in detail, it is to be understood that this is for the purpose of illustrat-ing the invention, and should not be construed as neces-sarily limiting the scope of the invention, since it is apparent that many changes can be made by those skilled in the art while still practicing the invention claimed herein.
EXTENDED REFERENCE RANGE, VOLTAGE-MODE
CMOS D/A CONVERTER
BACKGROUND OF THE INVENTION
Field of the Invention . .
This invention relates to digital-to-analog (D/A) converters. More particularly, this invention relates to D/A converters using complementary-driven CMOS switches to produce a voltage-mode output signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 shows basic elements of a conventional CMOS D/A converter;
FIGURE 2 shows a known switch pair configura-tion fox adapting a conventional current-mode converter to voltage-mode operation;
FIGURE 3 shows a known switch-pair configuration for use in a voltage--mode D/A converter, and providing "ON" resistance match at one value of reference voltage;
FIGURE 4 shows a switch-pair configuration in accordance with the invention;
FIGURE 5 is a block diagxam of a gate-voltage generator for the Agn~ switch of Figure 4;
FIGURE 6 illustrates one gate-voltage generator circuit suitable for fabrication on an integrated circuit;
FIGURE 7 shows a switch-driver circuit;
FIGURES 8A and 8B are block diagrams illustrat-ing an alternative gate-voltage generator;
FIGURE 9 shows one circuit schematic for a gate-voltage generator of the kind shown in Figures 8A and 8B; and FIGURE 10 shows a switch driver circuit for use with the generator circuit of Figure 9.
.~ ~
~2~3~ .
Description of the Prior Art Referring to Figure 1, the basic voltage-mode (or voltage-switching) CMOS D/A converter includes a thin-film R/2R ladder network 20 and pairs of n-channel MOS switches generally indicated at 22. Each complemen-tary-driven switch pair consists of a Vref (reference voltage) switch and an A d (analog ground) switch, the "ON" switch being determined by the corresponding input code bit to the converter. The ladder network termina-tion is connected to A nd via a permanently "ON" Agndswitch.
Because of the nature of the R/2R ladder net-work and the fact that switch "ON" resistance (RoN) is finite (i.e. r >0), the RoNIs conventionally are binarily weighted. This is done by weighting the device geometries, of both the Vref and Ag d switshes, in a binary fashion.
3~
Also, it is important that switch pair "ON" resistances match as closely as possible, i.e. ideally:
ONVref ONA d' for a ~iven switch pair Referring now to Figure 2, there is shown a known switch pair arrangement 22A, 22B sometimes emp~loyed when a conventional current-mode D/A converter is used in the voltage mode. Important characteristics of this con-figuration are:
( ) tL)V (L)A (L)- The Vref and Agnd switches are the same size: (Subscript V identifies the Vref switch~
and subscript A identifies the Ag~ld switch.) (b) Both devices occupy the same p-well, which is con-nected to A d.
(c) Both devices have "ON" gate voltages of VDD.
Assuming non-saturated device operation, expres-sions for the "ON" resistances of the switches can be developed from the basic current equation:
IDS = (L~ ~( GS T) VDs ~ VDS ]' Where ~'n = COX ~ = oxt o ~ , ox ~ ~ Effective channel mobility, VT = threshold voltage, W = effective channel width and L = effective channel width 73~
(i) This relationship can be developed for the Vref Switch as follows:
DSv ~ n (L)V [(VGSv Tv) VDSV - ~ VDSv ]
= ~'n (W) [( DD (Vref DSV) VTV) VDSv ~ DSV]
= ~'n (L) DD ref TV DSy DSV
R ~ = ~ n ( - L) [(VDD ~ Vref - VT ) + VDs ]
~ RON = W
(ii) A corresponding relationship can be developed for the Agnd Switch as follows:
IDsA ~ n (L)A [( GSA TA) DSA ~YDSA ]
~ (L) [(VDD ~ VTA) VDS ~ ~VDS 2 ]
RON avDs ~ n (L) [VDD ~ VT ~ VDS ]
A ~n (L) [VDD ~ VT ~ V ]
~4--At the drain of each device, the threshold voltage is given by:
f ! (i) Vref Switch: VT ~ VTo + M[ J Vref 20F ~ ~ 2~F~
, (ii)Agnd Switch: VTA = VTo '~ VDSA + 20F ~ ~F]:
Where the body effect factor, tox ~ ksi q NB
ox J o - and 0F is the Fermi potential.
From the above expressions, it is apparent that in the known switch configuration of Figure 2 there exists an inherent switch RON mismatch (i.e. RON > RON ) due to discrepancies between the VGs, and VDs values of the Vref A~nd devices. The fact that this RON mismatch worsens as Vref increases, results in a restricted reference voltage range for the converter.
On the other hand, the Figure 2 arrangement has the advantages of: (i) Relatively small die area, since all the switches can be contained within one p-well con-nected to Agnd, and (ii) ease of adaptabilit~ to current-mode operation since the configuration is originally de-signed for use in that mode.
Figure 3 shows another known swi-tch pair con-figuration di,rected to achieving RON matching in a D/A
converter designed specifically for use in the voltage mode. This switch pair arrangement 22C, 22D has the following important features:
73~
(a) (LW) > (W) . This (Lw) mismatch is deliberately introduced.
(b) The Vref and Agnd devices occupy separate p-wells.
(c) Both devices have "ON" gate voltages of VDD.
5In this case~ the "ON" resistances expressions are: .
(i) Vref Switch V ~ n (L) ~VDD - Vref - VT + VDs ]
(ii) Agnd Switch:
10RON = , n W
- A ~ (L)A ~VDD T~ DSA]
The drain threshold voltages are.
(i) Vre~ Switch:
TV To M [ r--DSv + 2~F ~ ~2~F]
(ii) Agnd Switch:
VTA VTO M [¦ VDSA ~F ~ ]
~ J~
h,~æ~
Because the V ef devices have individual p-wells, their threshold voltages a.re now lower than the correspond-ing threshold voltages in Figure 2 (due to reduced body effect) and they match theix A d counterparts more closely.
Equating RoN's shows that a (L) mismatch can be deliberately introduced to give a first order compensation for the inherent switch VGs mismatch, at a given value of Vref:
(L-)V A A
(W) VDD - Vref TV D~V
The advantage of this arrangement over that of Figure 2 is an increase in the upper limit of the value of the reference voltage which can be employed. Disadvan-tages include: (i) A relatively large die area, since each Vref switch requires its own separate p-well; and (ii) a reference voltage range restricted to values close to the particular value of Vref which satisfies the above equation.
SUMMARY OF THE INVENTION
In order to optimize the accuracy of a CMOS
converter operated in a voltage mode, it is important that, for a given switch pair, the "ON" resistance of a Vref switch matches that of the corresponding Agnd switch as closely as possible~ The present invention is directed to an arrangement for achieving such a re-sistance match over a relatively wide range of refe~encevoltages. In a preferred embodiment of the invention to be described hereinbelow in detail, this result is obtained by adjusting the gate voltage of the A d switch 3~) in accordance with the value of Vref to give switch VGs equality and therefore "ON" resistance matching over a wide range of reference voltage. This result advanta-geously allows the voltage-mode D/A converter to nave multiplying capability.
DETAILED DESCRIPTION OF PREFERRED
EMBODI~ENTS
Referring now to Figure 4, there is shown a basic CMOS switch pair arrangement 30A, 30B in accordance with this invention. This configuration comprises the following characteristics:
73~
( ) (L)V (L)A (L). The Vref a~d Agnd switches are the same size.
.f. (b) The Vref and Agnd devices occup~ separate p-wells.
(c) The "ON" gate voltage of the A d switch is VDD -Vref/ whereas that of the Vr f switch is VDD.
The relevant RON expressions are:
(i.) Vref Switch:
ON~ ~'n (L) [VDD ~ Vref - VTV VDSV]
(ii) Agnd Switch:
R
ONA ~ n (L) [VDD Vref VTA ~DSA]
The drain threshold voltages are:
(i) Vref Switch:
TV VTO M[ ~ VDSV ~ 20F - r0F]
(ii) Agnd Swi-tch:
yTA VTO [ ~ S~ ~ ~ ]
It will be seen from the above RON expressions that both the Vref and the Agnd switch RoNIs are a function of V
and provide a close match for a wide range of Vref.
f,. .
'73~
g-- .
Figure 5 shows in block format an Agnd switch "ON" gate voltage generator circuit for use with the Fig-ure 4 configuration. The output voltage of this generator circuit provides the positive power supply rail for all the hgnd switch drivers.
Figure 6 is a schematic of a particular circuit, suitable for fabrication on an integrated circuit/ which implements the required gate-voltage function. This VDD -Vref generator circuit provides the positive power supply rail for the Agnd switch driver shown in Figure 7.
The operation of the generator circuit in Figure 6 may be explained as follows:
The input voltage, Vref, is applied to the emi-t-ter follower formed by Ql and Q2. The emitter follower output is Vref - Vbe. ~evices Q3 - Q6 form a double cur-rent mirror which reproduces Vref - Vbe at the source of Q4, thereby setting up a current ~ref ~ Vbe)/R through the resistance R. This current is mirrored b~ devices Q7 - Q9 into an identical resistance R, resulting in a Qll base voltage of VDD ~ Vref ~ Vbe which appears as VDD - Vref at the output of the emitter follower formed by Q10 and Qll. It may particularly be noted that the Vbe term, inevitably introduced by the emitter follower at the output, is compensated by the introduction oE a similar Vbe term by the emitter follower at the input.
.
Figures 8A and 8B show an alternative arrangement for providing Vbe compensation~ This approach uses both a Vre~ and an Agnd switch "ON" gate voltage generator cir-cuit. A particular circuit schematic is given in Figure 9, ~l21;273~
for use with the corresponding switch driver arrangement of ~igure 10.
Some important aspects o~ the basic generator circuit design are:
(~) Because the most significant D/A converter linearity error, due to switch pair RON mismatch, occurs when Vref is a maximum, the Agnd switch "ON" gate voltage generator circuit preferably is designed to be most ac-curate at this particular value. Typically, for a ~DD
of 15V, the VDD - V f generator circuit in Figure 6 can be designed to handle a reference of 10V.
(B) A design trade-off exists in the choice of a value for R in Figure 6. The resistance should be rel-atively large in order to minimize quiescent power supply current, whereas a small value is desirable to decrease the significance of the base current transients during driver switching.
(C) In order that the particular RON equations, given previously, remain valid, it is necessar~7 to ensure the non-saturated operation of the A d switches. The ladder network -termination Ag d switch, with all the Vref swltches "ON", represents the worst case.
The following inequality should be considered:
VGs _~ YT > VDS
DD reE VTA VDsA
This means that IDS must be sufficiently small so ~ max.
that:
A Imax DD Vref - VT ~I
One method of ensuring that this inequality remains true is to select a sufficiently large value of R in the R/2R ladder network. The problem does not arise ~2~730 in the case of the V ef switches, where the correspond-ing inequality ls independent of VDS:
`` ..
V DSV
=> VDD - (V f ~ VDS ) - V > DSV
VDD Vref Tv DSv DSv Vref¦max (VDD VTV~ Imin Although several preferred embodiments of the invention have been disclosed herein in detail, it is to be understood that this is for the purpose of illustrat-ing the invention, and should not be construed as neces-sarily limiting the scope of the invention, since it is apparent that many changes can be made by those skilled in the art while still practicing the invention claimed herein.
Claims (8)
1. In a digital-to-analog converter of the type comprising a plurality of complementary-driven CMOS switch pairs for Vref and Agnd respectively;
that improvement for assuring a close match between the "ON" resistances of the switch pairs over an extended range of values of Vref, comprising:
a gate-voltage generator having means producing an Agnd switch gate voltage which varies with changes in Vref.
that improvement for assuring a close match between the "ON" resistances of the switch pairs over an extended range of values of Vref, comprising:
a gate-voltage generator having means producing an Agnd switch gate voltage which varies with changes in Vref.
2. Apparatus as in claim 1, wherein said generator produces a voltage corresponding to VDD-Vref, where VDD
is the supply voltage.
is the supply voltage.
3. Apparatus as in claim 2, wherein said generator includes an output circuit having a transistor introducing a Vbe component in the output signal; and a compensation circuit for said generator in-cluding a second transistor applying to said first tran-sistor an input signal having a Vbe component cancelling the effect of said first Vbe component on the generated gate voltage.
4. Apparatus as in claim 1, wherein said generator includes circuits to develop both Vref and Agnd switch gate voltages;
said circuits including transistor means intro-ducing corresponding Vbe factors in both of said gate voltages so as to avoid Vbe effects.
said circuits including transistor means intro-ducing corresponding Vbe factors in both of said gate voltages so as to avoid Vbe effects.
5. Apparatus as in Claim 1, wherein the Vref and Agnd switches of each pair have identical W/L ratios.
6. Apparatus as in Claim 5, wherein the Vref and Agnd switches of each pair are of the same size.
7. Apparatus as in Claim 6, wherein the Vref and Agnd switches occupy separate p-wells.
8. Apparatus as in Claim 7, wherein the "ON"
gate voltage of the Agnd switch is VDD - Vref, and the "ON" gate voltage of the Vref switch is VDD.
gate voltage of the Agnd switch is VDD - Vref, and the "ON" gate voltage of the Vref switch is VDD.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/465,493 US4558242A (en) | 1983-02-11 | 1983-02-11 | Extended reference range, voltage-mode CMOS D/A converter |
| US465,493 | 1983-02-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1212730A true CA1212730A (en) | 1986-10-14 |
Family
ID=23848041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000445397A Expired CA1212730A (en) | 1983-02-11 | 1984-01-16 | Extended reference range, voltage-mode cmos d/a converter |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4558242A (en) |
| JP (1) | JPH0656957B2 (en) |
| CA (1) | CA1212730A (en) |
| DE (1) | DE3404652A1 (en) |
| FR (1) | FR2541059B1 (en) |
| GB (1) | GB2135545B (en) |
| NL (1) | NL8400444A (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1190325B (en) * | 1986-04-18 | 1988-02-16 | Sgs Microelettronica Spa | POLARIZATION CIRCUIT FOR DEVICES INTEGRATED IN MOS TECHNOLOGY, PARTICULARLY OF THE MIXED DIGITAL-ANALOG TYPE |
| US4800365A (en) * | 1987-06-15 | 1989-01-24 | Burr-Brown Corporation | CMOS digital-to-analog converter circuitry |
| US5008671A (en) * | 1988-06-27 | 1991-04-16 | Analog Devices, Incorporated | High-speed digital-to-analog converter with BiMOS cell structure |
| US4881512A (en) * | 1988-08-31 | 1989-11-21 | General Motors Corporation | Internal combustion engine ignition system |
| JPH02268524A (en) * | 1989-04-11 | 1990-11-02 | Seiko Epson Corp | Digital/analog converter |
| US5075677A (en) * | 1989-07-27 | 1991-12-24 | Analog Devices, Inc. | Voltage-switching d/a converter using p- and n-channel MOSFETs |
| US5017919A (en) * | 1990-06-06 | 1991-05-21 | Western Digital Corporation | Digital-to-analog converter with bit weight segmented arrays |
| US5994755A (en) * | 1991-10-30 | 1999-11-30 | Intersil Corporation | Analog-to-digital converter and method of fabrication |
| US5369309A (en) * | 1991-10-30 | 1994-11-29 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| US5258757A (en) * | 1992-05-08 | 1993-11-02 | Analog Devices, Incorporated | Apparatus and method for increasing the output impedance of a current-type digital-to-analog converter |
| US5489904A (en) * | 1993-09-28 | 1996-02-06 | The Regents Of The University Of California | Analog current mode analog/digital converter |
| US6118261A (en) * | 1993-11-08 | 2000-09-12 | International Business Machines Corp. | Slew rate control circuit |
| US5675278A (en) * | 1994-02-09 | 1997-10-07 | Texas Instruments Incorporated/Hiji High-Tech Co., Ltd. | Level shifting circuit |
| JP3436971B2 (en) * | 1994-06-03 | 2003-08-18 | 三菱電機株式会社 | Voltage controlled current source and bias generation circuit using the same |
| FR2732129B1 (en) * | 1995-03-22 | 1997-06-20 | Suisse Electronique Microtech | REFERENCE CURRENT GENERATOR IN CMOS TECHNOLOGY |
| US5764174A (en) * | 1996-05-14 | 1998-06-09 | Analog Devices, Inc. | Switch architecture for R/2R digital to analog converters |
| US5969657A (en) * | 1997-07-22 | 1999-10-19 | Analog Devices, Inc. | Digital to analog converter |
| US6208278B1 (en) * | 1999-05-07 | 2001-03-27 | Infineon Technologies North America Corp. | System and method for logarithmic digital to analog conversion |
| US6150971A (en) * | 1999-06-22 | 2000-11-21 | Burr-Brown Corporation | R/2R' ladder switch circuit and method for digital-to-analog converter |
| JP3450257B2 (en) | 2000-02-28 | 2003-09-22 | Ｎｅｃ化合物デバイス株式会社 | Active bias circuit |
| US6414616B1 (en) | 2000-06-22 | 2002-07-02 | Analog Devices, Inc. | Architecture for voltage scaling DAC |
| US7884747B2 (en) * | 2009-06-12 | 2011-02-08 | Analog Devices, Inc. | Digital to analog converters having circuit architectures to overcome switch losses |
| US10574247B1 (en) | 2018-09-14 | 2020-02-25 | Analog Devices Global Unlimited Company | Digital-to-analog converter transfer function modification |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2851789C2 (en) * | 1978-11-30 | 1981-10-01 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Circuit for switching and transmitting alternating voltages |
| JPS55156422A (en) * | 1979-05-25 | 1980-12-05 | Nec Corp | Digital-analog converter |
| GB2054996B (en) * | 1979-07-20 | 1983-06-08 | Philips Electronic Associated | D/a converter mos ic |
| JPS5647128A (en) * | 1979-09-26 | 1981-04-28 | Matsushita Electric Ind Co Ltd | Switch circuit |
| US4308467A (en) * | 1979-11-02 | 1981-12-29 | Raytheon Company | Electronic circuitry |
| US4338590A (en) * | 1980-01-07 | 1982-07-06 | National Semiconductor Corporation | Multi stage resistive ladder network having extra stages for trimming |
| US4267550A (en) * | 1980-01-25 | 1981-05-12 | National Semiconductor Corporation | Digital to analog conversion circuit including compensation FET'S |
| US4410880A (en) * | 1981-03-25 | 1983-10-18 | Sperry Corporation | Digital-to-analog converter and analog-to-digital converter with controllable bi-polar and uni-polar capability |
| US4464588A (en) * | 1982-04-01 | 1984-08-07 | National Semiconductor Corporation | Temperature stable CMOS voltage reference |
| US4495425A (en) * | 1982-06-24 | 1985-01-22 | Motorola, Inc. | VBE Voltage reference circuit |
-
1983
- 1983-02-11 US US06/465,493 patent/US4558242A/en not_active Expired - Lifetime
-
1984
- 1984-01-16 CA CA000445397A patent/CA1212730A/en not_active Expired
- 1984-01-18 GB GB08401269A patent/GB2135545B/en not_active Expired
- 1984-02-10 DE DE19843404652 patent/DE3404652A1/en active Granted
- 1984-02-10 NL NL8400444A patent/NL8400444A/en not_active Application Discontinuation
- 1984-02-10 FR FR8402108A patent/FR2541059B1/en not_active Expired
- 1984-02-13 JP JP59023033A patent/JPH0656957B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2541059B1 (en) | 1988-07-08 |
| JPS59214321A (en) | 1984-12-04 |
| GB2135545A (en) | 1984-08-30 |
| DE3404652C2 (en) | 1992-12-03 |
| DE3404652A1 (en) | 1984-08-16 |
| FR2541059A1 (en) | 1984-08-17 |
| GB2135545B (en) | 1986-06-11 |
| NL8400444A (en) | 1984-09-03 |
| JPH0656957B2 (en) | 1994-07-27 |
| US4558242A (en) | 1985-12-10 |
| GB8401269D0 (en) | 1984-02-22 |
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