CA1212485A - Integrated semiconductor circuits with bipolar components and method of producing same - Google Patents
Integrated semiconductor circuits with bipolar components and method of producing sameInfo
- Publication number
- CA1212485A CA1212485A CA000434348A CA434348A CA1212485A CA 1212485 A CA1212485 A CA 1212485A CA 000434348 A CA000434348 A CA 000434348A CA 434348 A CA434348 A CA 434348A CA 1212485 A CA1212485 A CA 1212485A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- bipolar transistor
- silicide
- contact
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
Abstract
ABSTRACT OF THE DISCLOSURE
Integrated semiconductor circuits with bipolar components preferably with at least one bipolar transistor and at least two Schottky diodes having different threshold voltages are disclosed along with a method of producing such circuits. The contact from a metal interconnect level to diffused active regions of the circuits comprises a directly deposited silicide of a high melting point metal such as tantalum tungsten molybdenum or titanium. In addition to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides enables its simultaneous use as an implantation mask. The invention allows the production of bipolar integrated circuits in VLSI technology.
Integrated semiconductor circuits with bipolar components preferably with at least one bipolar transistor and at least two Schottky diodes having different threshold voltages are disclosed along with a method of producing such circuits. The contact from a metal interconnect level to diffused active regions of the circuits comprises a directly deposited silicide of a high melting point metal such as tantalum tungsten molybdenum or titanium. In addition to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides enables its simultaneous use as an implantation mask. The invention allows the production of bipolar integrated circuits in VLSI technology.
Description
BACKGROUND OF TIE INVENTION
Field of the Involution The involution relates to integrated semiconductor circuits and somewhat more particularly -to integrated semiconductor circuits having at least bipolar components wherein the contacts from a metal intercolmect level to diffuse active regions of the circuit occur over additionally generated interconnects. The invention also relates to integrated semi-conductor circuits having at least bipolar component and at least two Skeptic diodes which are generated next to one another a-t locations of a surface of a semiconductor substrate having tile same conductivity -type, such that a first Skeptic diode has a lower threshold voltage than a second Skeptic diode. The invention also relates to a method of product in -these types of circuits.
Prior Art The smallest possible dimensions of bipolar transistors are determined by the relatively coarse metallization grid utilized, because contacts, bottle to the emitter and collector zones, as well as to a base zone, must be produced from a metal interconl1ec-t level.
TllCI`C h;lVC been Lowe nt-tel~ is to alleviate -the wiriilg or inter-I coy cat problem by lulls of, for example, Utilizing a polysilicon wiring, as described in an article by D. D. Tang e-t at appearing in IEEE Trays-Achilles Old Electoral Devices, Vol. ED-27 No. 8 (August 1980) pages 1379-1384 or by utilizing a pulsed wiring, as described in an article by Y. Suzuki et at appearing in IEEE Transactions On Electron Devices, Vol.
ED-27, No. 8, (August 1980) pages 1385-1389. however, polysilicon inter-connects are relatively high-resistant and result in high intermediate resistances. Since the emitter is generally diffused out of the polysilicon fly in this procedure and because the n and p do pants diffuse into one another, a high emitter/base capacitance also occurs and vitiates the limiting frequency. The use of a wiring composed of molybdenum solaced, as suggested in the earlier referenced Suzuki et at article, does indeed considerably reduce the wiring nests-lance in comparison to that of a polysilicon wiring; however, the process of producing this type of wiring is very mask-intensive.
SUMMARY OF THE INVENTION
The invention provides integrated semiconductor circuits with at least bipolar components, preferably bipolar transistors, wherein contacting and connection of base, emitter and collector regions is independent of a metallization grid, i.e. requires rota-lively little space, and therefore allows a high packing density.
Further, with the inventive circuits, sheet resistance of the dip-fused regions is reduced.
The invention also provides a process for producing air-cults of the initially referenced type, with a combination of method steps which are as simple and mask-saving as possible.
In accordance with the principles of -the invention, add-I tonal interconnects are comprised of a directly deposited sift-aide of a hump (high melting point) metal, such as tantalum, lung-steno molybdenum or titanium. In certain embodiments of the invent lion, integrated semiconductor circuits having at least one bipolar -transistor and at least two Skeptic diodes are provided, wherein the Skeptic diodes are generated spaced and next to one another at locations of the surface of a semiconductor crystal having the same conductivity type, such that a first Skeptic diode exhibits a lower threshold voltage -than a second Skeptic diode, with -the emitter and collector contact of the bipolar transistor and -the contact of the first Skeptic diode being composed of a solaced of a high melting point metal selected from the group consisting of tantalum, tungsten, molybdenum and titanium while the base con-tact of the bipolar transistor as well as -the contact of the second pa .
I
Skeptic diode are composed of aluminum or a layer sequence consisting of platinum silicide/aluminum.
In addition to the independence from a metalliza-tion grid and the low-resistance of the additional spiring thereby achieved, the utilization (only partial) of solaced wiring in conjunction with the high temperature stability of the silicides, enables its simultaneous use as an implantation mask. As a result, the advantages of an additional wiring can be exploited without exertion of additional photo-lithographic steps since the base contact mask can also be eliminated.
IYith the invelltioll) one can simultaneously utilize the metal solaced, because of its low barrier height, for the second Skeptic diode, as may be requireLI in some applications see German Patent 25 2-1 579), in addition to -the more standard aluminum or aluminum/platinum solaced Squatly diode.
The involution is particularly suitable for producing bipolar integrated circuits in VLSI technology.
BRIM EN DESCRY I PUT ION OF To if Dryly INS
FIGURES 1-3 are partial, elevated, cross-sectional, schematic views of a semicollcluctor chip unclergoillg processing in accordance with the pi sulks of toll VC~IItiOII.
I DISCRIPr`ION 01 I~EFEI~RED El~lB~DI~lENrrS
The invention will be further described by setting forth a process sequence for production of an inventive circuit with a bipolar transistor end two types of Skeptic diodes.
In this description, only the process steps considered essential for an understanding of the invention are illustrated in the drawings, with the same referrals numerals being utilized throughout for identical parts or components.
US
Active regions of a desired circuit are defined by producing n -doped zones 2 with masked ion implantation on a monocrystalline, p-doped, (oriented silicon substrate wafer 1 having a specific resistance in the range of about 10 ohm cm. A n -doped silicon layer 3 having a specie lie resistance in the range of about 2 ohm cm is then applied on the n+
-doped zones 2 by an epitaxial deposition technique and an insulation trough or well (not illustrated in the Figure) is etched by use of a mask covering the active regions 2. Subsequently, an insulating oxide 4 is generated in the region of the insulation trough. After application of a layer masking the remaining regiorls, a n+ -deep diffusiorl 5 in a collector region of -the bipolar transistor is produced and after removal of the mask for the deep diffusion collector 5 and after application of another mask, a base implantation 6, with p-doping ions, preferably boron ions, is executed.
Next, a photo-lithographic process is carried out for defining the emitter ones 8, during which an oxide layer 7 generated on -the base zone 6 is removed in area for the emitter region. The emitter zone 8 is then gelleratecl by impl.llltntioll allot diffusioll o-f, for example, arsenic ions.
I Isle plloto-litllographic process is utilized to define a contact for a first Skeptic diode 18 (best seen in FIGURE 3) as well as the contacts for emitter 8 and collector zones 2, 5 and the oxide layer 7 is removed in these regions. Next, a metal solaced layer 10, in an exemplary embodiment preferably composed of tantalum solaced, is then applied surface-wide in a layer thickness in the range of about 200 no and is structured such that it functions as an additional interconnect in the region of the bipolar transistor 17 (best seen in FIGURE I and also functions as an implantation mask in the region of the bipolar transistor 17, during a subsequent base contact implantation 11. The Skeptic diode region, 18 and/or 19 is covered with a photosensitive resist layer 13 before wldertaking the base contact implantation 11 with boron ions 12.
After removal of the photosensitive resist layer 13, an amlealillg process is executed whereby the structured solaced layer 10 is crystallized while the implanted ions are simultaneously electrically activated. After deposition of an insulation layer 14, functioning as intermediate oxide, contact hole regions for the base contact 9 of -the bipolar transistor 17 and the contact 20 of a second Skeptic diode 19 are etched free and the metallizatioll all structuring of an outer metal interconnect layer 15, 16 is carried out in a knoll mauler. This outer metal interconnect layer can be composed of aluminum or be composed of a double layer consisting of a layer sequence comprised of platinum solaced 15/aluminum 16.
The beeper transistor area in FIGURE 3 is identified by bracket 17, the first Skeptic diode with pa to alum solaced con-tact is identified ilk bracket lo all a second Skeptic diode with a platinum solaced/
allele l colltnct it klelltifiecll~itll bracket 19.
The solaced layer 10 can be composed of hump metals selected from the group consisting of -titanium, molybdenum, tungsten and, of course, tantalum.
in all e~elllplary em~odimellt, the first Skeptic diode 18 exhibited a -threshold voltage of 0.59 volts and a second Skeptic diode 19 exhibited a threshold voltage of 0.8~ volts.
As is apparent from the foregoing specification, the present invention is susceptible of being embodied with various alterations and modifications which may differ particularly from those that have 'noon described in the preceding ~2~8S
specification and description. or this reason, it is to be fully under-stood that all of the foregoing is intended to be merely illustrative and is not to be construed or interpreted as being restrictive or otherwise limiting of the present invention, excepting as it is sex forth and defined in the hereto-appended claims.
Field of the Involution The involution relates to integrated semiconductor circuits and somewhat more particularly -to integrated semiconductor circuits having at least bipolar components wherein the contacts from a metal intercolmect level to diffuse active regions of the circuit occur over additionally generated interconnects. The invention also relates to integrated semi-conductor circuits having at least bipolar component and at least two Skeptic diodes which are generated next to one another a-t locations of a surface of a semiconductor substrate having tile same conductivity -type, such that a first Skeptic diode has a lower threshold voltage than a second Skeptic diode. The invention also relates to a method of product in -these types of circuits.
Prior Art The smallest possible dimensions of bipolar transistors are determined by the relatively coarse metallization grid utilized, because contacts, bottle to the emitter and collector zones, as well as to a base zone, must be produced from a metal interconl1ec-t level.
TllCI`C h;lVC been Lowe nt-tel~ is to alleviate -the wiriilg or inter-I coy cat problem by lulls of, for example, Utilizing a polysilicon wiring, as described in an article by D. D. Tang e-t at appearing in IEEE Trays-Achilles Old Electoral Devices, Vol. ED-27 No. 8 (August 1980) pages 1379-1384 or by utilizing a pulsed wiring, as described in an article by Y. Suzuki et at appearing in IEEE Transactions On Electron Devices, Vol.
ED-27, No. 8, (August 1980) pages 1385-1389. however, polysilicon inter-connects are relatively high-resistant and result in high intermediate resistances. Since the emitter is generally diffused out of the polysilicon fly in this procedure and because the n and p do pants diffuse into one another, a high emitter/base capacitance also occurs and vitiates the limiting frequency. The use of a wiring composed of molybdenum solaced, as suggested in the earlier referenced Suzuki et at article, does indeed considerably reduce the wiring nests-lance in comparison to that of a polysilicon wiring; however, the process of producing this type of wiring is very mask-intensive.
SUMMARY OF THE INVENTION
The invention provides integrated semiconductor circuits with at least bipolar components, preferably bipolar transistors, wherein contacting and connection of base, emitter and collector regions is independent of a metallization grid, i.e. requires rota-lively little space, and therefore allows a high packing density.
Further, with the inventive circuits, sheet resistance of the dip-fused regions is reduced.
The invention also provides a process for producing air-cults of the initially referenced type, with a combination of method steps which are as simple and mask-saving as possible.
In accordance with the principles of -the invention, add-I tonal interconnects are comprised of a directly deposited sift-aide of a hump (high melting point) metal, such as tantalum, lung-steno molybdenum or titanium. In certain embodiments of the invent lion, integrated semiconductor circuits having at least one bipolar -transistor and at least two Skeptic diodes are provided, wherein the Skeptic diodes are generated spaced and next to one another at locations of the surface of a semiconductor crystal having the same conductivity type, such that a first Skeptic diode exhibits a lower threshold voltage -than a second Skeptic diode, with -the emitter and collector contact of the bipolar transistor and -the contact of the first Skeptic diode being composed of a solaced of a high melting point metal selected from the group consisting of tantalum, tungsten, molybdenum and titanium while the base con-tact of the bipolar transistor as well as -the contact of the second pa .
I
Skeptic diode are composed of aluminum or a layer sequence consisting of platinum silicide/aluminum.
In addition to the independence from a metalliza-tion grid and the low-resistance of the additional spiring thereby achieved, the utilization (only partial) of solaced wiring in conjunction with the high temperature stability of the silicides, enables its simultaneous use as an implantation mask. As a result, the advantages of an additional wiring can be exploited without exertion of additional photo-lithographic steps since the base contact mask can also be eliminated.
IYith the invelltioll) one can simultaneously utilize the metal solaced, because of its low barrier height, for the second Skeptic diode, as may be requireLI in some applications see German Patent 25 2-1 579), in addition to -the more standard aluminum or aluminum/platinum solaced Squatly diode.
The involution is particularly suitable for producing bipolar integrated circuits in VLSI technology.
BRIM EN DESCRY I PUT ION OF To if Dryly INS
FIGURES 1-3 are partial, elevated, cross-sectional, schematic views of a semicollcluctor chip unclergoillg processing in accordance with the pi sulks of toll VC~IItiOII.
I DISCRIPr`ION 01 I~EFEI~RED El~lB~DI~lENrrS
The invention will be further described by setting forth a process sequence for production of an inventive circuit with a bipolar transistor end two types of Skeptic diodes.
In this description, only the process steps considered essential for an understanding of the invention are illustrated in the drawings, with the same referrals numerals being utilized throughout for identical parts or components.
US
Active regions of a desired circuit are defined by producing n -doped zones 2 with masked ion implantation on a monocrystalline, p-doped, (oriented silicon substrate wafer 1 having a specific resistance in the range of about 10 ohm cm. A n -doped silicon layer 3 having a specie lie resistance in the range of about 2 ohm cm is then applied on the n+
-doped zones 2 by an epitaxial deposition technique and an insulation trough or well (not illustrated in the Figure) is etched by use of a mask covering the active regions 2. Subsequently, an insulating oxide 4 is generated in the region of the insulation trough. After application of a layer masking the remaining regiorls, a n+ -deep diffusiorl 5 in a collector region of -the bipolar transistor is produced and after removal of the mask for the deep diffusion collector 5 and after application of another mask, a base implantation 6, with p-doping ions, preferably boron ions, is executed.
Next, a photo-lithographic process is carried out for defining the emitter ones 8, during which an oxide layer 7 generated on -the base zone 6 is removed in area for the emitter region. The emitter zone 8 is then gelleratecl by impl.llltntioll allot diffusioll o-f, for example, arsenic ions.
I Isle plloto-litllographic process is utilized to define a contact for a first Skeptic diode 18 (best seen in FIGURE 3) as well as the contacts for emitter 8 and collector zones 2, 5 and the oxide layer 7 is removed in these regions. Next, a metal solaced layer 10, in an exemplary embodiment preferably composed of tantalum solaced, is then applied surface-wide in a layer thickness in the range of about 200 no and is structured such that it functions as an additional interconnect in the region of the bipolar transistor 17 (best seen in FIGURE I and also functions as an implantation mask in the region of the bipolar transistor 17, during a subsequent base contact implantation 11. The Skeptic diode region, 18 and/or 19 is covered with a photosensitive resist layer 13 before wldertaking the base contact implantation 11 with boron ions 12.
After removal of the photosensitive resist layer 13, an amlealillg process is executed whereby the structured solaced layer 10 is crystallized while the implanted ions are simultaneously electrically activated. After deposition of an insulation layer 14, functioning as intermediate oxide, contact hole regions for the base contact 9 of -the bipolar transistor 17 and the contact 20 of a second Skeptic diode 19 are etched free and the metallizatioll all structuring of an outer metal interconnect layer 15, 16 is carried out in a knoll mauler. This outer metal interconnect layer can be composed of aluminum or be composed of a double layer consisting of a layer sequence comprised of platinum solaced 15/aluminum 16.
The beeper transistor area in FIGURE 3 is identified by bracket 17, the first Skeptic diode with pa to alum solaced con-tact is identified ilk bracket lo all a second Skeptic diode with a platinum solaced/
allele l colltnct it klelltifiecll~itll bracket 19.
The solaced layer 10 can be composed of hump metals selected from the group consisting of -titanium, molybdenum, tungsten and, of course, tantalum.
in all e~elllplary em~odimellt, the first Skeptic diode 18 exhibited a -threshold voltage of 0.59 volts and a second Skeptic diode 19 exhibited a threshold voltage of 0.8~ volts.
As is apparent from the foregoing specification, the present invention is susceptible of being embodied with various alterations and modifications which may differ particularly from those that have 'noon described in the preceding ~2~8S
specification and description. or this reason, it is to be fully under-stood that all of the foregoing is intended to be merely illustrative and is not to be construed or interpreted as being restrictive or otherwise limiting of the present invention, excepting as it is sex forth and defined in the hereto-appended claims.
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In an integrated semiconductor circuit with at least one bipolar transistor and at least two Schottky diodes wherein the Schottky diodes are generated spaced and next to one another at locations of a surface of a semiconductor crystal having the same conductivity type, such that a first Schottky diode exhibits a lower threshold voltage than a second Schottky diode, wherein the improvement comprises:
in that the emitter and collector contacts of the bipolar tran-sistor as well as the contact of the first Schottky diode are part of an interconnect level generated in addition to a conventional aluminum based interconnect system and consist of a silicide of a high melting point metal selected from the group consisting of tantalum, tungsten, molybdenum and titanium, and the base contact of the bipolar transistor as well as the contact of the second Schottky diode consist of a metallization selected from the group consisting of aluminum and a layer sequence of platinum silicide/
aluminum.
in that the emitter and collector contacts of the bipolar tran-sistor as well as the contact of the first Schottky diode are part of an interconnect level generated in addition to a conventional aluminum based interconnect system and consist of a silicide of a high melting point metal selected from the group consisting of tantalum, tungsten, molybdenum and titanium, and the base contact of the bipolar transistor as well as the contact of the second Schottky diode consist of a metallization selected from the group consisting of aluminum and a layer sequence of platinum silicide/
aluminum.
2. A method of producing an integrated semiconductor cir-cuit with at least one npn bipolar transistor and at least two types of Schottky diodes as defined in claim 1, comprising, a sequential combination of the steps:
a) defining active regions of said circuits by producing n+
-doped zones spaced from one another in a p-doped substrate by masked ion implantation;
b) applying an expitaxial n- -doped layer on the n+ -doped zones;
c) etching an insulation trough in the region between the n+
-doped zones;
d) generating an insulation oxide in the region of the insulation trough;
e) producing an n+ -deep diffusion in a collector region of the bipolar transistor, after masking the remaining regions of the bipolar transistor;
f) removing the masking layer for the deep diffusion collector, generating a mask for defining a base zone of the bipolar tran-sistor and executing an ion implantation with p-doping ions for generating the base zone of the bipolar transistor;
g) executing a photo-lithographic process for defining an emitter zone and etching an oxide layer generated during base diffusion in the emitter region;
h) generating the emitter zone by an ion implantation and diffu-sion of n-doping ions;
i) executing a photo-lithographic process for defining a contact of a first Schottky diode and for defining contacts for emitter and collector zone of the bipolar transistor and removing the oxide layers in these regions;
j) depositing surface-wide, a silicide layer and structuring such layer such that it functions as an additional interconnect in the region of the bipolar transistor and functions as an implantation mask during a subsequent base contact implantation;
k) covering the Schottky region with a photosensitive resist layer;
l) executing a base contact implantation with p-doping ions;
m) removing the resist layer and annealing the structured sili-cide layer so as to crystallize the silicide layer while simultane-ously electrically activating the implanted ions;
n) depositing an insulation layer functioning as an intermediate oxide;
o) etching contact hole regions for the base contact of the bipolar transistor and a contact of a Schottky diode; and p) metallizing and structuring an outer metal interconnect level.
a) defining active regions of said circuits by producing n+
-doped zones spaced from one another in a p-doped substrate by masked ion implantation;
b) applying an expitaxial n- -doped layer on the n+ -doped zones;
c) etching an insulation trough in the region between the n+
-doped zones;
d) generating an insulation oxide in the region of the insulation trough;
e) producing an n+ -deep diffusion in a collector region of the bipolar transistor, after masking the remaining regions of the bipolar transistor;
f) removing the masking layer for the deep diffusion collector, generating a mask for defining a base zone of the bipolar tran-sistor and executing an ion implantation with p-doping ions for generating the base zone of the bipolar transistor;
g) executing a photo-lithographic process for defining an emitter zone and etching an oxide layer generated during base diffusion in the emitter region;
h) generating the emitter zone by an ion implantation and diffu-sion of n-doping ions;
i) executing a photo-lithographic process for defining a contact of a first Schottky diode and for defining contacts for emitter and collector zone of the bipolar transistor and removing the oxide layers in these regions;
j) depositing surface-wide, a silicide layer and structuring such layer such that it functions as an additional interconnect in the region of the bipolar transistor and functions as an implantation mask during a subsequent base contact implantation;
k) covering the Schottky region with a photosensitive resist layer;
l) executing a base contact implantation with p-doping ions;
m) removing the resist layer and annealing the structured sili-cide layer so as to crystallize the silicide layer while simultane-ously electrically activating the implanted ions;
n) depositing an insulation layer functioning as an intermediate oxide;
o) etching contact hole regions for the base contact of the bipolar transistor and a contact of a Schottky diode; and p) metallizing and structuring an outer metal interconnect level.
3. A method as defined in claim 2, wherein, in step (j) said silicide layer is a silicide of a metal selected from the group consisting of tantalum, titanium, tungsten, and molybdenum.
4. In a method as defined in claim 2, wherein arsenic ions are utilized for the emitter implantation in step (h) and boron ions are utilized for the base contact implantation in step (1).
5. A method as defined in claim 2, wherein the metalliza-tion utilized in step (p) is selected from the group consisting of aluminum and a layer sequence of platinum silicide/aluminum.
6. A method as defined in claim 2, wherein a (100)-oriented, p-doped silicon substrate having a specific resistance in the range of about 10 ohm cm is utilized as the starting substrate.
7. A method as defined in claim 2, wherein the specific resistance of the n- -doped epitaxial layer applied in step (b) is in the range of about 2 ohm ? cm.
8. A method as defined in claim 2, wherein the silicide layer deposited in step (j) has a layer thickness in the range of about 200 nm.
9. A method as defined in claim 8, wherein said silicide layer is composed of tantalum silicide.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3230050.6 | 1982-08-12 | ||
| DE19823230050 DE3230050A1 (en) | 1982-08-12 | 1982-08-12 | INTEGRATED SEMICONDUCTOR CIRCUIT WITH BIPOLAR COMPONENTS AND METHOD FOR THE PRODUCTION THEREOF |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1212485A true CA1212485A (en) | 1986-10-07 |
Family
ID=6170719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000434348A Expired CA1212485A (en) | 1982-08-12 | 1983-08-11 | Integrated semiconductor circuits with bipolar components and method of producing same |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0100999B1 (en) |
| JP (1) | JPS5948958A (en) |
| CA (1) | CA1212485A (en) |
| DE (2) | DE3230050A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319974A (en) * | 1988-06-20 | 1989-12-26 | Nec Corp | Semiconductor device |
| KR930003273B1 (en) * | 1989-03-14 | 1993-04-24 | 가부시키가이샤 도시바 | Semiconductor device |
| JPH0582772A (en) * | 1991-09-20 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| DE102007011406B4 (en) * | 2007-03-08 | 2009-10-22 | Austriamicrosystems Ag | A method of fabricating a Schottky diode and Schottky diode semiconductor device |
| CN113066723B (en) * | 2021-03-19 | 2022-06-07 | 厦门市三安集成电路有限公司 | Heterojunction bipolar transistor and manufacturing method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2624339C2 (en) * | 1976-05-31 | 1986-09-11 | Siemens AG, 1000 Berlin und 8000 München | Schottky transistor logic |
| DE2624409A1 (en) * | 1976-05-31 | 1977-12-15 | Siemens Ag | Schottky transistor logic circuit - is formed by deep implantation in epitaxial layer to give switching time of order of 1 nanosecond |
| US4215156A (en) * | 1977-08-26 | 1980-07-29 | International Business Machines Corporation | Method for fabricating tantalum semiconductor contacts |
| US4190466A (en) * | 1977-12-22 | 1980-02-26 | International Business Machines Corporation | Method for making a bipolar transistor structure utilizing self-passivating diffusion sources |
| JPS55125666A (en) * | 1979-03-23 | 1980-09-27 | Nec Corp | Semiconductor device |
| IL61678A (en) * | 1979-12-13 | 1984-04-30 | Energy Conversion Devices Inc | Programmable cell and programmable electronic arrays comprising such cells |
| JPS56137655A (en) * | 1980-03-29 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS57106156A (en) * | 1980-12-24 | 1982-07-01 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS582065A (en) * | 1981-06-25 | 1983-01-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58169971A (en) * | 1982-03-30 | 1983-10-06 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1982
- 1982-08-12 DE DE19823230050 patent/DE3230050A1/en not_active Withdrawn
-
1983
- 1983-08-02 EP EP83107620A patent/EP0100999B1/en not_active Expired
- 1983-08-02 DE DE8383107620T patent/DE3379564D1/en not_active Expired
- 1983-08-10 JP JP58146262A patent/JPS5948958A/en active Granted
- 1983-08-11 CA CA000434348A patent/CA1212485A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0100999A2 (en) | 1984-02-22 |
| EP0100999B1 (en) | 1989-04-05 |
| DE3379564D1 (en) | 1989-05-11 |
| EP0100999A3 (en) | 1986-05-14 |
| JPS5948958A (en) | 1984-03-21 |
| JPH0241902B2 (en) | 1990-09-19 |
| DE3230050A1 (en) | 1984-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1203641A (en) | Semiconductor circuit containing integrated bipolar and mos transistors on a chip and method of producing same | |
| US6630377B1 (en) | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process | |
| EP0110211A2 (en) | Bipolar transistor integrated circuit and method for manufacturing | |
| US5895953A (en) | Ohmic contact to lightly doped islands from a conductive rapid diffusion buried layer | |
| EP0021403B1 (en) | Self-aligned semiconductor circuits | |
| JP3285207B2 (en) | Vertical fuse device using thin sacrificial layer and method of manufacturing Schottky diode | |
| JPH07120653B2 (en) | Manufacturing method of monolithic integrated circuit | |
| US5014107A (en) | Process for fabricating complementary contactless vertical bipolar transistors | |
| EP0450500A2 (en) | High performance semiconductor devices and their manufacture | |
| US4425379A (en) | Polycrystalline silicon Schottky diode array | |
| EP0463476A2 (en) | Self-aligned collector implant for bipolar transistors | |
| EP0709894B1 (en) | High-frequency bipolar transistor structure, and related manufacturing process | |
| US5055418A (en) | Process for fabricating complementary contactless vertical bipolar transistors | |
| CA1212485A (en) | Integrated semiconductor circuits with bipolar components and method of producing same | |
| US6387769B2 (en) | Method of producing a schottky varicap | |
| US5244832A (en) | Method for fabricating a poly emitter logic array and apparatus produced thereby | |
| JPH0241170B2 (en) | ||
| US5107320A (en) | Method and apparatus for improvement of interconnection capacitance | |
| CA1290466C (en) | Process for fabricating complementary contactless vertical bipolar transistors | |
| KR100303701B1 (en) | Retrograde N-Well cathode Schottky transistors and how to manufacture them | |
| US5262672A (en) | Apparatus for improvement of interconnection capacitance | |
| US5355015A (en) | High breakdown lateral PNP transistor | |
| US5885897A (en) | Process for making contact to differently doped regions in a semiconductor device, and semiconductor device | |
| KR100350760B1 (en) | Semiconductor integrated bi-mos circuit having isolating regions different in thickness between bipolar area and mos area and process of fabrication thereof | |
| US5140383A (en) | Method for fabricating a buried Schottky logic array and apparatus produced thereby |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |