CA1197322A - Apparatus for the dynamic in-circuit testing of electronic digital circuit elements - Google Patents
Apparatus for the dynamic in-circuit testing of electronic digital circuit elementsInfo
- Publication number
- CA1197322A CA1197322A CA000444461A CA444461A CA1197322A CA 1197322 A CA1197322 A CA 1197322A CA 000444461 A CA000444461 A CA 000444461A CA 444461 A CA444461 A CA 444461A CA 1197322 A CA1197322 A CA 1197322A
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- Canada
- Prior art keywords
- test
- library
- signals
- block
- signal
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Abstract of the Disclosure Apparatus for the dynamic in-circuit testing of digital electronic devices employs a hardware testing circuit that is set by a microcomputer which takes no direct part in the test, so that the test hardware speed is not limited by the computer speed. The apparatus comprises a library of devices corres-ponding to the devices to be tested, the library including a ROM containing the information regarding the devices needed by the microcomputer for its purpose. An internal interface or router receives signals from the test device that are input signals to its terminals and routes them directly to the corres-ponding selected device in the library where it becomes an input to that device also. Signals from the test device that are output signals are routed instead to a comparison block where they are compared with the respective output signals from the library reference device. The signals at each corresponding pin of the two devices are compared and upon the presence of a fault the apparatus stops and identifies the pin or pins on which a fault has been detected. An external interface is provided to shift the signal levels as required between the test device and the TTL logic devices of the apparatus. The signals are sampled during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.
Description
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APPAI?I\TUS ~;'OR T~E DYNI~MIC IN-CIRC[)IT TESTINC, OF ELECTRONIC
l~)IGII'}\L CI RCUIT EI,EMENTS
Field of the Invention This invention is concerned with apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
Review of the Prior Art The continuing development of electronic digital circuit elements, and electronic circuits including such elements, of greater diversity and complexity is accompanied by corresponding increases in the difficulty and expense of testing them quickly and adequately, either during assembly of the circuit or sub-sequently after the circuit has been in use for some time. Such testing is important commercially, since the sale of equipment with too high an incidence of faults will result in loss of reputation for quality, while if the testing is unduly difficult and time-consuming, requiring expensive skilled manpower for its implementation, then the resultant increase in the servicing cost may be unacceptable.
Traditional forms of test gear such as oscilloscopes and logic analyzers require a high degree of skill in the test operator. In the application of another technique known as signature analysis a known bit stream is passed through the digital circuit and the resultant "signature" produced by that hit-stream examined for response at different points in the circuit. In a further technique a microprocessor or the like under test is replaced with an emulating microprocessor which - 1- ~
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controls the circuit in its place; such a system can only indicate that a malfunction exists in the devices on the bus but not the Location of the malfunction. Simple replacement of an entire faulty circuit board is also employed, but is expensive in inventory, and su~sequently the faulty board must be examined for repair.
It is of course ~nown to test a circuit element by direct comparison with a pre tested sample of the same element, since this reduces the amount of information re~uired to determine whether or not the tested element is satisfactory. However, such testing has been difficult and time-consuming with known arrangements. A typical circuit board will carry a wide variety of different elements to be tested, all of which usually are operative with different parameters that must be pre-set before the particular element can be tested. If a number of similar boards are to be tested, the same element on all the boards can be examined one after the other while the test equipment is set for that element, but this then involves moving from board to board between each test.
Definition of the Invention It is therefore an object of the invention to provide a new apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
It isa more specific ob~ect to provide such apparatus wi-th which an element is tested rapidly by direct comparison with the same element provided by the testing apparatus.
.. . . . .. .... . . .
In accordance with the present invention there is provided a library module for use in apparatus for the dynamic in-circuit testing of a plurality of different electronic digital test elemen-ts comprising:
a circuit board having thereon a plurality of busbars;
a plurality of electronic digital reference elements connected to the said busbars to permit the selective access -to the terminals of each reference ele~ment; and a memory means connected to the said busbars for access by a memory interrogation means, said memory means having therein informa-tion for each reference element consisting of:
a) identification of the respective reference element, b) identification of the busbars that are accessed for access to the respective reference element, c) identification of the sta-tus of each operative contact of the respective reference element as to whether it is an input terminal, an output terminal, or bidirectional between an output and an input terminal.
Preferably such a library module includes logic means for each reference element having therein information as to the toggle signal required for the element for determination of the status of each b.idirectional terminal as an input or output terminal .
Such a library module is employed in combination with apparatus for the dynamic in-circuit testing of an electronic di~ital circuit element employing the module, the apparatus comprising:
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means for accessing the terminals of a test elemen-t to be tes-ted Eor -the receipt of the respective electric signals at at least the operative -terminals of the test element said library module;
means for selecting a reference digi-tal el.ement from the said plurality thereof in the library module corresponding to the respective test element to be tested, and signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indica-tion if the comparison indicates the presence of a fault.
Preferably, the said selecting means may comprise computer means ~or interroyating the memory means and subsequently powering the selected reference element in the library module.
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Description of the Drawings.
Test apparatus which is a particular preferred embodiment of the invention will now be descxibed, by way of example, with reference to the accompanying ~chomatic drawings, wherein:
FIGU~E 1 is a generalised block diagram of the preferred embodiment, FIGURE 2 is a more detailed schematic diagram of the external interface block of the perferred embodiment, FIGURE 3 is a more detailed schematic diagram of the internal interface block, FIGURE 4 is a moxe detailed schematic diagram of the library block, FIGURE 5 is a more detailed schematic diagram of the comparison and fault detection block, FIGURE 6 is a timing diagram to iilustrate the timing system used in the comparison and fault detection block, and FIGURE 7 is a logic diagram to show the operation of the control block in controlling the operation of the other blocks of the preferred embodiment.
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Description of the Preferred Embodiment The test apparatus illustrated is intended for the testing of elements made under current industry manufacturing standards wherein each element has the form of a rectangular S block of either 7.5 mm or 15 mm width, provîded along its two longer parallel sides with two respective rows of uniformly-spaced metal terminal pins. Currently such el~ments have from 14 to 40 pins, each of which depending upon the intcrnal architecture may be a signal input terminal, a signal output terminal, or be bi-dïrectional. For testing purposes with this embodiment an element is temporarily connected to the test apparatus by use of a known type of spring-~awed clip, the opposed jaws of which carry respective sets of electric contacts each arranged to engage a respective pin when the clip is clamped lS on the element. A multi-wire cable carries signals from the jaw contacts and thus to and from the respective pins.
In addition to the clip the apparatus provides five other leads as follows:
1) A ground lead for connection to the ground of the board on which the device is mounted,
APPAI?I\TUS ~;'OR T~E DYNI~MIC IN-CIRC[)IT TESTINC, OF ELECTRONIC
l~)IGII'}\L CI RCUIT EI,EMENTS
Field of the Invention This invention is concerned with apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
Review of the Prior Art The continuing development of electronic digital circuit elements, and electronic circuits including such elements, of greater diversity and complexity is accompanied by corresponding increases in the difficulty and expense of testing them quickly and adequately, either during assembly of the circuit or sub-sequently after the circuit has been in use for some time. Such testing is important commercially, since the sale of equipment with too high an incidence of faults will result in loss of reputation for quality, while if the testing is unduly difficult and time-consuming, requiring expensive skilled manpower for its implementation, then the resultant increase in the servicing cost may be unacceptable.
Traditional forms of test gear such as oscilloscopes and logic analyzers require a high degree of skill in the test operator. In the application of another technique known as signature analysis a known bit stream is passed through the digital circuit and the resultant "signature" produced by that hit-stream examined for response at different points in the circuit. In a further technique a microprocessor or the like under test is replaced with an emulating microprocessor which - 1- ~
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controls the circuit in its place; such a system can only indicate that a malfunction exists in the devices on the bus but not the Location of the malfunction. Simple replacement of an entire faulty circuit board is also employed, but is expensive in inventory, and su~sequently the faulty board must be examined for repair.
It is of course ~nown to test a circuit element by direct comparison with a pre tested sample of the same element, since this reduces the amount of information re~uired to determine whether or not the tested element is satisfactory. However, such testing has been difficult and time-consuming with known arrangements. A typical circuit board will carry a wide variety of different elements to be tested, all of which usually are operative with different parameters that must be pre-set before the particular element can be tested. If a number of similar boards are to be tested, the same element on all the boards can be examined one after the other while the test equipment is set for that element, but this then involves moving from board to board between each test.
Definition of the Invention It is therefore an object of the invention to provide a new apparatus for the dynamic in-circuit testing of electronic digital circuit elements.
It isa more specific ob~ect to provide such apparatus wi-th which an element is tested rapidly by direct comparison with the same element provided by the testing apparatus.
.. . . . .. .... . . .
In accordance with the present invention there is provided a library module for use in apparatus for the dynamic in-circuit testing of a plurality of different electronic digital test elemen-ts comprising:
a circuit board having thereon a plurality of busbars;
a plurality of electronic digital reference elements connected to the said busbars to permit the selective access -to the terminals of each reference ele~ment; and a memory means connected to the said busbars for access by a memory interrogation means, said memory means having therein informa-tion for each reference element consisting of:
a) identification of the respective reference element, b) identification of the busbars that are accessed for access to the respective reference element, c) identification of the sta-tus of each operative contact of the respective reference element as to whether it is an input terminal, an output terminal, or bidirectional between an output and an input terminal.
Preferably such a library module includes logic means for each reference element having therein information as to the toggle signal required for the element for determination of the status of each b.idirectional terminal as an input or output terminal .
Such a library module is employed in combination with apparatus for the dynamic in-circuit testing of an electronic di~ital circuit element employing the module, the apparatus comprising:
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means for accessing the terminals of a test elemen-t to be tes-ted Eor -the receipt of the respective electric signals at at least the operative -terminals of the test element said library module;
means for selecting a reference digi-tal el.ement from the said plurality thereof in the library module corresponding to the respective test element to be tested, and signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indica-tion if the comparison indicates the presence of a fault.
Preferably, the said selecting means may comprise computer means ~or interroyating the memory means and subsequently powering the selected reference element in the library module.
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Description of the Drawings.
Test apparatus which is a particular preferred embodiment of the invention will now be descxibed, by way of example, with reference to the accompanying ~chomatic drawings, wherein:
FIGU~E 1 is a generalised block diagram of the preferred embodiment, FIGURE 2 is a more detailed schematic diagram of the external interface block of the perferred embodiment, FIGURE 3 is a more detailed schematic diagram of the internal interface block, FIGURE 4 is a moxe detailed schematic diagram of the library block, FIGURE 5 is a more detailed schematic diagram of the comparison and fault detection block, FIGURE 6 is a timing diagram to iilustrate the timing system used in the comparison and fault detection block, and FIGURE 7 is a logic diagram to show the operation of the control block in controlling the operation of the other blocks of the preferred embodiment.
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Description of the Preferred Embodiment The test apparatus illustrated is intended for the testing of elements made under current industry manufacturing standards wherein each element has the form of a rectangular S block of either 7.5 mm or 15 mm width, provîded along its two longer parallel sides with two respective rows of uniformly-spaced metal terminal pins. Currently such el~ments have from 14 to 40 pins, each of which depending upon the intcrnal architecture may be a signal input terminal, a signal output terminal, or be bi-dïrectional. For testing purposes with this embodiment an element is temporarily connected to the test apparatus by use of a known type of spring-~awed clip, the opposed jaws of which carry respective sets of electric contacts each arranged to engage a respective pin when the clip is clamped lS on the element. A multi-wire cable carries signals from the jaw contacts and thus to and from the respective pins.
In addition to the clip the apparatus provides five other leads as follows:
1) A ground lead for connection to the ground of the board on which the device is mounted,
2) A lead (EX CLK~ to connect to the external clock or its equivalent on the test board,
3) A lead (INT CLK) to prov.ide an internal clock from the apparatus to the test board if such is a clock needed, or if the test clock i.s too fast for the apparatus,
4) A lead (INT CLK) providing the complement of 3), and S)An external lead for giving a reset signal to restart a proyranunable device or board operation when required.
T~lrning now to F'igure 1, the jaw contacts of such a clip 10 are connected via a cable 12 to corresponding contacts of an external interface (E.I.) block 14, which is in turn connected to an internal interface (I.I.) block 16. Signals from the I.I. block may pass di.rectl~ to a comparison and fault detector (C~F.D.) hlock 18, or may go to a library block 20, as will be described belo~. Signals also pass from the library block 20 to the C.F.D. block 18 and signals indicating the "status" of each of the pins of an element under test are passed from the C.F.D. block 18 to a display ~lock 22, which in this embodiment gives a visual display. It will be understood that for example in an embodiment employed in an automatic test facility such a visual display may not be necessary and may be omitted or replaced by some other unit as required by the purchaser for indicating that the tested element has passed or failed the test and/or taking some action depending upon pass or failure of the test.
Certain control functions to ~e described below, particularly those required during a test, are performed by a control block 24, which has direct access to the I.I. block 16 and C.F.D. block 18, while other functions required in preparation for and following a test are performed by a microcomputer 26, which has direct access to all of the block with the exoeption of ~le display block 22. Microcomputer 26 also has access to a user interface block 28 including a keyboard and alphanumeric display by which a human operator can insert necessary information into ; the apparatus and al.so receive information, prompts and commands there~rom. As with display block 22, the configuration of the user interface block 28 will also depend upon whether a human operat~r is required, or whether the test apparatus is being run by a machine. The function of each of the above-~escribed blocks and their inter-relation with one another will be described below.
The operation of apparatus of the inventlon depends upon the presence in the librar~ block 20 of a device or element that is a duplicate of the device to ~e tes~ed, or that can be made to operate as ;f it were a duplicate of the tested device.
Such duplication of the tested device may be for example by adjustment of the voltage levels and/or timing of the input/
output signals involved. This may be contrasted with test apparatus of the kind employing a microcomputer in which the microcomputer software or firmware is written so that the micro-computer will simulate the device under test, requiring complete and detailed information as to the operation of the device as well as the signals involved in its operation.
The library block consists of at least one board, usually a plurality of boards, each of which has connected to the busbars thereof a plurality of devices that are to be tested, all wired`to the busbars to permit individual access to each element and also to the pins of each element as required. Each such board can consist, for example, of a group of dissimilar elements all from the same manufacturer, or a group o~ similar elements, one from each of the available manufacturers, or a group o~ devices all of the same technology e.g. TTL; MOS; CMOS;
DTL; ECL, etc. Again, each library board can be as identical , as possible in content and layout to a circuib board that is . . .
to be tested, ~nd this is particularly valuable in ensuriny that heating conditions, time delays, intercouplings, leakages, etc.
will be as nearly as possible the same.
Each library board also includes a read only memory means connected to appropriate bus~ars of the ~oard and containing necessary information for each element on the board, such as lts index number ~or operator identification, the identi-fication of the ~oard on which it is mounted, the library board bus coordinates t~at must be enabled and accessed to power the element and access its terminals, the status of each of the terminals of the element ~.e. whether it is an input, output or bidirectional terminal), the voltage bias levels required for operation, the speed of operation and the corresponding time delays that may be required for its signals to be compared with those of the test device, and the time required for a complete test of its operation. For economy in manufacture this memory preferably is a single central unit for the whole board, but of a type that can be re-programmed when required if any of the devices on the board is replaced by a different device.
Let it first be assumed that a human operator is to test a single element on a board having a clock signal that is directly usable by the test apparatus and of a kind that does not require a reset si.gnal for its operation~ Before commencing the test the operator will interrogate the test apparatus via the user interface 28 to determine whether or not the same or an equivalent device is in the library block. Each device to be ., 9 tested and the reference device are identified to the operator by the above-mentioned identification number stored in the respective library board memory. rrhe operator supplies this number to the microcomputer 26 via a numerical keypad 30 in the user interface 28 and then presses the search (SRCH) key 32, causing the microcomputer to search the library memories and display on an alpanumeric display unit 34 in t~e user interface 28 whether or not the device is in the library, and if so the library board on which it is located. If the search does not find a device with this identification the computer will provide the display unit 34 with an appropriate display such as "not available".
Once assured that the device can be tested the operator now connects EX CLK lead 35 to the board on which the device is mounted to receive the clock signal, connects ground lead 36 to the board bround, puts clip 10 on to the device and p~esses enter key 37 to enter the devioe identification data as shown on the display 34.
The microcomputer now interrogates the respective library memory unit for the pertinent information on the selected device and also powers the selected device, so that it is in the same condition of operation as the external test device. At the same time the data about the selected device is employed by the micro-computer to set the E.I. block 14 to provide the required bias voltages; ~o ,set the I.I. block 16 so that it will properly route the signals it receives, as will be described below, and to set the control ~lock ~4 so that the latter will initiate and control a testing cycle for the selected device~ This data ~ o 3~'~
about the selec~ed device will be stored in suitable registers which may be provided in the microcomputer block or in the respective block to which the data has been transferred. If the register is in the respective block then once the data has been transferred to it the microcomputer can disable itself from further access to that register until there is a need to replace the data for a new test device. ~laving performed these functions the microcomputer enters on the display 34 an indication that a test is possible and then, except forvarious accessory functions described below, disables itself from taking any further part in the test per _ .
The test element is in active condition in its circuit~
which must be powered up for the test to be possible, so that the element is receiviny the input signals and power supply or supplies that are available to it from its own board; the element will also be delivering output signals to the respective output terminals which, if the element is functionlng properly, are appropriate for the input signals and power that it is receiving. As described above the signal at a particular terminal pin of the test element will be supplied via clip 10 to the external interface, where its level will be changed if necessary as previously set by the microcomputer. If it is an input signal it is routed automatically by the I.I. block 16 to the C.F~D. block and also to the corresponding terminal pin ~-~ of the library reference device and becomes an input to that device. If it is an output signal it is routed automatically by the I.I. block 16 to the C.F.D. block 1~ and is preven~ed from / I
access to the library reference element. If the signal is changing from input to output then in input mode it will be routed as above for an input signal while in output mode it will be routed as above for an output signal under control of a "toggle"
signal supplied to the I.I. block 16.
Upon the operator pre~sing the test key 38 the control block 24 will now operate the I.I. ~lock 16, the library block 20, and the C.F.D. block 18 to scan synchronously and simultaneously the pins of the external device and the same pins of the library device. The input signal on any input pin of the test device will be routed by the I.I. block 16 to the library reference device, while the output signal on any output pin of the test device will be routed directly to the C.F.D.
block 18 to be compared with the signal from the same pin of the library reference device. It is usually preferred for a complete test to scan over a relatively large number of cycles since, in general, each such cycle takes only a small fraction of a second and the total t~ for an exhaustive test is very sm~ll as co~pared with the time required to ve the clip 10 from one element to another. In the case when one or more of the pins are bi-directional a plurality of scans will be required until the device has been tested in all possible states, the I.I. block 16,routing the signal as required in dependence upon whether it is an input or an output.
The C.F.D. block 18 comprises a bank of comhinatorial logic elements, forty in this particular embodiment since forty pin devices are to be tested, each of which compares the signal from the respective pin of the test device with that from the corresponding pin of the library reference device and feeds any _ ~ _ / '~
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output to a respective one of forty indicator devices 40 in the display block 22. Thus, if any one of the combination logic elements is fed two different digital signals the respective indicator will be actuated to show a fault condition on that pin, whereupon the operator will know not only that the device is faulty, but the pin or pins at which the fault or faults is occurring An audible signal may also be employed to alert the operator that a fault is present. The clip can then be moved to another similar device and the test button 38 again pressed to obtain a test of the new device, and so on. At any time the status of the pins and whether or not a fault is present can be read by the microcomputer and this information supplied to the interface 28 or some other external apparatus.
It was assumed above that the devioe under test en~plc~ed the clock signal frcm its c~n board, but frequently this is not the ~ase, and a cloc~ signal or c~mplen~ntary clock signal can be supplied from the micro-c~mputer via the E.I. block 14 through respective leads 42 and 43, while a reset signal is supplied when required from the same block under cor~trol of the microcomputer through a lead 44~ The direction of the clock signal to be supplied from the test apparatus is selectable, depending upon whether triggering occurs on the rising or falling edge of the clock pulse. The information as to what clock signal is required will be in the library memory, but needs to be fed to the microproeessor as an instruetion. The operator therefore presses a eloek key 46, whereupon the mic:roprocessor will display the clock requirement for the deviee and a menu for operation of the numeric pad 30 l3 to ob~ain the necessary signal; for example the menu will instruct the operator to press "1" for the microprocessor internal clock to supply the device with a clock signal of one polarity, press "2" for an internal clock signal with opposite polarity; and press "3" if an external clock signal is already provided.
It may be found that the external clock signal is too fast to be usable or for convenience in testing, in which case the internal clock will be used at a speed set by the micro processor and determined from the information in the library.
The library information conveniently is stored therein in the form of the preferred frequency and preferred number of cycles for the test: upon reading this information the microcomputer will calculate the test duration required and terminate the test cycle upon expiry of this time. The microcomputar includes a frequency counter unit which is actuated by operation of a frequency key (FREQ) 48, whereupon the display 34 will display the usual frequency and polarity of the clock that is in use.
Upon the operator pressing a time key 50 the micro-computer will show on the display 34 the duration of the test tobe made and a menu to change the time if this is not satisfactory. The required test duration is selected by keying the number of milliseconds via the numerical pad 30 and then pressing the enter key 36. This feature is used, for example, if the fault is known to be intermittent, or if a longer test time than usual is required, e.g. for a soaking test.
The circuits and logic arrangement of the various blocks _ ;~ _ 1~
~l97322 will now be described in greater detail, other ~eatures of the apparatus also being described where this is appropriate~
External Interface ~lock 14 This constitutes a buffer of high input impedance between the test apparatus and the device being tested, so as not to unduly affect the operation of the test device, and also acts as a level translator to enable the test apparatus to deal with families of devices other than those used in the apparatus blocks. Thus, this particular preferred embodiment predominantly employs TTL logic devices in its construction and in the absence of the interface block 14 could only conveniently test other TTL logic devices, since other types requiring different logic thresholds might not give signals that could be handled by the test apparatus. Part of the information stored in the l.ibrary memory on each library board and supplied by the microcomputer to the external interface block is the bias level offset required to translate the digital signals received and transmitted by the E~I. block to the standard levels for TTL
logic devices of a maximum of 008 volts for "0" and a minimum of 2.4 volts for "1". The operator presses a bias key 52 to be told the offset that has been given to the E.I. block by the microcomputer for the test device together with a menu for change if this should prove necessry. If necessary the number of millivolts of change required is set by the key pad 30 and entered by pressing the enter key 36.
Referring now to Figure 2, which shows in greater detail the circuit of the external interface block, the forty leads in the cable 12 and the single clock lead 35 feed their signals to 1S' ~732~
respective high input impedance buffers 54, whilP the corres-ponding forty one separate output leads 56 feed their signals to respective offset modules 58, each of which will accept the digital signal received on lead 56 and feed the corresponding TTL logic signal out on its output lead 60 to the I.I. block 16.
An internal power unit (not shown) provides each offset module on input leads 62 and 64 respectively with the voltages appropriate to produce a TTL logic "1" or "O" on the output lead 60. The offset data from the microcomputer is also fed via a lead 66 to a shift register 68, which controls the output of a digita~
analog converter and driver 70 to produce a ground reference voltage for the signals from the offset modules. This analog ground signal is fed to a ground detector 72 which is also connected to the external ground lead 36. Upon detection of current flow between the two grounds the detector transmits a signal via lead 76 to the microcomputer that a ground refer-ence is available and the test may proceed, and otherwise not.
Internal Interface Block 16 Referring now to Figure 3, which shows in greater detail the circuit of the I I. or routing block 16, each output lead 60 from E.I. block 14 constitutes an input lead to a respective set of three controlled switch devices 80 (designated Cl, C2 and C3 respectively) which set is controlled by a respective control block 82. The input to each control block 82 i5 from two separate 40-bit registers 84 and 86, _ ~ _ /~
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called respectively the Y and Z register, which are ~upplied with the required information as to the status of the respective device pin from the library memory via the microcomputer 26.
The bit signals received by each control block 82 from the X
and Y registers is used in combination with a toggle signal received from the lihrary block via lead 88 to issue the necessary control signals to the switches Cl, C2 and C3. The two bit YZ
input specifies whether the signal is an input or an output or a toggle, and the incoming toggle signal will in the latter case make the final determination hetween input and output as required. Thus, if the incoming signal is an input then the two switches C2 and C3 are closed while the switch C~ is open and the signal is fed via leads 90 and 92-to the C.F.D. block 18 and via lead 94 to the library block 20. If the incoming signal is an ou~put then the two switches C2 and C3 are open and the switch Cl is closed, whereupon the signal from the E.I. block 14 cannot acoess the library devioe, but can ~ccess the C.F.D. block 18 via lead 92, while the oorresponding output signal from the ~ rary devioe can return to the I.I. block vla lead 94 and access the C.F.D. block via the lead 90.
A special situation arises when the device to be tested is of a kind, such as a shift register, which must be synchronised with the library device. In such case each control device 82 is issued a "synchronous mode" signal via lead 96; in this mode with an input signal the switches Cl and C3 are now open while switch C~ is closed so that the signal can only input the C.F.D. block 18 via leads 90 and 9 and is blocked from the library devioe via lead 94, while with an output signal the switch Cl is closed and l7 ~J ~
both switches C2 and C3 are open so that access to the library device from the E.I. block is ~gain prevented while the library device can feed to the C.F.D. block 18 via leads 94 and 90. The library device is therefore inactive in a specîfic pattern and the C.F.D. block will detect this as a fault~since it is immaterial to that block whether the "fault" is in the test device or the library device; the test devic2 will cycle through different patterns and upon achieving a pattern corresponding to the "frozen" pattern of the library device the "fault" indication will 10 disappear and the two devices now operate ln synchronism. The C.F.D. block is controlled by the control block to ignore this "fault" for a pr~determined period of time and if synchronisation is not achieved with this period the control block 24 then issues a restart signal to the cycle control to indicate this failure 15 and put the apparatus in standby mode; at the same time the micro-computer block will provide an instruction "failure to synchronise"
on the display 34, since the most likely reason is of course a faulty device.
Library ~lock 20 Figure 4 is a more detailed circuit drawing of a part of one library board in the library block although, as will be understood, a typical embodiment of the invention will usually comprise a number of diferent boards. As described above each board 98 includes a read only memory 100 connected by leads 102 2S and 104 respecti~ely to the address and data busses of the micro-computer so that it can be interrogated and transfer its stored information to the microcomputer ~or utilisation and display.
Ig ~:~ffl73~.
When the computer block has identified the device to be selected, either by a preset program to be described below, or by an operator feeding this information to the computer block, the computer block will issue a "select board" signal on lead 106 to a control logic device 108 that will in turn close a switch 110 permitting power to be supplied to the board. At the same time the computer block issues a "select device" signal on lead 112 to a register 114 that in turn will cause closing of a respective switch 116 that will permit the powering up of the selected library device 118 corresponding to the test device.
Each library device is connected via a board bus 119 to a library block bus 120 and by the leads 94 to the I.I. block 16.
If the selected device is of a type in which one or more of the pins is bidirectional then ~he board also carries a respective toggle logic block 121 arranged for that device and ~hich is selected by closing of the respective switch 116, this block feeding the toggle signal as described above on leads 88 to the I.I. block 16.
Since the test apparatus itself employs TTL logic devices such devices in the library are immediately compatible with the test apparatus circuits and can be connected directly to the board bus 119 and thence to the library bus 120. Devices such as device 122, corresponding to test devices that require offset voltages to be provided by the E.I. block 14, cannot be directly connected in this manner because of this inherent incompatability; instead they are connected to a sub-bus 123 that is connected to the board bus 119 via driver 124 providing to the sub-bus 123 73~3~
the voltages required for proper operation of the device, this driver being enabled by the ~oard select signal.
C.F.D. Block 18 Turning now to Figures 5 and 6 the C.F.D. block receives signals from the library block 20 via leads 90, and from the I.I. block 16 via leads 92; these signals are fed to respective high ~d nem~ry elements (lat~hes) 126 and 128, also labelled Ll and L2, and ~hence to a respective combinatorial logic element 130. The output from each element 130 is fed to a respective high speed memory element (latch) 132, also labelled L3.
If the digital signals received by an element 130 do not correspond it detects the lack of correspondence as a fault and activates a driver 134 that lights the respective lamp 40 in the display block 22. The outputs o all of the elements 130 are fed to a combination detector de~ice 136 that feeds a "fault detected" signal on-lead 138 to the microcomputer, so that it will give an indication of a fault detection. The device feeds a corresponding signal c~ lead 139 to the C.F.D. block, so as to "stop" the test immediately with the fault or faults indicated, since otherwise the test might move on to a situation where there is no fault and the fault indica~ion would be lost.
At the same time all the outputs are fed to a multiplex detector register 140 that can be interrogated by themicro.computer via leads 142 to determine which of the device pins have been detècted as faulty and provide a read~out either on the display 34 or some ~73~'~
equivalent unit, e.g. a printer.
Owing to the high speed at which the apparatus operates it is necessary to contro:L the operation of the latches 126, 128 and 132 so that the signals ~re sampled during precisely controlled time periods. This arrangement also permits compen-sation for the differing propagation times of signals through the various components from which the apparatus itself is assembled. It also widens the test capability of the apparatus in ~hat devices of the same configuration but of different families, and thereof of dif~erent response speeds, can be tested without the need for exact correspondence between the test and library devices. For example a TTL library device can be used to test a Schottky (fast TTL) device of the same configuration.
A high speed clock 144 feeds a ripple counter 146 which produces the necessary large number of uniform pulses. Inform-ation as to the time delays tdl, td2 and td3 required for the particular device are supplied by the microcomputer block to a register 1~8 after this information has been extracted by it from the R.O.M. 100 in the respective library board. The counter 146 and register 148 feed a comparator 150 which in turn feeds the selected pulses to a control logic module 152 that is also fed with the appropriate clock signal to synchronise its operation with the test device Referring to Figure 6 a pulse 25 is fed after time delay tdl rom the start of the respective clock cycle to open latches Ll and the signals from the ~.I.
block 16 are sa~pled during the period Pl. Latches L2 ~1 ~ ~ ~a~
are opened for another period P2 that occurs after time delay td2 to sample the signals from the library block 20, while latches L3 are opened for a last period P3 that occurs after time delay td3 to sample the outputs of the com~ina~orial logic devices 130. All three pulses occur within one clock cycle and there is no overlap between them, so that the actual speed of operation of the tested device and the propagation times through the apparatus a~e immaterial as long as this condition can be fulfilled. In a particular preferred embodiment operating at 10 Mhz the length of one clock cycle will be 100 nanoseconds and each pulse will typically have a duration of 15 nanoseconds.
Control Bl ock 24 Referring now to Figure 7 which is a logic diagram to show the manner in which the control block is employed to control the other blocks of the apparatus and to issue control signals to those other blocks as requiredO The control block of the preferred embodiment is of pulsed asynchronous logic config-uration employing TTL Schottky NAND logic gates of the 74S-family e.g. 74S00; 74S04; 74S10; 74S20 and 74S30. Other families and other logic systems can of course be employed, as will be fully apparent to those skilled in the art.
Upon powering-up of the apparatus it is required to be in stand-by mode represented by state 1. If the apparatus is not already in this state then the required prompt is not provided by the microcomputer and accordingly it is dri~en to the state by the operator pressing a reset key 166, whereupon the microcomputer will issue the necessary instruction signal to the logic~ If the operator now presses the test key 38 the microcomputer will issue its test signal that will cause the logic f ~
~.~7~
to move asynchronously to state 2, also called system reset I.
In this second state the input/outputs to the library block are enabled and those to the C.F.D. block are disabled; also an external reset signal is applied to the test device if it is of the type that requires such a signal.
For devices not requiring an external reset signal, such as simple logic ~ates, the logic can move directly to Test state 7 in which all inputs/outputs are enabled together with the C.F.D. block 18, provided the fol:Lowing conditions are met:
a) a test has previously been initiated (I'EST) b) the external system clock is at iogic zero (SYSCLK), and c) the device has been determined previously by examination of the library block memory to be of the type not requiring an external reset (SYN).
Assuming that the logic is now in state 7, if now a fault is detected, the logic moves to state 8 in which all the inputs/outputs are disabled to stop or "freeze" the apparatus in the fault condition, while all accumulated information from the cycle with regard to the fault is held, so that it can be examined and displayed by the slower-operating microcomputer. A
return to stand-by state 1 is only obtained by issue of the reset signal, for example by the operatorO If no fault is detected then upon expiry of thP test period the logic issues a reset signal to return to state 1.
If synchronisation is required at state 2 then the necessary information comes from the library block as described above and with the presence of only conditions a) and b) above .....
~3 ~7~2~
the logic is now moved to state 4~ where the necessary check is made for synchronisation. ~s described a~ove the lack of "synchronisation" is detected as a "fault'~, but the logic is not axmed to drive the apparatus into "fault state" as in the asynchronous loop contain;ng state 8. Upon detection of this "fault" the logic drives immediately asynchronously to state 3, which is also called system restart 2. In this state 3, as was described above, all inputs into the library block are disabled, but all outputs are enabled and compared, so that the library devlce is "inactivel'. As soon as synchronisation is obtained there is no ~' fault" detected and with the system clock at logic zero the logic returns ~o skate 4; this loop can of course repeat and also state6 5 and 6 are employed to confirm that synchronism has ~een achieved, to take account for example of "glitches" on the clock lines giving false clock indications.
States 5 and 6 are operative on opposite levels of the clock signal and if a "fault" is still present at either of these stations the logic will return immediately to station 3 and the cycle repeated. If there is no "fault" indication at state 6 and the system clock is at the required higher level then the logic passes immediately to state 7 and the test takes place.
To avoid "lock-out" of the logic in any of the states provision is made for the application of a reset signal at each station that will drive the logic to standby state 1 for the sequence to be repeated~
~'t 3~
Microcom~uter slock As will be apparent to those skilled in the art from the description of the apparatus the per~ormance required for the microcomputer block is well within the capability of many currently available units. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity; four No.
2114 static RAMS each of two kilobytes capacity; and three No.
8155 static R~MS each of 1.5 kilobytes capacity and 16 I~O ports to provide a total of 48 I/O ports.
It will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed, and the only software and/or firmware needed is in the microcomputer, which can ~e a readily 1~ available unit. Moreover the speed of operation of the various blocks, and therefore of the complete apparatuS~is independent of the speed of operation of the microcomputer, which typically is much slower than is possible with a hardwàre-only block.
For example, as described above a preferred minimum speed of operation of the hardware of the preferred embodiment during a test is at l0 Megaherz; the operating speed of a suitable microcompute~
is about 4 Megaher~, but each instruction of the microcomputer requires at least several machine cycles for its execution, so that its actual operating speed is only a fraction of the speed 2S of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion o the apparatus is independent of the computer. The ~, , -- 2~ --73~
resultant apparat:~ls can therefore readlly be provided as a "turn-key" unit not requirin~ any software programming by the user.
A parti.cularly advantageous characteristic o~ the apparatus of the invention is that it is not necessary to know the internal construction or mode of operation of the test device for it to be tested successfully, as long as information is available as to the status of its pins during operation.
The apparatus can therefore be used to test a proprietory or military device for which the manufacturer is unwilling or unable to provide information as to its operation, and used to test a batch of devices whose operation is unknown as long as one can be sure that a correctly functioning device can be selected to serve as the library device.
Because of the possibilities described above of testiny external devices making use of an internal library de~iice that is equivalent but of a different family, the library device having one identification may also be identified as.corresponding to a number of different configurations, usually referred to as packages. This information is stored in the respective library R.O.M. 100 and will be displayed by the miCrocoMputer block on the display 34 upon interrogation of the memory, which will show that the device in the li.brary is of "packa~e" type. A
package (PKG) key 154 is then pressed, whereupon the micro computer will present a menu ~or selection via the numeric pad of the different packages that are available. Such selection actuate~ the microcomputer block to provide the offsets and ;. time delays required to make the internal device equivalent to - ~4 ~Lb 32;2 the external device, and to set ~he test period that will result in a satisfactory test.
The use of microcomputer control of the hardware segments of the test apparatus also permits the storage of a test sequence, as is required for example for the examination of a circui~ boaxd carrying a number o different devices. This can be accomplished using a "scratchpad" random access memory (R~M) of the computer block~ in which case the test sequence that is entered will be lost when the apparatus is powered down. Alter-natively, if the apparatus is employed frequently or principally to test a particular board then that test sequence can be stored in the computer block by a progr~ble read only memory unit (PR~M).
- If the operator wishes to test with a PROM stored test sequence it is only necessary to press a sequence (SEQ) k~y 156 when a sequence identification will be produced by~th micro-computer on display 34, or a menu will appear if more than one sequence is stored. In this sequence mode the operator places the clip 10 on the first test device and presses test key 38 whereupon~the device will be tested. Once the device passes or fails the test the clip is passed to the next device and the next and test keys are pressed again. It will be seen therefore that such a sequence can be conducted by a relatively unskilled operator using only an assembly diagram from which the necessary information has been pre-inserted into the PROM.
A temporary test sequence or program i3 inserted by operation o program ~PROG) key 158, when the display 34 will advise that the apparatus is ready to accept the program ,:~
! `1., -- 2~ --and gives it a label. The identification for the first device is entered via the numeric pad and, if present in the library, this is entered in the se~uence in the microcomputer RA~. The operator then presSes a "next" key 160 and enters the identifi-cation for the second device, this procedure being continuedto the end of the sequence when an End key 162, used to indicate the end of any data insert:ion, is pressed. This sequence is now recalled by pressing sequence key 156 and proceeding as with a PROM recorded sequence.
The apparatus încludes the usual clear entry key 164 that is used to clear the immediately preceding entry if it has been incorrectly entered. A reset keyl66 is also provided in case at any time the operator wishes to terminate the mode in which the apparatus is operating. A selftest (STSTl key lS 168 is also provided for the usual self-testing procedures that are available via the microcomputer.
~ . , ~6 -~'b Drawings accompan~ing supplementar~ Di,sclosure FIGURE 8 is a detailed logic circuit for implementing the logic diagram of Figure 7, FIGURE 9 is a detail from the external interface block of Figure 2 and also illustrates an alternative embodi-ment for obtaining offset of the input logic signals, FIGURE 10 is a detail from the internal interface block of Figure 3 to show a specific structure or control blocks therein, and FIGURE 11 is a detail from the library block of Figure 4 to show the generation of a toggle signal from a toggle logic block thereof.
~ ~73~
, SUPPLEMENTARY DISCLOSURE
Fi~lre 8 illustrates one form of logic circuit to implement the logic diagra~ of Figur~ 7; ~s indicate~ above, in practice there are many different ways in which the circuit can be arranged depending upon the logic chosen by the desiyner. This circuit ~se~
! s 21 multi-input NAND module~ 184 ~hrough to 224~ 12 inverters 226 through to 24~ a~d 4 NOR modules 250 through to 255 connected as shown. Since all of the elements are ~nteracti~e a ~tep-by-~tep explanation of its function would be prolix and i3 unnece~sary for those skilled in the art. The circuit con~i~ts essentially of three set/reset registers identified by the initials K, L and M.
Register K con~ists of modules 202 and 204, register L con~ists of modules 208 and 210, while register ~ consists of modules 222 and - 224, the remaining modules serving for the control of the~e registers~ The following table correlates the settings of the 15 three registers with the numbered ~tate~ in the logic di~gram of Figure 7.
State K L M
2~ 0 0 7 , 1 0 ~ ~. 1 0 1) 32~
;~
I
Thus it will be seen that to move from ~tate 1 to ~tate 2 the registers K and L remain unchanged (O) whlle regiqter M ls set (1). ~gain to moYe from state 3 to ~tate 4 regi~ters K and L
remain respectively in their unchanged (O) form and set (1) state~
while reyister M must be reset from (1) to (O).
I The setting and resetting of the regi~ter~ al~o requlre~
j ! the following relations to be present~ among the various ~gnal~, ., the period between symbols ~ndicating ~or~:-S ET K = L ~ M ~ FAULT SYSCLX + L ~ M TEST S~NCH SYSCLX
RESET K = RESET + L^ FAULT
SET L = K o M- TEST S'YNCH SYSCLR
RF,SET L = RESET + K ~ M- FAULT S'XSCLK
'~, SET M = K L TEST ~ L FAULT ~ ~- L- FAULT o S~SCI.R
RESET M = ~ESF.T + K ~ L FAULT + K L - FAULT SYSCLK
~eferring now to Figure 9 a preferred form o amplifier 54 for the external interface block consists of a field effect transister (FETJ 160 which receives the input from a respective pin of the clip 10~ inverts it and feeds it to an NPN tran3ister 162, the output of which feeds on line 56 to the off~et module~
58 or, in an alternative embodiment illu~trated by thi~ figure, directly on the output line 60 to the IoI~ block 16. The signal level changing modules 58 can for example con3i~t of output device~
that are switched on and off by the input signals thereto and produce corre~ponding output signals of the required TTL logic levelsO Such an arrangement permits individual control of th~
signal levels from each pin but may not be neces~ary, when the simpler system of Figure 8 can be adopted. Thus, the offaet data from the microprocessor 26 takes the form of an eight bit string, and upon selection of the respective device to be tested, this is ~ed to a shift register 164, the outpu~ of which feeds a digitaL/analog converter 166, the output of which is Eed to an amplifier 168. The amplifier output is fed to the ground of the board on which the device being tested is mounted and shift~
the ground voltage o that board to a valve such that the signals ed to all of the amplifiers 54 are within the required logic levels to be handled thereby.
Referr.ing now to Figure 10, which illustrates a specific circuit or the control blocks g2 o~ Figure 3, each of the switches ~0 therein consiClts ~or example of an individually controllable tris~ate bu~fer 8uch aB the ~4126 device sol~ by Texa~ Ins~rument~.
The Y and Z r~yi~ltera feed re~pectLve dual input NO~ gatea 170 ., ~,~
_.~ ........
f~
and 172, the toggle signal rom cor-trol block 24 being fed to gate 170 with the Y bit, while the output of gate 170 is fed to gate 172 with the Z bit. ~n inverter 174 i~ connected between the control terminals of switches Cl and C2. The settiny for s an input signal is a positive bit from the Z register 80 that the I output of NOR gate 172 is low and Cl i~ disabled; the low ~ignal -~' is inverted by inverter 174 and C2 and C3 are enabled; the . presence of a bi~ from Y i~ immaterial. The ~e~ting for a pure output signal is Z=0 and ~=1 when NOR 17Z has an output enabling Cl and disabling C2 and C3. With both Z=0 and Y=0 then the state of the switches Cl to C3 depends entirely upon ~he toggle signal supplied to gate 170. System restart II for synchronisation is ,~ obtained by applying the signal via diode 176 to disable switch C3 and thereby prevent the input signals from accessing ~he library block.
;; Referring now to Figure 11, any device to be tested of the type which any of the pins can be alternatively input or output requires a respective toggle logic block 121 to generate the toggle signal that is to be supplied to the internal interface block 16. The arrangement of one such block will now he described.
By way o example only it i~ assumed that the device to be tested is logically simple, in which outputs are obtained on its output pins, su~h as pin 10, onl~ when signals Sl and S2 on it3 control pins 1 and 7 are both zero; if Sl or Sz or both are 1 then the output pin 10 is "tristate~ i.e. of very high impedance, ~o that any ~ignal~ applied thereto rom other devices on the bus will be ; ignored. The ~logic block~ lZl ~or ~uch an example reducee to A
_ ~ _ ....
~L.~d ~ QJ~
sin~le NOI~ ~ate 17~ having it~ inputs connected to the pin~ S1 and S2 and its output fed to a contro]lable tristate buffer 180 which is powered when the respective device is powered and permitn the toggle signal to be fed to the internal interface block~ The S logic block therefore produces a toggle sigrlal logic "1" when the ~wo input signal Sl and S2 are ~ero, and at all other times will produce toggle ~ignal logic 2ero to be fed to the gate~
170 of Figure 10.
The high speed mem~ry latches of the C.F.D. block 18 are for example the D-Flip-Flops Type 74273 o Texa~ Instruments which upon receipt of a signal will hold that signal by remaining in the state to which it wa~ changed by it. The comparator gates are exclusive OR modules type 7486 of Texas Instruments~ while the forty element detectors are assembled using for each eight 5-input NOR modules each feeding the input o an 8 input NAND module.
;
i
T~lrning now to F'igure 1, the jaw contacts of such a clip 10 are connected via a cable 12 to corresponding contacts of an external interface (E.I.) block 14, which is in turn connected to an internal interface (I.I.) block 16. Signals from the I.I. block may pass di.rectl~ to a comparison and fault detector (C~F.D.) hlock 18, or may go to a library block 20, as will be described belo~. Signals also pass from the library block 20 to the C.F.D. block 18 and signals indicating the "status" of each of the pins of an element under test are passed from the C.F.D. block 18 to a display ~lock 22, which in this embodiment gives a visual display. It will be understood that for example in an embodiment employed in an automatic test facility such a visual display may not be necessary and may be omitted or replaced by some other unit as required by the purchaser for indicating that the tested element has passed or failed the test and/or taking some action depending upon pass or failure of the test.
Certain control functions to ~e described below, particularly those required during a test, are performed by a control block 24, which has direct access to the I.I. block 16 and C.F.D. block 18, while other functions required in preparation for and following a test are performed by a microcomputer 26, which has direct access to all of the block with the exoeption of ~le display block 22. Microcomputer 26 also has access to a user interface block 28 including a keyboard and alphanumeric display by which a human operator can insert necessary information into ; the apparatus and al.so receive information, prompts and commands there~rom. As with display block 22, the configuration of the user interface block 28 will also depend upon whether a human operat~r is required, or whether the test apparatus is being run by a machine. The function of each of the above-~escribed blocks and their inter-relation with one another will be described below.
The operation of apparatus of the inventlon depends upon the presence in the librar~ block 20 of a device or element that is a duplicate of the device to ~e tes~ed, or that can be made to operate as ;f it were a duplicate of the tested device.
Such duplication of the tested device may be for example by adjustment of the voltage levels and/or timing of the input/
output signals involved. This may be contrasted with test apparatus of the kind employing a microcomputer in which the microcomputer software or firmware is written so that the micro-computer will simulate the device under test, requiring complete and detailed information as to the operation of the device as well as the signals involved in its operation.
The library block consists of at least one board, usually a plurality of boards, each of which has connected to the busbars thereof a plurality of devices that are to be tested, all wired`to the busbars to permit individual access to each element and also to the pins of each element as required. Each such board can consist, for example, of a group of dissimilar elements all from the same manufacturer, or a group o~ similar elements, one from each of the available manufacturers, or a group o~ devices all of the same technology e.g. TTL; MOS; CMOS;
DTL; ECL, etc. Again, each library board can be as identical , as possible in content and layout to a circuib board that is . . .
to be tested, ~nd this is particularly valuable in ensuriny that heating conditions, time delays, intercouplings, leakages, etc.
will be as nearly as possible the same.
Each library board also includes a read only memory means connected to appropriate bus~ars of the ~oard and containing necessary information for each element on the board, such as lts index number ~or operator identification, the identi-fication of the ~oard on which it is mounted, the library board bus coordinates t~at must be enabled and accessed to power the element and access its terminals, the status of each of the terminals of the element ~.e. whether it is an input, output or bidirectional terminal), the voltage bias levels required for operation, the speed of operation and the corresponding time delays that may be required for its signals to be compared with those of the test device, and the time required for a complete test of its operation. For economy in manufacture this memory preferably is a single central unit for the whole board, but of a type that can be re-programmed when required if any of the devices on the board is replaced by a different device.
Let it first be assumed that a human operator is to test a single element on a board having a clock signal that is directly usable by the test apparatus and of a kind that does not require a reset si.gnal for its operation~ Before commencing the test the operator will interrogate the test apparatus via the user interface 28 to determine whether or not the same or an equivalent device is in the library block. Each device to be ., 9 tested and the reference device are identified to the operator by the above-mentioned identification number stored in the respective library board memory. rrhe operator supplies this number to the microcomputer 26 via a numerical keypad 30 in the user interface 28 and then presses the search (SRCH) key 32, causing the microcomputer to search the library memories and display on an alpanumeric display unit 34 in t~e user interface 28 whether or not the device is in the library, and if so the library board on which it is located. If the search does not find a device with this identification the computer will provide the display unit 34 with an appropriate display such as "not available".
Once assured that the device can be tested the operator now connects EX CLK lead 35 to the board on which the device is mounted to receive the clock signal, connects ground lead 36 to the board bround, puts clip 10 on to the device and p~esses enter key 37 to enter the devioe identification data as shown on the display 34.
The microcomputer now interrogates the respective library memory unit for the pertinent information on the selected device and also powers the selected device, so that it is in the same condition of operation as the external test device. At the same time the data about the selected device is employed by the micro-computer to set the E.I. block 14 to provide the required bias voltages; ~o ,set the I.I. block 16 so that it will properly route the signals it receives, as will be described below, and to set the control ~lock ~4 so that the latter will initiate and control a testing cycle for the selected device~ This data ~ o 3~'~
about the selec~ed device will be stored in suitable registers which may be provided in the microcomputer block or in the respective block to which the data has been transferred. If the register is in the respective block then once the data has been transferred to it the microcomputer can disable itself from further access to that register until there is a need to replace the data for a new test device. ~laving performed these functions the microcomputer enters on the display 34 an indication that a test is possible and then, except forvarious accessory functions described below, disables itself from taking any further part in the test per _ .
The test element is in active condition in its circuit~
which must be powered up for the test to be possible, so that the element is receiviny the input signals and power supply or supplies that are available to it from its own board; the element will also be delivering output signals to the respective output terminals which, if the element is functionlng properly, are appropriate for the input signals and power that it is receiving. As described above the signal at a particular terminal pin of the test element will be supplied via clip 10 to the external interface, where its level will be changed if necessary as previously set by the microcomputer. If it is an input signal it is routed automatically by the I.I. block 16 to the C.F~D. block and also to the corresponding terminal pin ~-~ of the library reference device and becomes an input to that device. If it is an output signal it is routed automatically by the I.I. block 16 to the C.F.D. block 1~ and is preven~ed from / I
access to the library reference element. If the signal is changing from input to output then in input mode it will be routed as above for an input signal while in output mode it will be routed as above for an output signal under control of a "toggle"
signal supplied to the I.I. block 16.
Upon the operator pre~sing the test key 38 the control block 24 will now operate the I.I. ~lock 16, the library block 20, and the C.F.D. block 18 to scan synchronously and simultaneously the pins of the external device and the same pins of the library device. The input signal on any input pin of the test device will be routed by the I.I. block 16 to the library reference device, while the output signal on any output pin of the test device will be routed directly to the C.F.D.
block 18 to be compared with the signal from the same pin of the library reference device. It is usually preferred for a complete test to scan over a relatively large number of cycles since, in general, each such cycle takes only a small fraction of a second and the total t~ for an exhaustive test is very sm~ll as co~pared with the time required to ve the clip 10 from one element to another. In the case when one or more of the pins are bi-directional a plurality of scans will be required until the device has been tested in all possible states, the I.I. block 16,routing the signal as required in dependence upon whether it is an input or an output.
The C.F.D. block 18 comprises a bank of comhinatorial logic elements, forty in this particular embodiment since forty pin devices are to be tested, each of which compares the signal from the respective pin of the test device with that from the corresponding pin of the library reference device and feeds any _ ~ _ / '~
3'~
~., ~
output to a respective one of forty indicator devices 40 in the display block 22. Thus, if any one of the combination logic elements is fed two different digital signals the respective indicator will be actuated to show a fault condition on that pin, whereupon the operator will know not only that the device is faulty, but the pin or pins at which the fault or faults is occurring An audible signal may also be employed to alert the operator that a fault is present. The clip can then be moved to another similar device and the test button 38 again pressed to obtain a test of the new device, and so on. At any time the status of the pins and whether or not a fault is present can be read by the microcomputer and this information supplied to the interface 28 or some other external apparatus.
It was assumed above that the devioe under test en~plc~ed the clock signal frcm its c~n board, but frequently this is not the ~ase, and a cloc~ signal or c~mplen~ntary clock signal can be supplied from the micro-c~mputer via the E.I. block 14 through respective leads 42 and 43, while a reset signal is supplied when required from the same block under cor~trol of the microcomputer through a lead 44~ The direction of the clock signal to be supplied from the test apparatus is selectable, depending upon whether triggering occurs on the rising or falling edge of the clock pulse. The information as to what clock signal is required will be in the library memory, but needs to be fed to the microproeessor as an instruetion. The operator therefore presses a eloek key 46, whereupon the mic:roprocessor will display the clock requirement for the deviee and a menu for operation of the numeric pad 30 l3 to ob~ain the necessary signal; for example the menu will instruct the operator to press "1" for the microprocessor internal clock to supply the device with a clock signal of one polarity, press "2" for an internal clock signal with opposite polarity; and press "3" if an external clock signal is already provided.
It may be found that the external clock signal is too fast to be usable or for convenience in testing, in which case the internal clock will be used at a speed set by the micro processor and determined from the information in the library.
The library information conveniently is stored therein in the form of the preferred frequency and preferred number of cycles for the test: upon reading this information the microcomputer will calculate the test duration required and terminate the test cycle upon expiry of this time. The microcomputar includes a frequency counter unit which is actuated by operation of a frequency key (FREQ) 48, whereupon the display 34 will display the usual frequency and polarity of the clock that is in use.
Upon the operator pressing a time key 50 the micro-computer will show on the display 34 the duration of the test tobe made and a menu to change the time if this is not satisfactory. The required test duration is selected by keying the number of milliseconds via the numerical pad 30 and then pressing the enter key 36. This feature is used, for example, if the fault is known to be intermittent, or if a longer test time than usual is required, e.g. for a soaking test.
The circuits and logic arrangement of the various blocks _ ;~ _ 1~
~l97322 will now be described in greater detail, other ~eatures of the apparatus also being described where this is appropriate~
External Interface ~lock 14 This constitutes a buffer of high input impedance between the test apparatus and the device being tested, so as not to unduly affect the operation of the test device, and also acts as a level translator to enable the test apparatus to deal with families of devices other than those used in the apparatus blocks. Thus, this particular preferred embodiment predominantly employs TTL logic devices in its construction and in the absence of the interface block 14 could only conveniently test other TTL logic devices, since other types requiring different logic thresholds might not give signals that could be handled by the test apparatus. Part of the information stored in the l.ibrary memory on each library board and supplied by the microcomputer to the external interface block is the bias level offset required to translate the digital signals received and transmitted by the E~I. block to the standard levels for TTL
logic devices of a maximum of 008 volts for "0" and a minimum of 2.4 volts for "1". The operator presses a bias key 52 to be told the offset that has been given to the E.I. block by the microcomputer for the test device together with a menu for change if this should prove necessry. If necessary the number of millivolts of change required is set by the key pad 30 and entered by pressing the enter key 36.
Referring now to Figure 2, which shows in greater detail the circuit of the external interface block, the forty leads in the cable 12 and the single clock lead 35 feed their signals to 1S' ~732~
respective high input impedance buffers 54, whilP the corres-ponding forty one separate output leads 56 feed their signals to respective offset modules 58, each of which will accept the digital signal received on lead 56 and feed the corresponding TTL logic signal out on its output lead 60 to the I.I. block 16.
An internal power unit (not shown) provides each offset module on input leads 62 and 64 respectively with the voltages appropriate to produce a TTL logic "1" or "O" on the output lead 60. The offset data from the microcomputer is also fed via a lead 66 to a shift register 68, which controls the output of a digita~
analog converter and driver 70 to produce a ground reference voltage for the signals from the offset modules. This analog ground signal is fed to a ground detector 72 which is also connected to the external ground lead 36. Upon detection of current flow between the two grounds the detector transmits a signal via lead 76 to the microcomputer that a ground refer-ence is available and the test may proceed, and otherwise not.
Internal Interface Block 16 Referring now to Figure 3, which shows in greater detail the circuit of the I I. or routing block 16, each output lead 60 from E.I. block 14 constitutes an input lead to a respective set of three controlled switch devices 80 (designated Cl, C2 and C3 respectively) which set is controlled by a respective control block 82. The input to each control block 82 i5 from two separate 40-bit registers 84 and 86, _ ~ _ /~
.~
:, . .
~3'732;~
called respectively the Y and Z register, which are ~upplied with the required information as to the status of the respective device pin from the library memory via the microcomputer 26.
The bit signals received by each control block 82 from the X
and Y registers is used in combination with a toggle signal received from the lihrary block via lead 88 to issue the necessary control signals to the switches Cl, C2 and C3. The two bit YZ
input specifies whether the signal is an input or an output or a toggle, and the incoming toggle signal will in the latter case make the final determination hetween input and output as required. Thus, if the incoming signal is an input then the two switches C2 and C3 are closed while the switch C~ is open and the signal is fed via leads 90 and 92-to the C.F.D. block 18 and via lead 94 to the library block 20. If the incoming signal is an ou~put then the two switches C2 and C3 are open and the switch Cl is closed, whereupon the signal from the E.I. block 14 cannot acoess the library devioe, but can ~ccess the C.F.D. block 18 via lead 92, while the oorresponding output signal from the ~ rary devioe can return to the I.I. block vla lead 94 and access the C.F.D. block via the lead 90.
A special situation arises when the device to be tested is of a kind, such as a shift register, which must be synchronised with the library device. In such case each control device 82 is issued a "synchronous mode" signal via lead 96; in this mode with an input signal the switches Cl and C3 are now open while switch C~ is closed so that the signal can only input the C.F.D. block 18 via leads 90 and 9 and is blocked from the library devioe via lead 94, while with an output signal the switch Cl is closed and l7 ~J ~
both switches C2 and C3 are open so that access to the library device from the E.I. block is ~gain prevented while the library device can feed to the C.F.D. block 18 via leads 94 and 90. The library device is therefore inactive in a specîfic pattern and the C.F.D. block will detect this as a fault~since it is immaterial to that block whether the "fault" is in the test device or the library device; the test devic2 will cycle through different patterns and upon achieving a pattern corresponding to the "frozen" pattern of the library device the "fault" indication will 10 disappear and the two devices now operate ln synchronism. The C.F.D. block is controlled by the control block to ignore this "fault" for a pr~determined period of time and if synchronisation is not achieved with this period the control block 24 then issues a restart signal to the cycle control to indicate this failure 15 and put the apparatus in standby mode; at the same time the micro-computer block will provide an instruction "failure to synchronise"
on the display 34, since the most likely reason is of course a faulty device.
Library ~lock 20 Figure 4 is a more detailed circuit drawing of a part of one library board in the library block although, as will be understood, a typical embodiment of the invention will usually comprise a number of diferent boards. As described above each board 98 includes a read only memory 100 connected by leads 102 2S and 104 respecti~ely to the address and data busses of the micro-computer so that it can be interrogated and transfer its stored information to the microcomputer ~or utilisation and display.
Ig ~:~ffl73~.
When the computer block has identified the device to be selected, either by a preset program to be described below, or by an operator feeding this information to the computer block, the computer block will issue a "select board" signal on lead 106 to a control logic device 108 that will in turn close a switch 110 permitting power to be supplied to the board. At the same time the computer block issues a "select device" signal on lead 112 to a register 114 that in turn will cause closing of a respective switch 116 that will permit the powering up of the selected library device 118 corresponding to the test device.
Each library device is connected via a board bus 119 to a library block bus 120 and by the leads 94 to the I.I. block 16.
If the selected device is of a type in which one or more of the pins is bidirectional then ~he board also carries a respective toggle logic block 121 arranged for that device and ~hich is selected by closing of the respective switch 116, this block feeding the toggle signal as described above on leads 88 to the I.I. block 16.
Since the test apparatus itself employs TTL logic devices such devices in the library are immediately compatible with the test apparatus circuits and can be connected directly to the board bus 119 and thence to the library bus 120. Devices such as device 122, corresponding to test devices that require offset voltages to be provided by the E.I. block 14, cannot be directly connected in this manner because of this inherent incompatability; instead they are connected to a sub-bus 123 that is connected to the board bus 119 via driver 124 providing to the sub-bus 123 73~3~
the voltages required for proper operation of the device, this driver being enabled by the ~oard select signal.
C.F.D. Block 18 Turning now to Figures 5 and 6 the C.F.D. block receives signals from the library block 20 via leads 90, and from the I.I. block 16 via leads 92; these signals are fed to respective high ~d nem~ry elements (lat~hes) 126 and 128, also labelled Ll and L2, and ~hence to a respective combinatorial logic element 130. The output from each element 130 is fed to a respective high speed memory element (latch) 132, also labelled L3.
If the digital signals received by an element 130 do not correspond it detects the lack of correspondence as a fault and activates a driver 134 that lights the respective lamp 40 in the display block 22. The outputs o all of the elements 130 are fed to a combination detector de~ice 136 that feeds a "fault detected" signal on-lead 138 to the microcomputer, so that it will give an indication of a fault detection. The device feeds a corresponding signal c~ lead 139 to the C.F.D. block, so as to "stop" the test immediately with the fault or faults indicated, since otherwise the test might move on to a situation where there is no fault and the fault indica~ion would be lost.
At the same time all the outputs are fed to a multiplex detector register 140 that can be interrogated by themicro.computer via leads 142 to determine which of the device pins have been detècted as faulty and provide a read~out either on the display 34 or some ~73~'~
equivalent unit, e.g. a printer.
Owing to the high speed at which the apparatus operates it is necessary to contro:L the operation of the latches 126, 128 and 132 so that the signals ~re sampled during precisely controlled time periods. This arrangement also permits compen-sation for the differing propagation times of signals through the various components from which the apparatus itself is assembled. It also widens the test capability of the apparatus in ~hat devices of the same configuration but of different families, and thereof of dif~erent response speeds, can be tested without the need for exact correspondence between the test and library devices. For example a TTL library device can be used to test a Schottky (fast TTL) device of the same configuration.
A high speed clock 144 feeds a ripple counter 146 which produces the necessary large number of uniform pulses. Inform-ation as to the time delays tdl, td2 and td3 required for the particular device are supplied by the microcomputer block to a register 1~8 after this information has been extracted by it from the R.O.M. 100 in the respective library board. The counter 146 and register 148 feed a comparator 150 which in turn feeds the selected pulses to a control logic module 152 that is also fed with the appropriate clock signal to synchronise its operation with the test device Referring to Figure 6 a pulse 25 is fed after time delay tdl rom the start of the respective clock cycle to open latches Ll and the signals from the ~.I.
block 16 are sa~pled during the period Pl. Latches L2 ~1 ~ ~ ~a~
are opened for another period P2 that occurs after time delay td2 to sample the signals from the library block 20, while latches L3 are opened for a last period P3 that occurs after time delay td3 to sample the outputs of the com~ina~orial logic devices 130. All three pulses occur within one clock cycle and there is no overlap between them, so that the actual speed of operation of the tested device and the propagation times through the apparatus a~e immaterial as long as this condition can be fulfilled. In a particular preferred embodiment operating at 10 Mhz the length of one clock cycle will be 100 nanoseconds and each pulse will typically have a duration of 15 nanoseconds.
Control Bl ock 24 Referring now to Figure 7 which is a logic diagram to show the manner in which the control block is employed to control the other blocks of the apparatus and to issue control signals to those other blocks as requiredO The control block of the preferred embodiment is of pulsed asynchronous logic config-uration employing TTL Schottky NAND logic gates of the 74S-family e.g. 74S00; 74S04; 74S10; 74S20 and 74S30. Other families and other logic systems can of course be employed, as will be fully apparent to those skilled in the art.
Upon powering-up of the apparatus it is required to be in stand-by mode represented by state 1. If the apparatus is not already in this state then the required prompt is not provided by the microcomputer and accordingly it is dri~en to the state by the operator pressing a reset key 166, whereupon the microcomputer will issue the necessary instruction signal to the logic~ If the operator now presses the test key 38 the microcomputer will issue its test signal that will cause the logic f ~
~.~7~
to move asynchronously to state 2, also called system reset I.
In this second state the input/outputs to the library block are enabled and those to the C.F.D. block are disabled; also an external reset signal is applied to the test device if it is of the type that requires such a signal.
For devices not requiring an external reset signal, such as simple logic ~ates, the logic can move directly to Test state 7 in which all inputs/outputs are enabled together with the C.F.D. block 18, provided the fol:Lowing conditions are met:
a) a test has previously been initiated (I'EST) b) the external system clock is at iogic zero (SYSCLK), and c) the device has been determined previously by examination of the library block memory to be of the type not requiring an external reset (SYN).
Assuming that the logic is now in state 7, if now a fault is detected, the logic moves to state 8 in which all the inputs/outputs are disabled to stop or "freeze" the apparatus in the fault condition, while all accumulated information from the cycle with regard to the fault is held, so that it can be examined and displayed by the slower-operating microcomputer. A
return to stand-by state 1 is only obtained by issue of the reset signal, for example by the operatorO If no fault is detected then upon expiry of thP test period the logic issues a reset signal to return to state 1.
If synchronisation is required at state 2 then the necessary information comes from the library block as described above and with the presence of only conditions a) and b) above .....
~3 ~7~2~
the logic is now moved to state 4~ where the necessary check is made for synchronisation. ~s described a~ove the lack of "synchronisation" is detected as a "fault'~, but the logic is not axmed to drive the apparatus into "fault state" as in the asynchronous loop contain;ng state 8. Upon detection of this "fault" the logic drives immediately asynchronously to state 3, which is also called system restart 2. In this state 3, as was described above, all inputs into the library block are disabled, but all outputs are enabled and compared, so that the library devlce is "inactivel'. As soon as synchronisation is obtained there is no ~' fault" detected and with the system clock at logic zero the logic returns ~o skate 4; this loop can of course repeat and also state6 5 and 6 are employed to confirm that synchronism has ~een achieved, to take account for example of "glitches" on the clock lines giving false clock indications.
States 5 and 6 are operative on opposite levels of the clock signal and if a "fault" is still present at either of these stations the logic will return immediately to station 3 and the cycle repeated. If there is no "fault" indication at state 6 and the system clock is at the required higher level then the logic passes immediately to state 7 and the test takes place.
To avoid "lock-out" of the logic in any of the states provision is made for the application of a reset signal at each station that will drive the logic to standby state 1 for the sequence to be repeated~
~'t 3~
Microcom~uter slock As will be apparent to those skilled in the art from the description of the apparatus the per~ormance required for the microcomputer block is well within the capability of many currently available units. The particular preferred embodiment described employs an Intel 8085 based central processor unit together with four No. 2716 EPROMS each of two kilobytes capacity; four No.
2114 static RAMS each of two kilobytes capacity; and three No.
8155 static R~MS each of 1.5 kilobytes capacity and 16 I~O ports to provide a total of 48 I/O ports.
It will be seen that all of the different blocks of the apparatus can be constructed using hardware only, since their individual functions are fixed, and the only software and/or firmware needed is in the microcomputer, which can ~e a readily 1~ available unit. Moreover the speed of operation of the various blocks, and therefore of the complete apparatuS~is independent of the speed of operation of the microcomputer, which typically is much slower than is possible with a hardwàre-only block.
For example, as described above a preferred minimum speed of operation of the hardware of the preferred embodiment during a test is at l0 Megaherz; the operating speed of a suitable microcompute~
is about 4 Megaher~, but each instruction of the microcomputer requires at least several machine cycles for its execution, so that its actual operating speed is only a fraction of the speed 2S of which the test apparatus is capable. This slower speed of the computed block is immaterial since the testing by the hardware portion o the apparatus is independent of the computer. The ~, , -- 2~ --73~
resultant apparat:~ls can therefore readlly be provided as a "turn-key" unit not requirin~ any software programming by the user.
A parti.cularly advantageous characteristic o~ the apparatus of the invention is that it is not necessary to know the internal construction or mode of operation of the test device for it to be tested successfully, as long as information is available as to the status of its pins during operation.
The apparatus can therefore be used to test a proprietory or military device for which the manufacturer is unwilling or unable to provide information as to its operation, and used to test a batch of devices whose operation is unknown as long as one can be sure that a correctly functioning device can be selected to serve as the library device.
Because of the possibilities described above of testiny external devices making use of an internal library de~iice that is equivalent but of a different family, the library device having one identification may also be identified as.corresponding to a number of different configurations, usually referred to as packages. This information is stored in the respective library R.O.M. 100 and will be displayed by the miCrocoMputer block on the display 34 upon interrogation of the memory, which will show that the device in the li.brary is of "packa~e" type. A
package (PKG) key 154 is then pressed, whereupon the micro computer will present a menu ~or selection via the numeric pad of the different packages that are available. Such selection actuate~ the microcomputer block to provide the offsets and ;. time delays required to make the internal device equivalent to - ~4 ~Lb 32;2 the external device, and to set ~he test period that will result in a satisfactory test.
The use of microcomputer control of the hardware segments of the test apparatus also permits the storage of a test sequence, as is required for example for the examination of a circui~ boaxd carrying a number o different devices. This can be accomplished using a "scratchpad" random access memory (R~M) of the computer block~ in which case the test sequence that is entered will be lost when the apparatus is powered down. Alter-natively, if the apparatus is employed frequently or principally to test a particular board then that test sequence can be stored in the computer block by a progr~ble read only memory unit (PR~M).
- If the operator wishes to test with a PROM stored test sequence it is only necessary to press a sequence (SEQ) k~y 156 when a sequence identification will be produced by~th micro-computer on display 34, or a menu will appear if more than one sequence is stored. In this sequence mode the operator places the clip 10 on the first test device and presses test key 38 whereupon~the device will be tested. Once the device passes or fails the test the clip is passed to the next device and the next and test keys are pressed again. It will be seen therefore that such a sequence can be conducted by a relatively unskilled operator using only an assembly diagram from which the necessary information has been pre-inserted into the PROM.
A temporary test sequence or program i3 inserted by operation o program ~PROG) key 158, when the display 34 will advise that the apparatus is ready to accept the program ,:~
! `1., -- 2~ --and gives it a label. The identification for the first device is entered via the numeric pad and, if present in the library, this is entered in the se~uence in the microcomputer RA~. The operator then presSes a "next" key 160 and enters the identifi-cation for the second device, this procedure being continuedto the end of the sequence when an End key 162, used to indicate the end of any data insert:ion, is pressed. This sequence is now recalled by pressing sequence key 156 and proceeding as with a PROM recorded sequence.
The apparatus încludes the usual clear entry key 164 that is used to clear the immediately preceding entry if it has been incorrectly entered. A reset keyl66 is also provided in case at any time the operator wishes to terminate the mode in which the apparatus is operating. A selftest (STSTl key lS 168 is also provided for the usual self-testing procedures that are available via the microcomputer.
~ . , ~6 -~'b Drawings accompan~ing supplementar~ Di,sclosure FIGURE 8 is a detailed logic circuit for implementing the logic diagram of Figure 7, FIGURE 9 is a detail from the external interface block of Figure 2 and also illustrates an alternative embodi-ment for obtaining offset of the input logic signals, FIGURE 10 is a detail from the internal interface block of Figure 3 to show a specific structure or control blocks therein, and FIGURE 11 is a detail from the library block of Figure 4 to show the generation of a toggle signal from a toggle logic block thereof.
~ ~73~
, SUPPLEMENTARY DISCLOSURE
Fi~lre 8 illustrates one form of logic circuit to implement the logic diagra~ of Figur~ 7; ~s indicate~ above, in practice there are many different ways in which the circuit can be arranged depending upon the logic chosen by the desiyner. This circuit ~se~
! s 21 multi-input NAND module~ 184 ~hrough to 224~ 12 inverters 226 through to 24~ a~d 4 NOR modules 250 through to 255 connected as shown. Since all of the elements are ~nteracti~e a ~tep-by-~tep explanation of its function would be prolix and i3 unnece~sary for those skilled in the art. The circuit con~i~ts essentially of three set/reset registers identified by the initials K, L and M.
Register K con~ists of modules 202 and 204, register L con~ists of modules 208 and 210, while register ~ consists of modules 222 and - 224, the remaining modules serving for the control of the~e registers~ The following table correlates the settings of the 15 three registers with the numbered ~tate~ in the logic di~gram of Figure 7.
State K L M
2~ 0 0 7 , 1 0 ~ ~. 1 0 1) 32~
;~
I
Thus it will be seen that to move from ~tate 1 to ~tate 2 the registers K and L remain unchanged (O) whlle regiqter M ls set (1). ~gain to moYe from state 3 to ~tate 4 regi~ters K and L
remain respectively in their unchanged (O) form and set (1) state~
while reyister M must be reset from (1) to (O).
I The setting and resetting of the regi~ter~ al~o requlre~
j ! the following relations to be present~ among the various ~gnal~, ., the period between symbols ~ndicating ~or~:-S ET K = L ~ M ~ FAULT SYSCLX + L ~ M TEST S~NCH SYSCLX
RESET K = RESET + L^ FAULT
SET L = K o M- TEST S'YNCH SYSCLR
RF,SET L = RESET + K ~ M- FAULT S'XSCLK
'~, SET M = K L TEST ~ L FAULT ~ ~- L- FAULT o S~SCI.R
RESET M = ~ESF.T + K ~ L FAULT + K L - FAULT SYSCLK
~eferring now to Figure 9 a preferred form o amplifier 54 for the external interface block consists of a field effect transister (FETJ 160 which receives the input from a respective pin of the clip 10~ inverts it and feeds it to an NPN tran3ister 162, the output of which feeds on line 56 to the off~et module~
58 or, in an alternative embodiment illu~trated by thi~ figure, directly on the output line 60 to the IoI~ block 16. The signal level changing modules 58 can for example con3i~t of output device~
that are switched on and off by the input signals thereto and produce corre~ponding output signals of the required TTL logic levelsO Such an arrangement permits individual control of th~
signal levels from each pin but may not be neces~ary, when the simpler system of Figure 8 can be adopted. Thus, the offaet data from the microprocessor 26 takes the form of an eight bit string, and upon selection of the respective device to be tested, this is ~ed to a shift register 164, the outpu~ of which feeds a digitaL/analog converter 166, the output of which is Eed to an amplifier 168. The amplifier output is fed to the ground of the board on which the device being tested is mounted and shift~
the ground voltage o that board to a valve such that the signals ed to all of the amplifiers 54 are within the required logic levels to be handled thereby.
Referr.ing now to Figure 10, which illustrates a specific circuit or the control blocks g2 o~ Figure 3, each of the switches ~0 therein consiClts ~or example of an individually controllable tris~ate bu~fer 8uch aB the ~4126 device sol~ by Texa~ Ins~rument~.
The Y and Z r~yi~ltera feed re~pectLve dual input NO~ gatea 170 ., ~,~
_.~ ........
f~
and 172, the toggle signal rom cor-trol block 24 being fed to gate 170 with the Y bit, while the output of gate 170 is fed to gate 172 with the Z bit. ~n inverter 174 i~ connected between the control terminals of switches Cl and C2. The settiny for s an input signal is a positive bit from the Z register 80 that the I output of NOR gate 172 is low and Cl i~ disabled; the low ~ignal -~' is inverted by inverter 174 and C2 and C3 are enabled; the . presence of a bi~ from Y i~ immaterial. The ~e~ting for a pure output signal is Z=0 and ~=1 when NOR 17Z has an output enabling Cl and disabling C2 and C3. With both Z=0 and Y=0 then the state of the switches Cl to C3 depends entirely upon ~he toggle signal supplied to gate 170. System restart II for synchronisation is ,~ obtained by applying the signal via diode 176 to disable switch C3 and thereby prevent the input signals from accessing ~he library block.
;; Referring now to Figure 11, any device to be tested of the type which any of the pins can be alternatively input or output requires a respective toggle logic block 121 to generate the toggle signal that is to be supplied to the internal interface block 16. The arrangement of one such block will now he described.
By way o example only it i~ assumed that the device to be tested is logically simple, in which outputs are obtained on its output pins, su~h as pin 10, onl~ when signals Sl and S2 on it3 control pins 1 and 7 are both zero; if Sl or Sz or both are 1 then the output pin 10 is "tristate~ i.e. of very high impedance, ~o that any ~ignal~ applied thereto rom other devices on the bus will be ; ignored. The ~logic block~ lZl ~or ~uch an example reducee to A
_ ~ _ ....
~L.~d ~ QJ~
sin~le NOI~ ~ate 17~ having it~ inputs connected to the pin~ S1 and S2 and its output fed to a contro]lable tristate buffer 180 which is powered when the respective device is powered and permitn the toggle signal to be fed to the internal interface block~ The S logic block therefore produces a toggle sigrlal logic "1" when the ~wo input signal Sl and S2 are ~ero, and at all other times will produce toggle ~ignal logic 2ero to be fed to the gate~
170 of Figure 10.
The high speed mem~ry latches of the C.F.D. block 18 are for example the D-Flip-Flops Type 74273 o Texa~ Instruments which upon receipt of a signal will hold that signal by remaining in the state to which it wa~ changed by it. The comparator gates are exclusive OR modules type 7486 of Texas Instruments~ while the forty element detectors are assembled using for each eight 5-input NOR modules each feeding the input o an 8 input NAND module.
;
i
Claims (13)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A library module for use in apparatus for the dynamic in-circuit testing of a plurality of different electronic digital test elements comprising:
a circuit board having thereon a plurality of busbars;
a plurality of electronic digital reference elements connected to the said busbars to permit the selective access to the terminals of each reference element; and a memory means connected to the said busbars for access by a memory interrogation means, said memory means having therein information for each reference element consisting of:
a) identification of the respective reference element, b) identification of the busbars that are accessed for access to the respective reference element, c) identification of the status of each operative contact of the respective reference element as to whether it is an input terminal, an output terminal, or bidirectional between an output and an input terminal.
a circuit board having thereon a plurality of busbars;
a plurality of electronic digital reference elements connected to the said busbars to permit the selective access to the terminals of each reference element; and a memory means connected to the said busbars for access by a memory interrogation means, said memory means having therein information for each reference element consisting of:
a) identification of the respective reference element, b) identification of the busbars that are accessed for access to the respective reference element, c) identification of the status of each operative contact of the respective reference element as to whether it is an input terminal, an output terminal, or bidirectional between an output and an input terminal.
2. A library module as claimed in claim 1, and including logic means for each reference element having therein information as to the toggle signal required for the element for determination of the status of each bidirectional terminal as an input or output terminal.
3. A library module as claimed in claim 1, in combination with apparatus for the dynamic in-circuit testing of an electronic digital circuit element employing the module, the apparatus comprising:
means for accessing the terminals of a test element to be tested for the receipt of the respective electric signals at at least the operative terminals of the test element;
said library module;
means for selecting a reference digital element from the said plurality thereof in the library module corresponding to the respective test element to be tested; and signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indication if the comparison indicates the presence of a fault.
means for accessing the terminals of a test element to be tested for the receipt of the respective electric signals at at least the operative terminals of the test element;
said library module;
means for selecting a reference digital element from the said plurality thereof in the library module corresponding to the respective test element to be tested; and signal comparison means for comparing the signals at the said operative terminals of the test element with the corresponding signals at the respective terminals of the reference element and for producing a fault indication if the comparison indicates the presence of a fault.
4. A library module and apparatus as claimed in claim 3, wherein the said selecting means comprises computer means for interrogating the memory means and subsequently powering the selected reference element in the library module.
5. A library module and apparatus as claimed in claim 3 or 4, and including external interface means connecting the said accessing means and the remainder of the apparatus, and means for shifting in the external interface means the voltage level of each signal received from the terminals of the test element to make the resulting output signal from the external interface means compatible with the test apparatus.
6. A library module and apparatus as claimed in claim 3, including timing means for sampling during a first time interval the signals from the terminals of the test element to be tested, for sampling during a second time interval the signals from the terminals of the reference element, and for comparing during a third time interval the said signals from the terminals of the test element and the signals from the terminals of the reference element.
7. A library module and apparatus as claimed in claim 6, wherein the said timing means produce the said first, second and third time intervals during a single clock timing period, and there are provided means for selecting the times of occurrence of the said time intervals during the clock timing period.
8. A library module and apparatus as claimed in claim 3, wherein the said feeding means comprise switch means for each terminal of the test element and the corresponding terminal of the library element, and means for controlling the said switch means in accordance with the status of each terminal of the test device as an input terminal, an output terminal or bidirectional.
9. A library module and apparatus as claimed in claim 8, wherein the said controlling means includes means providing signals indicating the status of each terminal of the test device as an input terminal or an output terminal, and there are provided toggle signal generating means providing a signal to the controlling means for final status of a bidirectional terminal as an input or output terminal.
10. A library module and apparatus as claimed in claim 9, wherein the said library means includes a logic means having therein information as to the toggle signal required for the reference element, and the said apparatus includes means for powering the reference element and its logic means to generate the said toggle signal.
11. A library module and apparatus as claimed in claim 3 or 4, and including means for supplying a clock signal to the test element via the said accessing means.
12. A library module and apparatus as claimed in claim 3 or 4, and including means for supplying a reset signal to the test element via the said accessing means.
13. A library module and apparatus as claimed in claim 3 or 4, and including an indicator for each terminal which is accessible by the said accessing means, and actuating means for each indicator responsive to an indication of the presence of a fault by the said signal comparison means to actuate the respective indicator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000444461A CA1197322A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000444461A CA1197322A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000444461A Division CA1197322A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000444461A Division CA1197322A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1197322A true CA1197322A (en) | 1985-11-26 |
Family
ID=4126842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000444461A Expired CA1197322A (en) | 1983-12-29 | 1983-12-29 | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1197322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1291662A2 (en) * | 2001-05-18 | 2003-03-12 | Sony Computer Entertainment Inc. | Debugging system for semiconductor integrated circuit |
-
1983
- 1983-12-29 CA CA000444461A patent/CA1197322A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1291662A2 (en) * | 2001-05-18 | 2003-03-12 | Sony Computer Entertainment Inc. | Debugging system for semiconductor integrated circuit |
| EP1291662A3 (en) * | 2001-05-18 | 2003-08-06 | Sony Computer Entertainment Inc. | Debugging system for semiconductor integrated circuit |
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