CA1184315A - Extended addressing apparatus and method for direct storage access devices - Google Patents

Abstract

Abstract:

Extended Addressing Apparatus and Method For Direct Storage Access Devices A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.

Description

~8~3~

Title: Extended Addressing Apparatus and Metho~
For Direct Storage Access Devices Background of the Invention:

Fielcl of the Inventiono This invention relates to storage addressing and, more particularly, to apparatus and method for controlling access to the same or different pages of storage by a plurality of direct storage Imemory) access (DMA) channels.

Discussion of the Prior Art:

This invention is an improvement on that of ~OS.
Patent No. 4,374,417, issued February 15, 1983 for METHOD
FOR USING PAGE ADDRESSING MECHANISM by D. J. Bradley et al, of common assignee.

The Bradley references extend the size of memory which can be addressed by an address bus carrying N bits of information from the normal 2 locations to a multiple of 2N by providing a plurality of register means each of which is separately programmable to store data capable of being selectably provided as page signals. Selection of the page registers is made by control signals manifesting the then occurring storage operation, such as instruction fetch, storage read, or storage write operations. Howe~er, the Bradley addressing technique suffers in a system where there exists a plurality of direct storage (or memory) access channels (DMA~. All DMA channels which can operate simultaneously must be 3~5;

directed to the same extended region of the storage address space. This may result in the necessity for double buffering of data, which reduces system performance and increases storage requirements.

Summary of the Invention:

In accordance with a preferred embodiment of this invention, there is provided an improvement in a computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) access (DMA) channels to operate simultaneously in the same or different storage page. Accordingly, there is provided in a computing system including a processor, a plurality of storage devices, a data bus and an address bus interconnecting said processor and said storage devices, and a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from the address register means corresponding to a currently active DMA
channel.

Brief Description of the Drawings:

One preferred embodiment of this lnvention is here-inafter described with reference being made to the following drawings in which:
Figure 1 is a block diagram showing a typical DMA
apparatus for addressing DMA channels to system storage.
Figure 2 is a block diagram showing the apparatus of the invention for addressing a plurality of ~MA channels into the same or distinct regions of system storage;
Figures 3A and 3B are block diagrams showing the bus and addressing apparakus of Eigure 2 in greater detail;
these are aligned as shown in Figure 3; and ' 3~

Figure 4 is a map diagram of storage address space illustrating DMA page rollover.

Description of the Preferred Embodiments:
~ . _ Herein, by way of example, processor unit 10 comprises an Intel 8088 microprocessor wi-th a twenty bit address bus 12 capable of addressing in excess of one million locations in storage 16, and an 8 bit data bus 14. Storage 16 may comprise standard read only storage and random access memory devices.

Input/output devices 18 are coupled to data bus 14 for transferring data with respect to storage 16 under control of DMA controller 20. DM~ controller 20 herein comprises an Intel 8237 or Intel DMA 8257 device with a capacity for coupling four channels (one is illustrated) to the eight bit data bus 14. DMA 20 address lines 2B couple sixteen address bits to the twenty bit address bus 12.

In the simplified diagram of Figure 1, line 22 represents the ~lany control and status lines to be described hereafter for controlling the activity on busses 12., 14. Control lines interconnecting processor 10 and DMA 20 to be specifically mentioned at this point include bus request (also referred to as HOLD) line 26 and bus grant (also referred to as HOLD A) line 24.
Control lines interconnecting DMA to a single input/output means (such as a plurality of I/O devices attached to an I/O adapter 18), and thus establishing a given instance of a channel, include data request (DRQ) line 31 and data acknowledge (DACK) line 30. A DRQ/DACK
line pair exists for each channelO

In operation, approximately one typical bus cycle under DMA control includes the following steps:
*
Trade Mark ,~.

3~

(1) Processor 10 communicates address information over data busses 14, 29 to DMA 20, where it is stored in the DMA 20 address register addressed by the four low order bits A0-A3 on address bus 12, indicating the location in storage 16, with respect to which data is to be transferred.
~ 2) Processor 10 communicates count information to DMA 20 over data busses 14, 29, where it is stored in the count register addressed by the four low order bits A0-A3 on the address bus 12, indicating the number o words or characters to be transferred.
(3) I/O controller 18, when ready to transfer, brings up data request (DRQ) line 31.
(4) Responding to DRQ 31, DMA 20 signals HOLD 26 to 15 processor 10 to request access to busses 12, 14.
~ 5) Responding to HOLD 26, processor 10 signals HOLD A 24 to DMA 20, granting access to busses 12, 1~.
(6) DMA 20, now controlling system busses 12, 14, loads address bus 12 with the address stored at step (1) in the DMA 20 address register for the currently active channel.
(7) DMA 20 signals DACK 30 to I/O controller 18.
(8) I/O controller 18 loads its data on data bus 14.
(9) DMA 20 controls selected control (CTL) lines 22 to indicate storage work to be performed.
~10) DMA 20 releases the system busses.

A DMA operation typically includes transfer of a plurality of data characters (a character is 8 bits for the B bit data bus in this example), and includes the following steps:
(1) load address on address bus 12 from the ~MA 20 address register corresponding to the active channel;

(2) perform bus operation ~data transer over bus 14);

BC9~81-003

(3) inorement (or, equivalently, decrement) DMA
20 address register;

(4) de~rement the DMA 20 count register corresponding to the active channel;

(5) repeat steps (1) - (4) until the count register reaches zero;

(6) signal end of operation (see Figure 3, pin EOP).

Referring now to Figure 2, a description will be given of the addressing apparatus of the invention. In Figure 2 there is provided, by way of example and not limitation, apparatus for controlling four DMA channels and ~or paglng each DMA channel into selectable pages of 215, or approximately 64K, addressable locations within an address space comprising 22, or approximately one million such locations. This particular example results from the combination of a twenty bit system address bus 12, ~Jith a four channel DMA chip 20 having 16 address lines 28, 29, and a four bit page array register 40, as will be further described hereafter.

As shown in Figure 2, processor chip 10 includes among its input/output lines an 8 bit data bus 14, a 20 bit address bus 12, a plurality of control and status lines 22, write control line 23, hold acknowledge line 24, and hold line 26. Control and status lines are coupled to I/O device read/write control and decode module 60, storage 16, and I/O device adapters 18. Eight bit data bus 14 is coupled to storage 16, adapters 18, via lines 29 to the eight data ports DO-D7 of DMA 20, and via the four (DO-D3) lines 62 to the data input terminals Dl, D2, D3, and D4 of pa~e array 40. The eight lines 29 from DMA 20 may be used for either data or address, and in the latter case are ~ated by AEN line 58 and ADSTB line 56 through 8 bit latch 50 via lines 54 to provide address bits A8-A15 to address bus 12. DMA 20 address bits AO-A7 BC9-81~003 3~
--6~
are coupled (through buffer 51 shown in Figure 3) by lines 28 to address bus 12. Address bus 12 is also coupled to control and decode 60, storage 16, device adapters 18, and the two low order bits (~0, Al) to the WA
and WB input terminals of page array chip 40.

The output of I/O device read/write control and decoder is a read-device/write device line pair for each of the attached devices.

Write control line 23 of processor 10 is coupled to the WRITE terminal of page array register 40. Address enable (AEN) line 58 indicates that DMA has control of the system busses 12, 14, and in this exemplary implementation is fed from the AEN terminal of DMA 20 to the OE terminal of latch 50, and via inverter 52 to the READ terminal of page array register 40. The address strobe (ADST~) terminal of DMA 20 is coupled to the clock CLK terminal of latch 50 by line 56, and becomes active to latch information on lines 29 into latch 50.

Device acknowledge DACK 1 line 37, DACK 2 line 38, DACK 3 line 39 are encoded by OR array 42, 46 and fed to the read A (RA) and read B (RB) input terminal 5 of page array 40. Device request DRQ 0 line 32, DRQ 1 line 33, DRQ 2 line 34, and DRQ 3 line 35, together with lines 36 38 couple DMA 20 to I/O device adapters 18, with a DRQ/DACK pair for each DMA channel.

Page array 40 output terminals Ql-Q4 are coupled to the A16-Al9 bits of address bus 12 by lines 46.

In this example, page array 40 compris~s a Texas Instruments standard TTL circuit type 74LS670 module latch 50 a standard TTL circuit type LS373, buffer 51 (Figure 3) a standard TTL circuit type LS244, DMA 20 an Intel 8237 (or, equivalently, an Intel 8257) DMA device.

In Figure 3 is shown in greater detail the interconnection of DMA 20, page array 40, 8 bit latch 50 ~all from Figure 2) ~nd buffer 51 which buffers address bits A0-A7 from DMA 20 onto lines 28 and address bus 12.
As illustrated in Figure 3, DMA chip 20 comprises ~0 terminal pins, the pertinent pins including adclress bits A0-A7, combined data/address pins DB0-DB7, data request pins DREQ0-DREQ3, data acknowledge pins DACK0-DACK3, bus ~or hold HOLD) request pin HRQ26, ADSTB pin 56, address enable AE~ pin 58, and group of control pins from processor 10 including chip select CS, hold acknowledge HLDA 24, I/O read pin IOR, and I/O write pin IOW.

In operation, the apparatus of Figures 2 and 3 extends the addressing capability of DMA 20 from the 16 bits provided by an Intel 8237 DMA chip to the full 20 bits system address bus provided by an Intel 8088 microprocessor chip (such as is described in A. P. Morse, The 8086 Primer, ~Iayden Book Co., Inc., copyright 1980, Li~rary of Congress number QA76.8.1292M67 001.6'4'04 79-23932 SBN 0-8104-5165~4) by selecting a pre-programmed page register for each separate DMA channel. Thus, simultaneous DMA operations can take place in the same or different 64K byte block regions, or pages.

Page array 40 includes four four-bit registers, ~5 each of which is individually programmable by processor 10 to provlde different or identical high order address bits A16-Al9 at output terminals Ql-Q4. To program one of these array 40 registers, the register address (00, 01, 10, or 11~ is established at the WA, WB terminals, the data bus 14 bits D0-D3 applied to array 40 terminals Dl-D4 respectively, and loaded into the addressed register when WRITE 23 is activated.

When a specific channel is requested by an I/O
device 18 on a DRQ line, DMA 20 indicates that this 3~

channel is active by sending a DACK signal unique to that channel and by activating the active enable AEN line 58 signalling that any channel is active. In order to gate address bits Al6-Al9 from one of array 40 registers to thereby estahlish the storage 16 page in which the active channel is to operate, DACK lines 37-39 are encoded at gates 4~, 44 to provide at array 40 read address input terminals RA, RB the address of the array 40 register corresponding to the active DMA channel. When the array 40 READ terminal is activated by DMA 20 signal AEN on line 58, the contents o the array 40 register selected by RA, RB is placed at array 40 terminals Ql-Q4 to load the high order address bits A16-Al9 on address bus 12.
The remaining, low order 16 address bits A0-A15 are loaded onto address bus 12 by buffer 51 (bits A0-A7) and latch 50 (bits A8-Al5) respectively, which rec~ive their address bits from DMA 20.

DMA 20 is primed with the 16 low order address bits by controller 10 via data bus 14, as was described in ; 20 connection with Figure 1.

In Table 1 is set forth a source code listing in Intel ASM-86 assembly language (as described in Morse, ; supra~ illustrating an example of the addressing technique of the invention, together with one approach for preventing rollover with DMA paging. Referring to Figure 4, to illustrate paging and rollover, assume that the high order address bits stored in the array register 40 for an active DMA channel are lllO, or he~ 7; that the low order address bits stored in DMA 20 are 1111 llll 1111 lllO, or hex FFFE. Assume further that a data transfer is initiated which will write into more than two storage 16 locations. After location 7FFFE and 7FFFF
have been written, because there is no carry provided from address bit A15 to A16, the next storage 16 location to receive data will be 70000, and not 80000 as would .

_g_ normally be d~sired. Consequently, the proced~re of Table 1 illustrates steps 1 and 2 of the sequence described above in connection with Figure 1, as adapted to the apparatus of Figures 2 and 3, to prime DMA 20 with the beglnning address for, and the count of, a da~a transfer.
TABLE 1: DMA SET UP
LINE SOURCE

612 ; DMA SETUP
613 ; THIS RCUTINE SETS UP THE D~iA F3R READ/~RITE~VERIFY
614 S UPERATIO~S.
615 ; I~IPUT
616 : ~AL) - ~iOOE BYTE FCR Tl~E D~lA
617 ; (ES:B~] - ADDRESS TO READ~URITE T~IE DATA
61S ; UUTPUT
619 ; (hX) DESTROYED

622 DIlA SETUP PROC NEAR
623 PUSH CX , SAVE T~E REGISTER
6Z4 OUT ~liA~12,AL ; SET TH: FIRSTfLAST F~F
625 DUT D,IA+11.AL ; OUTPUT ThE llODE 8YTE
626 ~lOV AX,ES ; GET TIlE ES VALUE
627 MOV C1.,4 ; SHIFT CO~IT
62~ ROL AX,CL ; ROTATE LEFT
629 llOV CH.AL ; GET HIG~lE5T NYBLE OF ES TO CH
630 A~D AL,OFOH ; ZERO TH_ L013 NYBSLE FR0~1 SE~,~ENT
631 ADD AX~EX ; TEST FOR CARRY FROlt ADDITION

633 INC C~ ; CARRY ~7EA~lS HIGH 4 BITS tlU5T BE INC
634 SKIP INC:
635 PUSH AX ; SAVE START ADDR SS
63S OUT D~lA~,AL ; OUTPUT LOW ADDRESS
637 ~lOV AL,AH
6~8 OUT D:IA~4,AL ; OUTPUT HIG~l ADD~ESS
639 ~iOV AL,CH ; GET HIGH 4 BITS
640 AIID AL,OFH
641 OUT DHA_HIGH,AL ; OUTPUT THE HIGH 4 ~ITS
643 ;~ -- DETERMINE COUNT

645 HOV AH,DH ; NUlBER OF SECTORS
6~i6 SUB AL,AL ; TI!ES c5S INTO AX
647 SH~ AX.1 : SECTORS ~ 12~ INTO AX

650 MA~LL B~;6 ; GET T~JE EYTES~SECTOR PARH
651 llOV CL,AH ; USE AS SHIFT COU~T lO-lZ3, 1-256 ETC~
653 S~L A~.CL ; ~ULTIPLY ~Y CORRECT A110U~iT
654 DEC A~ ; -1 FCR D;9A VALUE
65S OUT DliA+5,AL LO.~ BYTCE~rFvALllE

65~ OUT DllA~5,AL ; ~iIGl~ BYTE OF COUNT
CX ; RECCVER COUNT VALUE
661 AX ; RECOVER ADDRESS VALUE
66 ADD AX,CX ; A~D, TEST FOR 64~ OVERFLO~i 2 POP CX ; RECOVER ~EGISTER
663 MOV AL.2 ; ~ion~ FCR S27 6~5 our DllA~10,AL ; INITIALIZE Tl!E DISKETTE C~ANNEL
S6 DPlA SETUP ENDP ; RETU~II TO CALLER. CFL SEr ~Y A~DVE IF E~RO~

~C9-81-003 3~

In table 1, at lines 624-625 the read/write mode is selected; at lines 626-634 the twenty bit system address is formed from the ES and BX registers; at lines 636-638 the low order 16 bits are loaded to DMA 20; at lines 639-641 the high order 4 bits are loaded to a page register 40; and at line 661 a test is made to assure that rollover will not occur. (In the Intel 8080, a twenty bit address is generated from the two 16-bit ES and BX registers by offsetting the two registers by one four bit nybble and adding the offset registers, as is illustrated in Table 2.3 TABLE 2: TWENTY BIT ADDRESS FORMULATION
ES r ~ r ~ 16 bits ~ 16 bits ADDR~ ~ 20 bits

Claims (5)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Storage addressing control apparatus of the type including a processor having an address bus for manifesting a first plurality of address signals, and a direct memory access control means coupled to the address bus (a) for manifesting a second plurality of address signals less in number than the first plurality and (b) also providing means for accessing said storage by a plurality of selectively operable channels characterized by:
a plurality of programmable register means coupled to the address bus for manifesting a third plurality of address signals equal to or less in number than the difference between the first and second pluralities; and decoding means responsive to operation of said direct memory access control means on behalf of a respective one of the operating channels for gating, to the address bus, the address signals manifested by the programmable register means corresponding to said respective operating channel.

2. Apparatus of the type including a processor, a data bus, and an address bus, for addressing each of a plurality of selectably operable direct memory access channels into distinct or overlapping regions of an address space of said processor, and direct memory access control means for loading address signals into a first portion of said address bus, characterized by:
a plurality of page address registers for loading address signals into a second portion of said address bus;
gating means for gating address signals into said second portion of said address bus from a page address register corresponding to a currently operating direct memory access channel.

3. Apparatus of the type including a processor, storage, and a system bus having a data bus for transferring data with respect to said storage and an address bus capable of manifesting a plurality N of address bits for addressing a plurality of channels into overlapping or distinct regions in the storage address space of the processor, characterized by:
access control means for controlling access to the system bus by the plurality of channels, said access control means including (a) first address register means for each channel for storing and loading onto a first portion of the address bus a plurality M of address bits, where M<N, and (b) signalling means for signalling an acknowledgment to a request to access the data bus by one of the plurality of channels;
page array means including for eachsaid channel second address register means for storing and loading onto a second portion of the address bus a plurality N-M
of address bits; and selecting means responsive to said signalling means for selecting the second address register means corresponding to the one of the plurality of channels requesting access to the data bus for loading said plurality N-M of address bits onto said second portion of said address bus.

4. The method of operating a computing apparatus to enable a plurality of direct storage access channels to operate concurrently in the same or distinct storage pages, the computing apparatus including a processor; a system bus including a data bus, and an address bus capable of manifesting a plurality N of address bits; a direct storage access controller selectively capable of storing M<N address bits on behalf of each of the channels; and an array of page registers each selectively capable of storing N-M address bits for a corresponding one of the channels, the method comprising the steps of:
responsive to a request from a requesting one of the channels, establishing control of the system bus in the direct storage access controller;
responsive to the establishment of such control of the system bus, signalling an acknowledgment signal to the requesting channel;
loading onto the address bus the M<N address bits forming a data transfer address stored by the controller on behalf of said requesting channel; and gating with said acknowledgment signal the N-M
address bits to said address bus from the page register corresponding to said requesting channel.

5. The method of claim 4, further comprising the steps of:
operating the processor to store in the direct storage access controller the M<N address bits for a first channel, and in the page register corresponding to said first channel N-M address bits;
storing in said direct storage access controller a count manifesting the number of data characters to be transferred;
transferring a data character on the data bus, and thereupon incrementing said data transfer address and decrementing said count;
repeating said loading and transferring steps until said count is decremented to zero.