CA1171180A - Method and apparatus for encoding and decoding digital information - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Digital data formed of binary bits of first and second values occupying consecutive bit cells of predeter-mined intervals are encoded such that successive binary bits of the first ox second values are represented by predetermined separations between succeeding transitions.
A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a binary bit of the first value. When successive binary bits of the first value are sensed, a respective second transition is produced at a second reference point in a bit cell after sensing every 2 or 3 binary bits of the first value. When successive binary bits of the second value are sensed, a respective second transition is produced at the second reference point in a bit cell when at least two successive binary bits of the first value are followed by a binary bit of the second value and also after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned second transition at the second reference point is separated from the closest first transition thereto by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of the second transi-tions are separated from each other by no more than 4 bit cell intervals.

Description

~17~

BACKGROUND OF THE INVENTION
This invention relates to digital data encoding/
decoding techniques and, more particularly, to such encoding and decod~ng techniques wherein successive binary bits of first or second values are represented by the separation bet~een succeeding transitions, these transitions having predeter~ined minimum and maximum separations. The encoded data is particularly applicable for direct recording on a record mediumr such as a magnetic tape, a rotary disc, and the like.
~ ecord media and diffexent types of data transmission channels exhibit characteristics such that so~called raw digital data is not easily recorded/reproduced or transmitted/
recei~ed with sufficient fidelity. To avoid dlstortion and loss of information, various encoding techniques haYe been proposed whereby the usual binary "l"s and "0l's are converted to suitably coded form which is more accurately recorded or transmitted. One example of such an encoding technique con~erts an m-bit data word~ formed of m binary bits, into a n-bit data word,.as disclosed in United States Patent 4,323,931, Issued April 6, 1982. Another encoding technique is known as a l'three position modulation'l encoder, whereby digital data is encoded in a so-called look-ahead code by which the density of the recorded data is increased.
In the three position modulation encoder, succeeding binary ~ s are separated from ~each other by at least two binary 1'0"5. By reason of this separation, the min~m interval - ~7~
between succeeding transitions is equal to three bit cell intervals, wherein a bit cell is an interval, or duration, occupied by a binary bit. That is, if a binary "1" is represented by, for example, a signal voltage that is greater than the signal voltage representing a binary "0", the transitions between "1"5 and "O"s are separated.by at least 3T, wherein T is equal-.to the~bi.t cell interval. .. .
If the digital signal which is produced by the three position modulation encoding technique is further converted to, for example, NRZI form, then the minimum separation between succeeding transitions, ref~rred to herein as the transition interval, Tmin, and the maximum transition inter-val TmaXt are set at Tmin = l.S T and TmaX = 6T~
When digital data is recorded on a magnetic medium, certain constraints must be placed upon the minimum transitioninterval Tmin. That is, where a high recording data density is desired, the minimum transition interval Tmin must be o~
sufficient duration to avoid a possible misinterpretation of succeeding transitions that are spaced too closely to each other. That is, a transition that may be spaced too closely .
to another may be missed, or skipped, durlnq a signal repro- .
ducing operation, thereby distorting the information which can be recovered. Although the minimum transition interval T .
~m~
- of the aforementioned three position modulation encoder is satisfactory, the maximum transition interval TmaX of that encoder is, in many applications, too long. For example, a maximum transition interval TmaX of 6T is not favorably disposed for self-clocking. Hence, the synchronous reproduction t ~'7~

of data which has been encoded in three position modulation ~ormat may not be easily at~ained. Consequently, the reproduced data may be distorted, and valuable information may be lost.

OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved data encoding technique which avoids the aforenoted disadvantages of the prior art.
Another object of this invention is to provide a data encoding technique which can be used to record digital information with relatively high density, which information can be readily reproduced by means of self-clocking arrange-ments.
A further object of this invention is to provide a data encoding technique which is a marked improvement over the aforementioned three position modulation technique.
An additional object of this invention is to provide a data encoding technique wherein successive binary bits are represented by succeeding transitions in the encoded digital signal, and wherein the minimum transition interval is on the order of about 1.5T and the maximum transition interval is on the order of about 4T or 4.5T.
Yet another object of this invention is to provide a data encoding technique which can be implemented by an encoder of relatively simple construction, and wherei~ the encoded data can be decoded by a compatible decoder also of simple construction.
A still further object of this invention is to provide an improved data encoding technique wherein the encoded data is readily adaptable for self-clocking.

.
.--various other objects, advantages and features of the present invention will become readily apparent from the ensuinS detailed description, and the no~el eatures will be particularly pointed out in the appended claims.

SUM~l~RY OF THE I~IENTION
In accordance with this invention, a data encoding technique is described, wherein an encoded digital signal is produced haviny transitions therein, the separation between succeeding transitions representing successive binary bits of first or second values. A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a binary bit o~ the first value. When successive binary bits of the first value are prcsent, a respective second transition is produced- ;-at a second reference point in a bit cell after sensing every

2 or 3 binary bits of the first value. When successive -binary bits of the second value are present, a respective second transition is produced at khe second re~erence point in a bit cell when at least two successive binary bits of the firs,t value are followed by a binary bit of the second value and also after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned second transition is separated from a first transition by at least 1.5 bit cell intervals but no more than 4 5 bit cell intervals and successive ones of these second transi tions are separated from each other by no more than 4 hit cell intervals. In a preferred embodiment, when successive binary bits of the first value are present, a second transition ~:17~

is produced after every two of-the5e bits. If the total number of successive bits i~ odd, then one of the second transitions is produced after three such bits andr thereafter, a second transition is prod~ced after sensing each two succe~sive bits~
When the total nu~ber of successive bits of the second binary value is greater than 4, a second transition is produced, in one embodiment, after three such bits and, ~hereafter, after every four such bits. In another embodiment, the aforementioned second transition is produced after every 4 bits.
BRIEF DESCRIPTION OF THE DRAWI~GS
The following detailed description, given by way of example, will best be understood in conjunction with the accompanying drawings in which:
- FIGS. lA-lK, 2A-2H and 3A-3I are timing diagrams which are useful in understanding the encoding technique of the present invention;
FIG. 4 is a block diagram of one embodiment of the encoder in accordance with the present invention;
FIG. 5 is-a table which is use~ul in understandin~
the operation of the encoder shown in FIG. 4;
FIGS. 6A-6C are timin~ diagrams which represent the various timing signals used in the encoder of FIG. 4;
~ IGS~ 7A and 7B are timing diagrams which represent a synchroni~ing signal which can be inserted into the encoded data, in accordance with the present invention;
FIG. 8 is a block diagram of one embodiment of a decoder which can be used to decode the data that has been encoded by the present invention;

FIG. 9 is a timing diagram representin~ a modifi-cation o the encoding technique of the present invention;
FIGS. lOA~lOK and llA-llK are timing diagrams which represent another embodiment of the encoding technique of the present invention;
FIG. 12 is a block diagram of an encoder which can be used to carry out the encoding technique represented by -the timing diagrams of FIGS. 10 and 11; -FIG. 13 is a timing diagram representing a synchroniæ-ing signal which can be inserted into the data encoded inaccordance with the for~.at represented by FIGS. 10 and 11;
and FIG. 14 is a block diagram of a decoder which is :
compatible with the encoder shown in FIG. 17................ .-:L5DETAILED DESCRIPTION OF PREFERRED EMBO MENTS . - .
Referring now to the drawings, FIGS. 1~-lK represent the encoding technique by which successive binary "l"s axe encoded into the preferred format by which succeeding transi- .
tions in the encoded digital signal, that is, the digital signal produced by way of the present invention, represents successive binary "l"s. In each of these figures, an initial transition is produced when the input digital signal undergoes a change-over from a binary "O" to a binary "1". This transition is referred to herein as the I'first transition" or "first-type" transition, and is produced in substantially the middle portion of a bit cell. As used herein, the expression "bit cell" refers to the interval or duration occupied by a binary bit of eithex "1l' or 1l0--value.

~:~7~8~

When successive binary "l"s are encoded, after the first transition is produced at the middle portion of a bit cell, the next-following transition is produced at the trailing edge of a bit cell, that is, this next-following transition, which is referred to herein as the "second" or-"second~type"
transitionr is produced at the boundary between adjacent bit cells. For the purpose of the present description, a "first" transition is produced at a first reference point, that is, at the middle portion of a bit cell, and a "second"
transition is produced at a second reference point, that is, at the trailing edge of a bit cell. This location of the transitions in the encoded data is similar to that of the NRZI format. However, in the NRZI code, the minimum transi-tion interval T that is produced in response to successive binary "l"s is equal to lT, and the ~aximum transition interval that is produced in response to successive binary "O"s has no limitation. The present invention differs ~rom these conditions of the NRZI code in that the mlnimum transition interval Tmin that is produced in response to successive binary "l"s is equal to 1.5T ~wherein T is equal to the ~ ;-bit cell interval), and the maximum transition interval TmaX
is equal to 4.5T or even 4T in response to successive binary " O " s .
In the encoded data produced in esponse to the input digital signal [010] shown in FIG. lA, only a single transition in the encoded signal is produced, this single transition coincidîng with the middle portion of the bit :.
. .

~7~130 cell which is occupied by the ~inary "1". The waveform produced b this encoded data is shown beneath the representation of [0101, and a digitized version of this waveform is represented therebeneath. This digitized version of the waveform contains bits whose bit cells are equal to one-half the bit cell dura-tion of the input digital data; and a transition in the encoded data waveform is represented by a binary "0" bit bf one-half bit cell duration followed by a binary "1" bit of one-half bit cell duration. Although not shown herein, it may be appreciated that the transition in the wave~orm shown in FIG. lA may be a negative transition, that is, the waveorm may undergo a change from its relatively higher level to its lower level. Nevertheless, the digitized representation of such a transition is represented by digitized bits 0}.
As shown in FIG. lB, input di~ital data [0110 is encoded in a manner such that a first transition is produced in the middle of the bit cell containing the first binary "1", and a second transition is produced at the trailing edge of the bit cell containing the last binary "1", that is, this second transition is produced at the boundary of the bit cells containing the binary signals 10. The separatio~
between these first and second transitions is equal to 1.5T, wherein T is equal to the bit cell interval. It will be appreciated that a "first" transition is produced in the middle of a bit cell interval when the input digital data undergoes a changeover from a binary "0" value to a binary "1"
value. A "second" transition is produced at ~he trailing edge of a bit cell interval in accordance with the followin~
conditions: (a) a chan.geover rom a binary "1" to a binary "O"; or (b) after a predetermined number of ~uccessive binary "l"s or "O" have been received, provided that succeeding .
transitions are separated by no less than Tmin = 1.5T.
These conditions are not mutually exclusive and, as will be explained in g:{eater detail below, a "second" transition is nct produced in accordance with condition.(a) if such a --second transition wvuld follow a "first" transition by less .
than a predetermined amountO In encoding the input digital data shown in FIG. lB, the first and second transition~ are separated by 1.5T, that is, by 1.5 bit cell intervals.
Referring to FIG. lC, the input digital data 101110 is èncoded such that a first transition is produced in the middle of the bit cell interval containing the ~irst binary "1", and a second transition is produced at the trailing edge of the bit cell containing the last binary "1". Thus~ the . ..
total separa~ion between these transitions is seen to be equal to 2.5T. A binary "1" is not produced at ~e boundary separating the bit cells containing the second and third binary "l"s because this would result in a separation between .
two transitions hy an amount equal l.OT. In the present invention, the predetermined minimum separation Tmin between succeeding ~ransitions is equal 1.5T. Thus, the requirement of condition (b3 above would prohibit the production, in encoding the data shown in FIG. lC, of a transition between the second and third binary "1"~.
When the number of successive binary "l"s is greater than 3, a "second" transition is produced after every 2 or 3 successive "l"s, as will be described.

1171~BO

Stated otherwise, a "first" transition is produced in the middle of the bit cell containing the first of the binary "l"s (that is, following the change-over from a binary "0" to a_binary "l") and a second transition is produced after every n successive binary "l"s wherein n = 2 or 3 t provided that condition (b) above is satisfied. Thus, to encode the input digital signal [011110], the first transition is produced in the middle of the bit cell containing the first binary "1'', and a respective second transition is produced after every 2 successi~e binary "l"s.
Consequently, the first two transitions in the encoded data are separated by 1.5T, and the next two transitions are separated by 2T.
In FIG. lE, the first transition is produced in the middle of the bit cell containing the ~irst binary "i", and then a second transition is produced at the trailing edye of the bit cell containing the second binary 't1". Then, the next "second" transition is produced following the next 3 binary "l"s. It is recognized that a "second" transition cannot be produced after every 2 binary "l"s to encode the data shown in FIG. lE because this would result in a separation between the last two transitions by an amount equal to lT.
From FIGS. lF-lK, it is seen that if the total number of successive binary "l"s in the input digital data is an even number in excess of 3~ then a respective transition is produced after e~ery two successive binary "l"s. However, if the total number of successive binary "l"s is an odd number in excess of 3, then a transition is produced after ~3l1'7~L:180 every two successive binary "l"s, except that the last five binary "l"s are divided into two groups, the first group consisting of 2 binary "l"s and the second group consi.sting of-~3 binary "l"s. Hence, if the total number of successive binary "l"s is an odd number in excess of 3, then two transi-tions will be separated from each other by a maximum of 3T.
In FIGS. lG, lI and lK, this maximum separation is provided between the last two transitions. If desired, this maximum separation can be provided between any other pair of trans-tions, such as between the.second and t~ird transitions,the third and fourth tran.sitions, the fourth and fifth transitions, and the like. O~ course, the separation between the first two transitions, as shown in FIGS. lD-lK, is q min 1.
As a modification of the example represented by FIGS.-lD-lK, a transition can be produced after every 3 successive binary 'll"s. This would result in the encoded wa~eforms shown in FIGS. lD-lG. However, if the input digital data is as shown in FIG. lH, then, after the initial minimum separation of 1.5T between the:first two transitions, as shown, the next transition would be produced after 3 binary "l"s and then anothex transition would be produced after the next-following 3 binary "l"s. This would result in the usual mini~um separation of 1.5T between the first two transitions, and then the remaining transitions would be separated by 3T.
To encode the input digital data shown in FIG. lI, the Eirst two transitions would be separated by 1.5T, then the next-following transition would be separated by 3T, and 1~~

then the remaining transitions would be separated by 2T. To encode the input digital data shown in FIG. lJ, the first two transitions would be separated by 1.5T, the next-following tr~nsitions would be separated by 3T, the next-following transition also would be separated by 3T, and then the final transition would be separated by 2T. To encode the input digital data shown in FIG. lK, the first two transitions would be separated by 1.5T, and then all of the following transitions would be separated by 3T. Thus, where possible, a transition is produced after e~ery 3 binary "l"s, provided that this does not result in a separation between succeeding transitions which is less than the minimum separation of 1.5T.
As yet another example, successive binary "l"s can be divided into groups of three "l"s and groups of two "l"s alternately. Hence, if the input digital data contains 9 successive binary "l"s,-these successive bits may be divided into a group of 2, followed by another group of 2 bits, followed by a group of 3 bits, and then followed by a group of 2 bits, with a transition being produced at the trailing edge of each group. The encoded waveform thus will exhibit transitions which are separated by 1.5T, 2T, 3T and 2T, respecti~ely.~ If the input digital data contains ten successive binary "l"s, these bits ~ay be divided into a group of 2r followed by a group of 3, followed by a group of 2 and followed by a group of 3 such blts. The encoded waveform thus will be provided with transitions which are separated by 1.5T, 3T, 2T and 3T, respecti~ely. Nevertheless, even in this mDdified example, 117~

the minimum separation between succeeding transitions i5 seen to be 1.5T.
The foreyoing has described the encoding of input digital data wherein that data contains successive binary 1- 1 ~7 5 . FIGS. 2 and 3 represent the encoding of data which contains successive binary "O"s. ~IGS. ZA-2H
represent the encoding of input digital data in which, successive binary "O"s are preceded by the combination ~l.
FIGS. 3A-3I represent the encoding of input digital data in which the successive binary " n ~5 ~re Preceded by the combination 11. In FIGS. 2A-2H, a "first"-type transition is produced in the middle of the bit cell containing the first binary "1". Of course, another "first" transition is produced in the middle of,the bit cell containing the binary "1" which follows the successive binary "O"s.
In FIGS. 3A-3I, the initial transition is a "second"-type transition which is produced at the trailing edge of the bit cell containing the binary "1" which precedes the :.
successive "O"s. A "firgt"-type transition is produced in the middle of the bit cell containg ~he binary "1"
which follows the successive "O"s. . .
In FIG. 2A, a transition is produced in the middle of each bit cell con~aining a binary "1"~ and these transitions are seen to be separated by 2T. In ~5 FIG. 3A, the initial transition is produced at the boundary between the blt cells containing the binary "1"
and binary "0", respectively, and the next-fvllowing ~3~

8l~

transition is produced in ~he middle of the bit cell contain-ing the next binary "1". Hence, in FIG. 3A, the illustrated transitions are separated by 1.5T.
In FIG. 2s, transitions are produced in response to the change-over of a binary "0" to a binary "1", thereby resulting in a separation of 3T between these transitions.
It is preferred that a transition not be produced at the boundary between successive binary "O"s because this will :
result in two succeeding "transition intervals" exhibiting ~0 minimum separation T i = 1.5T. In FIG 3B, the initial transition is produced at the boundary between the prefix 11 and the successive binary "O"s; and the next-following transition is produced in response to the change-over ~rom binary "0" to binary "1". This latter transition is a "first"-type transition and, thus, occurs in the middle of the bit cell containing the changed-over binary "1".
As shown in FIG. 2C, when the ~put digital data is [010001], transitions are produced at the middle of those bit cells which contain a binary "1". Hence, these transi-tions are separated by the transition interval of 4T.It is preferred that a transition not be produced at the trailing edge of the bit cell containing the first of the successive binary "O"s ih order to distinguish successive binary "O"s from successive binary "l"s. It is recalled that, in response to successive binary "l"s, the first two transitions are separated by the minimum transition interval Tmin = 1.5T. Also, to improve such discrimination between successive "l"s and "O"s, it is preferred that a ~17~18~
transition not be produced at the trailing edge of the bit cell containing the second binary "0". Likewise, in FIG. 3C, the beginning of the successive binary t'O"s is represented by a "second"-type transition, and it is preferred not to produce another of these "second"-type transitions at the trailing edge of the bit cell containing the second binary ~r o 1l .
FIG. ~D represents the input digital data [0100001~.
If this data is encoded by producing transitions only in the middle of the bit cells containing the lllustrated binary "l"s, then the separation between such transitions would be equal to 5T. In the present invention, the maximum separation, or transition interval TmaX, is selected to be 4.5T. Hence, if the input digital data of FIG. 2D is encoded in the aforementioned manner, the separation between transitions would exceed TmaX. To avoid this possibility, a ~'second~-type transition is produced at the trailing edge of the bit cell containing the thlrd binary "0", as illustrated.
This results ln a separation between the first two tran~
tions of 3.5T, and a separa~ion between the last two .- ~~
transitions of 1.5T. Thus, the .illustrated transition intervals are greater than Tmin and less than TmaX~
In FIG. 3D, if a transition is produced at the trailing edge of the bit cell containing the third binary "0", the resultant transition intervals in the Pncoded waveform will be greater than Tmin and less than TmaX. However, if a "second"-type transition is pxoduced at the beginning of the successive ~inary "O"s, and then the next transit.ion is not produced until after the change over from binary "0"
''.

Y 1~ .

~ 1~7~180 to binary "1", as illustrated, the resultant transition inter-val will be equal to TmaX = 4. 5T. This latter encoding is preferred.
From FIGS. 2C and 2D, and also from FIGS. 3C and 3D, 5 it is observed that, if the input digital data contains three or more successive binary "O"s, then the transition interval between the first two transitions should be no less than 3.5T.
In view of this condition, a transition is not provided at the :
boundary between the last two binary "O"s in FIG. 3D.
From FIGS. 2E-2H, it is a~preciated that, if successive binary "O"s are preceded by the combination ~1, then, after the first transition twhich is produced at the middle of the bit cell containing the binary "1"), the n~xt transition is produced after three successive binary "Onsr ~nd, thereafter, a "second"-type transition is proauce~ after the next 4 successive binary "U'ls. However, a "second"-type transition is not produced ater 4 successive binary "O"s - .
if to do so would result in a separation thereof from a "first"-type transition by less than Tmin = 1.5T. It is for this 2Q reason that a "second"-type transition is not produced a~ter .-.
the final 4 binary "O"s in FIG. 2G. However, since this .;
minimum separation requirement is not violated in FIG. 2H, a "second"-type transition is produced at the trailing edse of the bit cell containing the fourth binary "O" in the group 2~ o~ ~our "O"s, as illustrated. Thus, if the input digital data contains 4 or mo.re successive binary "O"s which are preceded by the combination 01, then the transition interval defined by the first two transitions which are used as an encoded representation of the input digital data is equal to 3.5T.

~0~9 ~ ',.

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From FIGS. 3D-3I, it is seen tha~, if 4 or more - successive binary "O"s are preceded by the combination 11, an initial transition is produced at the bound~ry between the bit cells containing the change-over from hinary "1"
to binary "0", and another transition is produced at the trailing edge of the bit cell containing the fourth binary 1l0", provided that the transition interval be~ween this transition and the next-following transition is not less than Tmin = 1.5T.s In FIG. 3D,-if a transition is produced at the trailing edge of the bit cell containing the fourth binary "0", the transition interval between this transition and the "~irst"-type transition produced at the middle of the next-following bit cell will be less than Tmin. Hence, and as shown in . FIG. 3D, a "second"-type transition is not produced at the trailing edge of the bit cell containing the fourth binary "0",~
res~lting in a transltion interval equal to TmaX = 4.5T.
- But, since the minimum transition interval Tmin is equaled . or exceeded when 5 or more successive binary "O"s are - present, as shown in FIGS. 3E-3I, a "second"-type transition is produced at the trailing edge of the bit cell containing:
.
the fourth binary "0".
Consequently, in FIGS. 3E-3I, the transition interval between the first two transitions of the encoded waveform is equal to 4T. Thereafter, another "second"-type transition is produced after every 4 binary "O"s, unless the separation between this l'second"-type transition and the 117~80 next-following transition, such as the "first"-type transition shown in FIG. 3H, is less than Tmin= 1.5T.
A comparison between FIGS. 2D-2H and 3E-3I indicates that the transition interval between the first tw~ transitions in-the encoded waveform representing successive binary IO~s is.
equal to either 3.5T or 4T. From FIG. 1, it is recalled that this initial transition interval is on the order or 1.5T~ Hence, depending upon the inital transition interval, the encoded waveform representing successive binary ~ s can be distingui~hed easily from the encoded waveform representing successive binary "O'~s .
Also, it is seen that, when successive binary 'IO~'s are encoded in the manner discussed above, the maximum transition interval TmaX is limited to 4.5T, as shown in FIG. 2G and FIGS.
3D and 3H.
The encoding technique represented in FIGS. 2 and 3 may be described, generally, as producing a ~first~-type transition at the middle of a bit cell containing a binary "1"
when the input digital data changes over from a binary "01' to a binary "1", and a "second"-type transition is produced at the trailing edge of a bit cell after every m successive binary "O"s wherein m = 3 or 4. This general description is further limited by the condition that a transition interval will not exceed T = 4.5T, nor will a transition interval be less than Tmi~ = l.5T. Furthermore, m = 3 to define the first transition interval when successive binary "O"s are preceded by the co~bination 01 and m = 4 to define the first transition interval when successive binary 1'0"s are preceded --1~--~'7~18(~

by the combir.ation 11. Thereafter, the transition interval between succeeding "second"-type transitions is seen to be 4T, as shown in FIG. 2H and FIGS. 3E-3I. Also, it is preferred that, where possible, the transition interval between the first two transitions in the encoded waveform be less than TmaX = 4.5T.
In any sequence of successive bits, minimum and maximum transition intervals Tmin and TmaX occur only once in a sequence. That is, in the encoded waveform representing successive binary "l"s or "O"s, the minimum transition interval is not present ~ore than once and, likewise, the maximum transition interval also is not present more than once. It is appreciated that input digital data containing successive binary "O"s may be encoded as represented by FIG. 2 or FIG. 3/ depending upon whether the successive binary "O"s are preceded by the combination 01 or by the combination 11.
In any e~ent, when 3 or more successive binary "O"s are present, the initial transition interval is no less than 3.5T.
However, when the input digital data contains successive binary "l"s, the larg~st transition interval contained in the encoded waveform is 3T, as shown in FIGS. lE, lG, lI and lK.
Therefore, in order to distinguish the encoded representation of successive binary-"O"s from successive binary "l"s, the received transition intervals are compared to a reference predetermined interval whiich, in the present examplei, is selected to be equal bo 3.5T.
That is, in order to decode the waveforms produced by ~he encoder of the o present invention, ~he separatïon between succeeding transi tions is compared to this 3.5T s~andard. If the detected separation is less than 3.5T, it is assumed that the encod~d waveform represents successive binary "~"g. Conversely, if the detected sepa.ration between succeeding transitions in the encoded waveform is greater than 3.5T, the transitions are assumed to represent successive binary "0"s~
. One embodiment of encoding apparatus wh;ch is -readily adapted to carry out the encoding technique discussed hereinabove with respect to ~IGS~ 1-3 is illustrated in FIG. 4. Encoder 1 is comprised of a shift register 2, a read only memory (ROM) 5, a shlft register 6, a multi-stage shift register 8 and a logic gating circuit 11. Shift re~ister 2 is illustrated as a three-stage shift register having an input terminal 3 to which input digital data is . -supplied, and a shift pulse input 4 connected to receive -;
timing pulses, also referred to as clock pulses CPl.
Digital data`is shifted from right-to-left, one stage at a time, in response to each timing pulse supplied to shift register 2. As il.lustrated, an input hit is shifted .:
into stage a3, and.then -frsm stage a3 to stage a2, and then ..
from stage a2 to stage al, all in synchronism with successive timing pulses CPl. The contents of stages al, a2 and a3 are supplied as three bits of a 4-bit address signa7 to ROM 5. The fourth bit of this address signal is designated as bit x supplied to ROM 5 by logic gating circuit 11, to be described.

o ROM 5 may be a conventional read only memory having, for example, slxteen separate storage locations, each storage location being add~essed by the 4-bit address signal supplied thereto, and each of the sixteen storage locations storing 5 a 2-bit signal. This 2-bit signal is read out from the addressed storage location of ROM 5 and loaded, parallel-by-bit, into shift register 6. As illustrated, shift register 6 is a 2-bit shi~t registex having stages bl and b2 therein.
Shift register 6 includes a load input terminal 7 10 adapted to receive a load pulse ~D for loading the 2-bit signal read out of ROM 5 into stages bl and b2. This shift register also includes a shift pulse input coupled to a clock pulse termlnal 9 for receiving clock, or timing pulses CP2.
The contents of shift register 6 are shifted in synchronism 15 with clock pulses CP2 in the right-to-left direction. ~ence, in response to two successive clock pulses CP2, the bit loaded into stage bl is shifted out therefrom while ~e bit which L
had been loaded into stage b2 is shifted thereinto, and then --this bit is shifted out of stage b1. The outp~t o shlft register 6 is supplied serially-by-bit to multi-stage shift register 8 which, in the illustrated embodiment, is an 8-stage shift register including stages A-H. This shift register also includes a shift pulse input connected to clock pulse input terminal 9 ~o receive clock pulses CP2 so as to synchronously shift bits therethrough in the right-to-left -direction in response to each clock pulse. An output terminal 10 is coupled to the left-most stage A to recei~e the contents of shift register 8 which has been serially shifted therethrough.

'.;

. .

1~ 8~
Each stage A-H of shift register 8 is coupled to a respective input of logic gating circuit 11. An additional ..
input of this logi gating circuit is coupled to stage al of shift register 2. The logic gating circuit combines the various bit~ supplied thereto from shift r2gisters 2 and 8 to produce bit x of the 4-bit address supplied to ROM 5.
This logic gating circuit implements the Boolean equation:

x - (A+B).(C~D).(E+F).(G~H). al ~ (G+H). a~

.
Although not described in detail herein, one of ordinary skill in the art would be enabied to construct a suitable logic gating circuit to implement the foregoing equation.
In operation, clock pulses CP1 are supplied via clock input terminal 4 to shift register 2. These clock pulses serve to serially shift into shift register 2 the - ~
particular digital data supplied thereto via lnput terminal 3. . .
Clock pulses CP1 are illustrated in FIG. 6A. For the purpose of the present discussion, it may be assumed that a binary bit is shifted into stage a3 of ~hift register 2 in response:.
to the positive-going transition of clock pulse CPl.
Furthermore~ each positive transition of clock pulse CP
serves to shift the contents of shift register 2 to the left by one stage. Prior to loading the next bit of the input digital data into shift reaister 2, the contents of ROM 5 are read out therefrom in response to the 4-bit address supplied thereto, this 4-bit address being constituted as (xala2a3). This data read out of ROM 5 is loaded into shift registPr 6 in response to the load pulse LD, shown in FIG. 6C. Then, after shit register 6 is loaded with data represented as blb~, this 2-bit data is shifted into ~7~80 shift register 8 in response to the next 2 successive clock pulses CP2 shown in FIG. 6B. The contents of shift register 8 (ABCDEFGH), together with bit al in shift register 2, are ~upplied to logic gating circuit 11 to produce bit x. Ihereafter, the 4-bit address (xala2a3) reads out bits blb2 from ROM 5, -these bits being loaded .into shift register 6. The foreyoing cycle is repeated periodic~lly at the rate aetermined by clock pulses CPl. This cycle interval ECC is illustrated in FIG. 6.
As an example of the operation of the encoder shown in FIG. 4, let it be assumed that the input digital data [OLllllO~ hown in ~IG. lE, is supplied to input terminal 3.
Let it be further assumed that, initiaily, the contents of shift register 8 are reset to zero, bits blb2 are (00) and bits ala2a3 are tOOO). It is further assumed that successive clock pulses CP~ are generated at times to~ -t~ t2 ..., and clock pulses CPl, WhiCh are one-half the ~requency of clock pulses CP2, are generated at times to~ t2, t4 ... . At time to~ the binary 1l0ll of the input digital data is loaded into stage a3 of shift register 2. Also, at times to and tl, bits blb2, which are assumed to be (?, are shifted into stages G and H, respectively. Thus, at time tl, logic gating circuit 11 is supplied with bits A-H and al, all of which are a binary "O". From the foregoing equation, it is appreciated that bit x also is a binary ''0'l. FIG. 5 illustrates the "memory map"
of ROM 5, from which it is appreciated that bits tOO) are read out therefrom. These bits are loaded into shift register 6 in response to the load pulse LD ollowing time point tl.

~ ! . .~

O
At time t2, the binary "1" included in-the input digital data is loaded into stage a3. At times t2 and t3, the contents (00) of shift register 6 are loaded into stages G and H of shift register 8, and the contents (00 previously stored in stages G and H are shifted into stages E and F, re~pecti~ely. Logic gating circuit 11 produces a binary "0" as bit x, such that ROM 5 now is addressed by the address signal (0001). As shown in FIG. 5, ROM 5 now supplies the bits (00) to shift register 6 in response to the load pulse LD which is produced a~ter time point t3.
At time t4, the next binary "1" of the input digital data is loaded into stage a3, and the binary "1"
previously stored in stage a3 is loaded into stage a2.
Bits (00) which had been loaded into shift register 6 in response to the load pulse LD preceding time point t4 are shifted into stages G and H at times t4 and t5. At these times, the contents of stages E and F are shifted into stages C and D, and the contents previously s~o.red in stages G and H are shifted into sta~es E and F. Logic gating circuit 11 still is supplied with 0...0 to produce a :
binary "O" as bit x. Now, however, ROM S is addressed by the address signal (0011) to supply bits (01) to shift register 6. These bits are loaded into the shift register in response to the next load pulse LD which precedes time point t6.
At time t6, the third binary "1" of the input digital data is shlfted into stage a3, the binary "1"

.

-~lglL~71~8~

previously stored in this stage is shifted into stage a2, and the binary "1" previously stored in stage a2 is shifted into stage al. Furthermore, at times t6 and t7, I the contents (01) of shift register 6 are shifted into stages G and H, respectively, and, of course, the contents of stages C
and D are shifted into stages A and B, the contents of stages E and F are shifted into stages C and D, and the contents previously stored in stages G and H are shifted into stages E and F. Now, logic gating circuit 11 is supplied with a bi~ary "1" from stage H and also~with a binary "1" from stage al of shift register 2. In accordance with the preceding Boolean equation, logic gating circuit ll produces a binary "1" as bit x. Consequently, ROM 5 now is addressed with the address signal (1111) to supply bits ~00) to shift register 6. The load pulse LD produced between times t7 and t8 loads shi~t register 6 with this (00) information.
The foregoing operation is repeated cyclically as the input digital data is shifted through shift register 2. Hence encoder 1 operates such that, at times tl5, tl8 and t24, i 20 a binary "1", whose duration is e~ual to one-half the period of clock pulses CPl, is shifted to output terminal 10 from shift register 8. Thus, a binary "1" of duration 0.5T is produced at : times tl5, tl8 and t24. These binary "l"s represent the transi-tions of the encoded wave~orm; and if supplied to a flip-flop circuit, a toggle circuit, or the like will result in the wa~eform illustrated in FIG. lE.

-~5-` ~17~8~) It will be appreciated that encoder 1 functions to encode successive binary "l"s and successive binary "O"s in the manner described hereinabove with respect to FIGS~ 1-3.
Thus, tra~sitions having the aforenoted transition intervals are produced as encoded representations of the input digital data supplied to input terminal 3.
In the foregoing description of encoder 1, it has been assumed that a read only memory is used to supply shift register 6 with bits blb2 in response to the 4-bit address signal (xa1a~a3). If desired, this read only memory may be replaced by a logic gating circuit to implement the table shown in FIG. 5. More partic~llarly, the logic gating circuit may be used to implement the ollowing Boolean equations:

bl = x.al. (a2 + a3) ~ x al 2 b2 - al a2 ;
It is seen that the combination of shift register 2 and logic gating circuit 11 functions to sense the presence and number of successive binary "l"s or "O"s in the digital data supplied to input terminal 3. ROM 5 is addressed in response to the sensing of such data to read out therefrom signals which are used to produce "~irst"-type transitions the bit b2 is a binary "1") or "second"--~ype transitions (if the bit bl is a binary "1"). The for~going equation (1) in combination with reading out of the stored contents OL

ROM 5 insures a minimum transition interval Tmin ~ 1.5T

-2~-~l~7~

a maximum transition interval TmaX = 4.5T and a transition interval no greater than 4T between "second"-type transitions, in the encoded data produced a~ output ~erminal 10, Thi~
combination also serves to determine if the total number of successive binary 'll"s, for example, is greater than 3, is odd or is even. Furthermore, encoder l functions to sense the appropriate number of successi~e binary "0"s in order to produce the respective transitions discussed above with respect to FIGS. 2 and 3.
The encoded waveform derived by encoder 1 may be xecorded on a suitable record medium, such as magnetic tape, a magnetic disc, or the like. As one example, the encoded waveform may be recorded on a disc similar to a typical video disc. When recorded in this manner, it is desirable that a frame synchronizing signal FS also be recorded. This frame synchronizing signal is used during a xeproduction operation to synchronize timing pulses which are used to decode the encoded waveform, and thus recover the original digital data. Preferably, the frame synchronizing signal FS
is inserted into the encoded waveform. That is, it is not recorded in a separate location as a distinctive signal on th~ record medium. Consequently, it is necessary that the frame synchronizing signal FS be distinguishable from the encoded data, yet it should be of a similax format~
; 25 One example of a suitable frame synchronizing signal is illustrated in FIGS. 7A and 7B.
The frame synchronizing signal is constituted by three transitions defining two successive transition inter~als ~L:17~
.
equal to T ax = 4.5T. ~s mentioned ahove, the encoded data waveform representing successive h~nary "l"s and "O"s does not include consecutive transition intervals equal to TmaX. Hence, the frame synchronizing signal FS is seen S to be unique and may be readily detected when the encoded data waveform is reproduced or otherwise received.
The relationship between the frame synchronizing sign FS and a number of successive bit cells is illustrated in FIGS. 7A and 7B. It is seen ~hat the beginning and ending transitions of the frame synchronizing signal each coincides with the middle of a bit cell, and the middle, or intermediate transit~on of the frame synchronizing signal coincides with the boundary between adjacent bit cells. With this relation~hip, clock pulses may be synchxoni~ed with the r~spective frame synchronizing signal transitions. More particularly, clock pulses having a frequency similar to that of aforedescribed clock pulses CPl (FIG. 6A~ may ~e synchronized with the intermediate transition of the frame synchronizing signal; and clock pulses having a frequency similar to the aforedescribed clock pulses CP2 (FIG. 6B~
may be synchronized with the beginning and ending transitions of the frame synchronizing signal. As will be described belowr such synchronized clock pulses may be used to decode the encoded data waveform so as to recover the original digital data.
The frame synchronizing signal comprises two successive transition intervals, each equal to TmaX, which are present during an overall duration equal to 12T.

~` ~17~

It will be appreciated that encoder 1 does not produce an - encoded waveform whereby two transition intervals TmaX
are produced during a duration of 12T. Hence, the frame .
synchronizing signal may be readily detected merely by establishing a re~erence duration equal to 12T (or, if desired, equal to llT) and by sensing consecutive transi-tion intervals TmaX during such a reference duration. This frame synchronizing signal is used to synchronize the code `:
bits which represent the transitions of the encoded data waveform, as well as th~ recovered binary bits. Furthermore, the fxame synchronizing signal may be used to synchronize frame intervals which, in some applications, establish timing intervals in which data is recorded or transmitted.
One embodiment of a decoder which is compatible with encoder 1 and which may be used to recover the original digital data from the encoded data wave~orms shown in FIGS. 1-3 is illustrated in FIG. 8. This decoder 12 is comprised of a multi-stage shift register 14 having an input terminal 13 connected to receive a digitized version ~.
20 of the encoded data waveform, and a shift pulse input I8 .^
connected to receive clock, or timing, pulses CP3. Timing pulses CP3 ~ay be similar to aforede~cribed timing pulses CP2, having a frequen~y equal to twice the originaL data bit rate.
Encoder 12 also includes a logic ~ating circuit 15, which may be comprised of conventional gating circuitry, adapted to implement the following Boolean equation:

6 5 (Cg cll.C8) + (C4~C3) (C7~Cg~ + (C2~c ) C 1' wherein y is the output produced by the logic gating circuit in response to bits Cl .~. Cll supplied thereto. These bits are the contents of corresponding stage~ in multi-stage shift register 14.
The output of logic gating circuit 15 is coupled to a latch circuit 16, which may comprise a timing pulse controlled flip-flop circuit, or the like, coupled to a clock, or timing, pulse input 19 to receive clock pulses CP4.
The output produced by latch circuit 16 may be either a binary "1" or a binary "0", dePending upon the state of the input supplied thereto at the time of receipt of a clock pulse CP4. This output is supplied to an output terminal 17.
Clock pulses CP3 are synchronized with the beginning and ending transitions of frame synchronizing signal FS, and clock pulses CP4 are synchronized with the intermediate transition of this frame synchroniziny signal. It may be appreciated, therefore, that if the digitized version of the encoded data wave~orm supplied to input terminal 13 represents each transition as a binary "1" of one-half bit cell duration, when the binary "1" representing the beginning transition of - the frame synchronizing signal shown in FIG. 7B is shifted from stage Cll to stage C10 in shift register 14, a clock pulse CP4 is produced. Then, when this binary "1" is shifted from stage C9 to stage C~, and then from stage C7 to stage C6, and then stage C5 to stage C4, and then from stage C3 to stage C2, a respective clock pulse CP4 is generated in timed synchronism therewith. It is further appreciated that successive clock pu~ses CP3 serve to shift these bits from stage-to-stage of shift register 14 in the 8~

right-to-left direction.
As one example of the operation of decoder 12, let it be assumed that the encoded data waveform shown i~iFIG. 2G has been recorded. The original digital data .
llQ0000001~ thus is represented by the waveform wherein a "firstl'-type transition is produced in the middle of a bit cell interval, the next-following transition is separated therefrom by 3.5T, and an ending transition is a "firs~type transition spaced from the intermediate transition by 4.5T. This encoded waveform is ~urther converted by conventional m0ans (not shown) to code bits of the type shown in FIGS. lA, 2A, 3A
and 7B, wherein a transition is represented by a binary "1"
code bit whose duration is equal to one-half of a bit cell inter~al. Thusl it is appreciated that the encoded data bits which represent the encoded waveform of FIG. 2G are constituted by a binary "1" bit in the second-half portion of a first bit cell interyal, a binary l'l" code bit in the first-half portion of the next-following fifth bit cell interval, and a binary "1" code bit in the second-half portion of the next-following ninth bit cell interval.
Stated otherwise, let it be assumed that clock pulses CP3 are generated at times t~, tl, t2 ~ tl6~ tl7~ tl8~ ~o 2 The encoded data bits thus are present as binary "l"s in the intervals tl t2' 8 tg an tl7 18 Clock pulses CP4 are generated at one-half the rate of clock pulses CP3 and are synchronized ~y the frame synchronizing signal FS such that these clock pulses are genexated at times to~ t~, t~ ~o tl8' ~20' t22' Wow, at time tor a binary "O" code bit is shifted into stage Cll of shift register 14. At time tl, the binary ~1"
code bit is shifted into this stage. This binary "1" cod.e bit is shifted into stage C10 at time t2, into stage Cg at time t3, into stage C8 at time t4, into stage C7 at time t5, and into stage C6 at time t6. From equation (4), it is appreciated that an outpu~ ~ is produced by logic gate circuit 15 when a binary "1" is shifted into stage C6.
Hence, a binary "1" i5 produced as output ~ during the time interval t6-t7. At time t7, the bin~ry "1" in stage C6 is shifted into stage C5, and at time t8, the binary "1"
is shifted from stage C5 into stage C4. At this same time t8, the next binary "1" code bit is shifted into stage Cll, and the aforedescribed shifting process is repeated. . ~-.
From equation ~4), it is seen that a binary "1"
is produced at output y at time tl3, that is, at the time when the next binary "1" code bit which had been shifted into stage Cll is shifted into stage C6. Thereafter, a binary "ln is produced at output y at time t22. This is in response to ~e last binary "1" code bit which i5 shifted into s~age C11 at time tl7, this last binary "1" code bit being shifted sequentially until it reaches stage C6. Thus, a binary "1"
is produced at output y at times t6, tl3 and t22.
The binary "1" output y serves to set latch circuit 16 to a binary "1" condition only if the output is a binary "1" concurrent with a clcck pulse CP4. When output y is a binary "O", latch circuit 16 is reset in response to clock pulses CP~. Accordingly, in the foregoing -~2-example, latch circuit 16 is set in response to the binary "1 output ~ at time t6 r and then the latch circuit is reset 8' tlo' tl2' ~14' tl6' ~18 and t20- At the next clock pulse CP4, which occurs at time t22, the output ~
once again is a binary "1" to set latch circuit 16. Con-sequently, latch circuit 16 recovers the digital data signal [0100000001] at output terminal 17. This, of couxse, corresponds to the original input data shown in FIG. 2G.
Decoder 12 functions in a manner similar ~o that discussed hereinabove in order to recover the original digital data signal which may be supplied thereto as the encoded representations shown in FIGS. 1-3. In the interest of brevity, further description of the operation of decoder 12 is not provided. Nevertheless, it should be appreciated that logic gate circuit 15 func~ions to compare the representations of the transitions which are shifted to shift register 14 , - .
to predetermined "window" intervals. One of these window intervals effectively "measures'l the separation between the first two transitions to determine if this separation is of an amount corresponding to a series of binary "l"s or a series of binaxy "O"s, as mentioned above. It is recalled that the transitions which represent successive binary "l"s are separated from each other by an amount less than the transitions which represent successive binary "0"s. In ~5 this regard, logic gating circuit 15 efectively compares the separation be~ween transitions to two sets of "window"
intervals: one set of "window" intervals representing the various separatlons which are associated with binary "l"s;
and the other set of "windowl' intervals representing the separations associated with successive binary "0"st as 1~ 0 mentioned above. More particularly, these i'window" inter-vals are substantially equal to the expected separations represer.ting successive binary "L"s and "O"s. It is recalled tha~ the expected separa~ions representing S successive blnary "O"s are wider than the expected separations representing successive binary "l"s.
When the actual separations oorrespond to a particular "window" interval, the corxesponding binary bits are produced at output terminal 17 of latch circuit 16.
Hence, decoder 12 serves'to compare the separation between transitions, as represented by the code bits, to the aforementioned standard, or reference interval, whereby successive binary "l"s are produced when the transition intervals,are less than this standard, and successive binary "O"s are produced when the transition ' intervals exceed,this standard.
I~ is recognizea that the ll-stage storage capacity of shift register 14 is su~ficient to accommodate the code bits which represent at leask three succeeding transitions in the encoded version of successive binary "l"s.
That is, shift register 14 is sufficient to accommodate at least the encoded representation of the waveform shown in FIGo lE. This shift register also has sufficient capacity to accommodate the encoded versions shown in FIGS. 2D and 3D.
Various modifica~ions and changes may he made to decoder 12. For example, logic circuit 15 and logic circuit 16 may be replaced by a read only memory, similar to that used in encoder 1.

-3~-As discussed above, and as is apparent from FIGS. lD, lF~ lH and lJ, if the total number of suc-cessive binary "l"s in the input digital data is an even number, the binary "l"s may be divided into groups of two, and a "second"-type transition is produced in response to each group. If the total number of successive binary "l"s is an odd number, ~hen the last group of binary "l"s will be constituted by three such bits. In that event, the "second"-type transition is produced after these three bits have been sensed. It is seen, therefore, that the greatest transition interval in the encoded version of successive binary "i"s i5 equal to 3T.
Therefore, to distinguish successive binary "l"s from "O"s, the aforementioned reference, or standard, interval is selected as being equal to 3.51`. A transition interval that lS less than this standard thus is representative of successive binary 'll"s; and a transition interval that exceeds this standard is representative of successive~
binary ~ O 1~ 6 .
20 ~ ~ , As an aIternative, if the odd or even nature of ~he total number of~ successive binary "l"s is known~
prior t~ encoding, the àforementioned standard interval can be reduced from 3.5T to 205T. As shown in FIG. 9, if it is known that the total number of successive binary "l"s is an odd number, then the bits may be divided into a first group of three binary;"l"s, followed by succeeding groups of two binary "l"s. If "second"-type transitions are produced at the boundaries between adjacent -groups, the encoded waveform will appear as shown in FIG. 9. As illustrated, the initial transition interval , ~35-is equal to 2.ST because it is derived from the group of three binary "l"s. This initial transition interval is followed by succeeding transition interval5, all equal to 2T, because these latter transition intervals are derived from groups of two binary "l"s. Thus, a transition interval of 3T is avoided. The original input data sho~n in FI~. 9 corresponds to that shown in FIG. lK, and the differences between these encoding schemes are readiLy apparent. Of course, if it is known that the total number of successive binary "l"s is an even number, then these bits are divided into groups of two, resulting in the encvded waveforms shown in, for example, FIGS. lF, lH and lJ. Thus, for an odd numbex of binary "l"s, the initial transition interval is equal to 2.5T; whereas ~or an even number of successive binary "l"s, the initial transition interval is equal to 1.5T.
With this modification, if the reference, or standard interval which is used to di.scriminate the encoded representations of successive binary "l"s and "O"s is -reduced from 3.5T to 3T, the maximum transit.ion interval - T may be correspondingly reduced fxom 4.5T to 4T.
max As a result, the second transition interval shown in FIG. 2G would be reduced from 4.5T to 3.5T, the second transition interval shown in FIG. 2H would be reduced from 4T to 3T, the transition shown in FIG. 3D would be replaced by a firs~ transition interval of 3T followed by a second transition interval of 1.5T, and the like~
Of course, to best implement the foregoing modification, a buffer memory should be provided so as to store the successive binary "l"s of the input digital data, ~hereby indicating whether the successive binary "l"s constitute an odd or even number. Since, in a p~actical application, an infinite number of successlve binary "l"s is not provided, suitable buffer memories are readily available.
As yet another alternativP to the encoding technique described hereinabove, rather than determine, initially, if the total number of successive binary "l"s is odd or even, these data bits may be divided into groups of two and, if the '1remain~er" of one bit remains, tAen the last 5 bits in the sequence are divided into two groups: one group of 3 bits.and one group of 2 bits.
A "second"-type transition is provided at the bounda~y between these two groups. In the example described above .
- with respect to FIGS. lE, lG, lI and lX, the group of thre successive binary "l"s was designated the last of the groups.
In the example shown in FIGS. lOE, lOG, lOI and lOK, the group of three binary "l'ls is designated the penultimate group, and the final group o~ binary "l"s is fQrmed o two successive binary "l'ls.
In the examples represented by the timing d~agram . of FIG. 10, FIGS. lOA~lOD are seen to be substantially identical to FIGS. lA-lD, respectively. However, when the number of successive binary "l"s is 5 or greater, the last five of these bits are divided into two groups: a first group of three bits follow~d by a second group of two bits. Thus, in F~G. lOE, the first transltion interval of 2.5T is derived from the first qroup of three bits, and the next-following transition interval of 2T is derived from i7~80 the final group of two bits. In FIG. lE, the illustrated five binary "1"5 are divided into a first group of two bits, from which the transition interval of 1,5T i~ .
derived, foliowed by a final group of three bits, from which the transition interval of 3T is derived.
In the timina diagrams shown in ~IG. 10, the encoded wave~orms representing an even number of successive binary "l"s are substantially identical to the encoded waveforms of FIG. 1 which also represent an even number Of successive binary "l~'s. This is observed by comparing FIGS. lOF and lF, lOH and lH, and 1 W and lJ. However, when the input digital data contains an odd nu~er of successive binary "l"s in excess of 4, FIG. 10 illustrates a final transitio~ interval equal to 2T, derived from a final group of two successive binary l'l"sr preceded by a transi- , tion interval of either 2. 5T (FIG. lOE) or 3T, derived from the penultimate group of three successive binary "l"s. This .
arrangement is reversed in FIG. 1, as may be observed by .
comparing FIG5. lOE and lE, lOG and lG, lOI and lI, and 20 lOK and,lK. , A similar modifica~ion in the encoding scheme may be used to encode successive binary "O"sj as indicated in FIG. 11. More particularly, in FIG. 11, successive binary "O"s are divided into groups o.f three; and a "second"-type transition is produced at the trailing edge of a bitcell in response to each group, provided that the minimum separation between transitions is not less than 1.5T.
For the case of a single binary "0", as shown in FIGSo llA
and llA', the encoded waveform is similar to that discussed hereinabove with respect to PIGS~ 2A and 3A, respectively.
I~ the input digital data consists of only two successive binary "O"s, as shown in FIGS. 11B and llB'~ the encoded waveforms are similar to those shown in FIGS. 2B and 3B, 5 respectively. Likewise, if the input digital data is constituted by three successive binary "O"s, these three bits constitute a single group, resulting in the encoded waveform shown in FIG. llC, similar to the encoded waveforms shown in FI~S. 2C and 3C.
In FIGS. llC-llK, the encoded waveform having the first transition shown by the solid line represents that successive binary "O"s are preceded by the combination 01. -The encoded waveform having the first transition shown by the broken line represents that successive binary "O"s are pre~eded by the combination 11 In FIGS. llD-llK, four or more successive binary.
"O"s are present. In accordance with the illustrated -: encodiny scheme, the successive binary "O"s are divided into groups o~ three~ A~ter the first group of three 2.0 binary "~"s, a "second"-type transition is prodused.
Th~reafter, another "second" type transition is produced after the next group of three binary "O"s, only if the separation between this last-mentioned "secondi'-type transition and the final "first"-type transition is not less than 1.5T. In FIG. llF, if a "second"-type transition is produced in response to the second group of three binary "O"s, this "second"-type transition will be spaced from the final "first"-type transition by 0.5T. Since this condition is to be avoided, FIG. llF illustrates that such a "second"-type transition is not produced in , 8~

response to the last group of three binary "O"s.
Ho~ever, in FIG. llG, a "second"-typ~ transition is produced in response to the second group of three binary "O"s; and this "second"-type transition is spaced fro~ the final "first"-type transition by 1.5T.
It is seen from the waveforms shown in FIG. 11 that the maximum transition interval TmaX in this embodiment is equal to 4T. If four or more successive binary "O"s are p.resent in the input digital data, the initial transi-tion interval is equal to 3.5T if the binary "O"s arepreceded by the combination 01, and the initial transition interval is equal to 3.0T when the binary "O''s are preceded by ~he combination 11. Thereafter, a "second"-type transi-tion is produced in response to each group of three successive binary "O"s, provided that the minimum separation between succeeding transitions is no less than 1.5T. When this condition does not obtain, as shown in FIGS. llF and llI, the "second"-type transition is not produced.
The encoded waveforms shown in FIGS. 10 and 11 ~0 are distinauishable from each other in that, for example, except for FIG. llA, a transition interval of 2T is not present in the encoded representation of successive binary "O"s. Furthermore, in the encoded representation of successive binary "l"s, the initial transition interval is equal to 1. ST, whereas the initial transition interval associated with the encoded representation of successive binary "O"s is either 3T or 3.ST. Still further, for an even number of successive binary "l"s, succeeding transition intervals of 2T are present, and for an odd number of successive binary "l"s, the last two transition intervals are seen to be 3T followed by 2T. These characteristics ' are not present in the encoded representations of successive binary "0"s. These differences can be used in a modification of the decoder shown in FIG. 8, whereby successive binary "ons can be distinguished from successive binary "l"s as represented by the encoded waveforms.
FIG. 12 is a block diagram of.an encoder 21 which is readily adapted to carry out the encodina scheme represented by the timing diagrams o FIGS. 10 and 11. It is appreciated that encoder 21 is similar to encoder 1 of FIGo 4, and includes a shift .regi.ster 22, similar to shift register 2, but comprised of five stages al .... a5, a logic circuit 25, which perrorms a function analogous to ROM 5, a shift register 26, similar to aforeclescribed shift register 6, a multi-stage shift register 28, similar to shift reqister 8, and a logic gating circuit 31, similar to aforedescribed log.ic gating circuit 11. Shift register 22 is coupled to a data input terminal 23, from which successive binary bits of the input digital data are received. The shift register also is cou~led to a clock pulse input terminal 24 to receive clock pulses CPl, described above.
The contents of stases ala2a3a4a5 o~ shift register 22, together with bit x, are supplied to logic circuit 25.
Depending upon the status of the respective bits supplied thereto, this logic circuit generates bits blb2, which bits are supplied in parallel to shift register 26. More `~ ~
~L7~

particularly, logic circuit 25 produces bits bl and b in accordance with the ollowing Boolean equations:

1 1 a2 + x al (a2 + a3 . a4 . a ) (5) b2 = al a2 (6 As before, bits bl and b2 are loaded, parallel-by-bit into shift register 26 in response to a load pulse LD (FIGo 6C).
Shift register 26, as well as multi-stage shift register 28, is coupled to a clock pulse input terminal 29 to receive clock pulses CP2 (FIG. 6B). Thus. in response to successive ones of clock pulses CP2, bits b1 and b2 are shifted from shift register 26 into sequential stages GFEDCBA
of shift register 28. As each bit blb2 is shifted out of stage A of the multi-stage shift register, code biks of one-half bit cell duration are generated, sequentially, at output terminal 30.
The contents of stages A...G of shift register 28, to~ether with the contents of stage al of shift register 22, are supplied to logic gating circuit 31. This logic gating circuit implements the following Boolean equation to produce bit x:

x = (A+B) . (D~E~ . (F~G) . al ~ ~F+G) . al (7) Of course, bit x, in conjunction with ~its ala2a3a4a5 in shift register 22 are used by loqic circuit 25 to generate .

" 1:17~0 bits bl and b2 in accordance with equations ~5) and ~6).
In the interest o brevity, and to avoid sub-stantial duplication o~ explanation, a detailed descripti,on . of the operation of encoder 21 is not provided. It will be readily apparent to those of ordinary skill in the art that this encoder operates in a manner similar to that described hereinabove with respect to the er~odiment of encoder 1.
If desired, logic circuit 25 may be replaced by, for example, a read only memory having 64 storage locations, each being addressed by the 6-bit signal xala2a3a4a5, and each storaae location storing appropriate bits bl and b2, so as to read out these bits to shift register 26 in response to the particular address signals supplied to the ROM.
It is appreciated that encoder 21 generates the encoded versions of successive binary "l"s and "0"s as illus~rated in FIGS. 10 and 11. Advantageously, a frame synchronizing signal FS, fully distinguishable fro~ the encoded data, is inserted into the encoded representations of digital data in order to synchronize the operatio~ of a decoder which is compatible with the encoder shown in FIG. 12. It would appear that the frame synchronizing signal shown in FIG. 7B may be used with the encoder of FIG. 12. Another pattern of -transition intervals which can be used as the fra~e synchronizing signal E'S is illus-trated in FIG. 13, together with the coded bits representing such transitions. Successive transition intervals of 4T, followed by 3.5T, f'ollowed by 2T, are not present in the _ A '~_ encoded waveforms shown in FIGS. 10 and 11. Thus, the frame synchronizing signal represented in FIG. 13 is easily distinguished from the encoded data. The initial.
transition of this frame synchronizing signal may coincide with the middle of a bit cell interval or, alternatively, may coincide with the boundary bPtween adjacent bit cell-intervals.
FIG. 14 illustrates an embodiment of a decoder 32 which is compatible with encoder 21 and which is readily adapted to recover the original digital data in response to receiving coded bits corresponding ko the encoded waveforms of FIGS. 10 and 11. Decoder 32 includes a shift register 34, comprlsed of skages Cl ... C15, a logic circuit 35 and a logic circuit 36. It is seen that this is similar to shift register 14, logic circuit 15 and logic circuit 16, respectively, of FIG. 8. Shi~t register 34 is connected to an input terminal 33 to receive coded bits representing the transitions of the encoded data.
A shift pulse input of shift register 34 is coupled to an input term.inal 38 to receive clock pulses CP3. These clock pulses are similar to those described hereinabove with respect to FIG. .~.
The outputs of stages Cl-Cg, Cll, 13 15 all are coupled to respective inputs of logic circuit 35.
This logic circuit implements the ~olI`owing Boolean Pquation Y 6 5--8-cll~cl5+c9~ (C3~cl3+c4+C5) + C7.(Cl.c ~ CZ+c3+c4~ . (8 _A A_ ~l~7~

The resultant output y produce~ by logic circuit 35 is supplied to latch circuit 36. This latch circuit, being similar to aforedescribed latch circuit 16, is set or reset in timed synchronism with clock pulses CP4, depending upon whether output ~ is a binary "1" or "0", respectively. The state of the latch circuitr that is, whether it is set or reset, is represented by an output signal supplied to output termina} 37. This output sianal corresponds to the original input digital data which is recovered from the coded bits serially shifted into shift register 34.
The operation o decoder 32 is similar to that set out in detail hereinabove with respect to decoder 12.
Therefore, in the interest of brevity, this explanation is not repeated. Suffice it to say, however, that as the representations of transitions are serially shifted through shift register 34, logic circuit 35 serves to - compare the separation between such transitions to predetermined "window" intervals to produce an output y depending upon the relationship between the measured ~ transition intervals and these "window" intervals~
If desired, lo~ic circuit 35 may be replaced by a suitable ROM which is addressed by the contents of shift register 34 to read out a corresponding output y, consistent with equation (8jo If the encoded version of the input digital data, as produced by the embodiments of the encoder 8~

disc~ssed hereinabove, are recorded as an audio PCM signal on, for example, a vide disc record medium, the frame synchronizing signal ~S, discussed above, might not be recorded. In that event, clock pulses CP3 and CP4 must be deri~ed from the reproduced data stream. Since the maximum transition interval TmaX is relatively short, in accordance with one advanta~eous feature of the present invention, such synchronous reproduction is readily obtained.
Even i.f the actual transition interval in the reproauced data stream exceeds the aforementioned maximum, due to time base fluctuations, or the like, the encoded data nevertheless may be readily decoded~
While the present invention has been particulaxly shown and described.with reference to certain preferred embodiments, it should be readily apparent to those of ordinary skill in the art that various chanaes and modifi-cations in form and details may be made without departing from the spirit and scope of the invention. ~t is, therefore, intended that the appended clai~.s be interpreted as including all such changes and modifications.

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method of decoding digital data having transitions therein r wherein the separation between succeeding transitions represents a particular number of successive binary bits of a particular bit value, said method comprising the steps of measuring the separation between succeeding transitions; determining if the separation between two succeeding transitions is less than or greater than a pre-determined amount; producing successive binary bits of a first value when said separation is determined to be less than said predetermined amount; and producing successive binary bits of a second value when said separation is determined to be greater than said predetermined amount.

2. The method of Claim 1 wherein the maximum separation between succeeding transitions in data representing at least three successive binary bits of said first value is less than the minimum separation between the first two transitions in data representing at least three successive binary bits of said first value; and said predetermined amount is substantially equal to said last-mentioned minimum separation.

3. The method of Claim 2 wherein said step of measuring the separation between succeeding transitions comprises providing a predetermined bit of predetermined duration representative of a transition; and loading said predetermined bits into a multi-stage shift resister in synchronism with timing pulses; whereby the particular stages of said shift register which are occupied by said predetermined bits provide a measurement of the separa-tion between succeeding transitions.

4. The method of Claim 3 wherein the storage capacity of said shift register is sufficient to accommodate concurrently the predetermined bits representing at least three succeeding transitions in data representing successive binary bits of said first value.

5. The method of Claim 4 wherein the storage capacity of said shift register is sufficient to accommodate concurrently the predetermined bits representing at least three succeeding transitions in data representing successive binary bits of said second value.

6. The method of Claim 3 wherein said step of determining if the separation between at least the first two succeeding transitions is less than or greater than a predetermined amount comprises comparing the contents of preselected stages of said multi-stage shift register to each other, said preselected stages being separated from each other by amounts equal to the expected separation between transitions representing successive binary bits of said first and second values, respectively.

7. The method of Claim 6 wherein said timing pulses have a period equal to one-half the interval of a bit cell and wherein said expected separation between transitions is an integral number of timing pulse periods;
and wherein said step of comparing the contents of preselected stages of said multi-stage shift register includes the step of comparing the contents of stages separated from each other by an amount corresponding to a range of 3 to 6 timing pulse periods to determine if said predetermined bits are present in said compared stages.

8. The method of Claim 7 wherein said step of producing successive binary bits of a first value when said separation is determined to be less than said predetermined amount includes the step of generating a binary bit of said first value when said predetermined bit is present concurrently in said compared stages.

9. A method of decoding digital data having transitions therein, wherein the separation between succeeding transitions represents successive binary bits of a first value if said separation is less than a predetermined amount and said separation represents successive binary bits of a second value if said separation is more than said predetermined amount, said separation being confined to a predetermined range, said method comprising the steps of comparing the separation between succeeding transitions to first and second sets of window intervals, said first set of window intervals being equal to the expected separations representing successive binary bits of said first value and said second set of window intervals being wider than said first set and being equal to the expected separations representing suc-cessive binary bits of said second value; producing binary bits of said first value when the separation between succeeding transitions is equal to an interval defined by a window interval included in said first set; and producing binary bits of said second value when the separation between succeeding transitions is equal to an interval defined by window interval included in said second set.

10. Apparatus for decoding received digital data having transitions therein, wherein the separation between succeeding transitions represents a particular number of successive binary bits of a particular bit value, said apparatus comprising means for measuring the separation between succeeding transitions; means for determining if the separation between two succeeding transitions of said received data is less than or greater than a predetermined amount; and means for producing successive binary bits of a first value when said means for determining determines that said separation is less than said predetermined amount, and for producing successive binary bits of a second value when said means for determining determines that said separation is greater than said predetermined amount.

11. The apparatus of Claim 10 wherein said means for measuring comprises means for providing a predetermined bit of predetermined duration representative of a transition;
a source of timing pulses; and multi-stage shift register means for receiving said predetermined bits in synchronism with said timing pulses; whereby the particular stages of said shift register means which are occupied by said predeter-mined bits provide a measurement of the separation between succeeding transitions.

12. The apparatus of Claim 11 wherein said deter-mining means comprises means for comparing the contents of preselected stages of said multi-stage shift register means to each other, said preselected stages being separated from each other by amounts equal to the expected separation between transitions representing successive binary bits of said first and second values, respectively.

13. The apparatus of Claim 12 wherein said timing pulses have a period equal to one-half the interval of a bit cell and wherein said expected separation between transi-tions is an integral number of timing pulse periods; and wherein said means for comparing compares the contents of stages separated from each other by an amount corresponding to a range of 3 to 6 timing pulse periods to determine if said predetermined bits are present in said compared stages.

14. Apparatus for decoding received digital data having transitions therein, wherein the separation between succeeding transitions represents successive binary bits of a first value if said separation is less than a predeter-mined amount and said separation represents successive binary bits of a second value if said separation is more than said predetermined amount, said separation being confined to a predetermined range, said apparatus comprising means for defining first and second sets of window intervals, said first set of window intervals being equal to the expected separations representing successive binary bits of said first value and said second set of window intervals being wider than said first set and being equal to the expected separations representing successive binary bits of said second value;
means for comparing the separation between succeeding transi-tions to said first and second sets of window intervals; and means for producing binary bits of said first value when the separation between succeeding transitions is equal to an interval defined by a window interval included in said first set and for producing binary bits of said second value when the separation between succeeding transitions is equal to an interval defined by a window interval included in said second set.