CA1167968A - Method and apparatus for encoding and decoding digital information - Google Patents
Method and apparatus for encoding and decoding digital informationInfo
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- CA1167968A CA1167968A CA000367992A CA367992A CA1167968A CA 1167968 A CA1167968 A CA 1167968A CA 000367992 A CA000367992 A CA 000367992A CA 367992 A CA367992 A CA 367992A CA 1167968 A CA1167968 A CA 1167968A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Abstract
ABSTRACT OF THE DISCLOSURE
Digital data formed of binary bits of first and second values occupying consecutive bit cells of predeter-mined intervals are encoded such that successive binary bits of the first or second values are represented by predetermined separations between succeeding transitions.
A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a binary bit of the first value. When successive binary bits of the first value are sensed, a respective second transition is produced at a second reference point in a bit cell after sensing every 2 or 3 binary bits of the first value. When successive binary bits of the second value are sensed, a respective second transition is produced at the second reference Point in a bit cell when at least two successive binary bits of the first value are followed by a binary bit of the second value and also after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned second transition at the second reference point is separated from the closest first transition thereto by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of the second transi-tions are separated from each other by no more than 4 bit cell intervals.
Digital data formed of binary bits of first and second values occupying consecutive bit cells of predeter-mined intervals are encoded such that successive binary bits of the first or second values are represented by predetermined separations between succeeding transitions.
A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a binary bit of the first value. When successive binary bits of the first value are sensed, a respective second transition is produced at a second reference point in a bit cell after sensing every 2 or 3 binary bits of the first value. When successive binary bits of the second value are sensed, a respective second transition is produced at the second reference Point in a bit cell when at least two successive binary bits of the first value are followed by a binary bit of the second value and also after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned second transition at the second reference point is separated from the closest first transition thereto by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of the second transi-tions are separated from each other by no more than 4 bit cell intervals.
Description
;'79~3 13ACKGROllND OF l'}~E INV NTION
_ This invention rela~es to digital data encoding/decodin~
techniques and, more particularly, to such encoding and decoding techniques wherein successive binary bits of first or second values are represented by the separation between succeeding transitions, these transitions having predetermined minimum and maximum separations. The encoded data is particularly applicable for direct recording on a record medium, such as a magnetic tape, a rotary disc, and the like.
Record media and di~f~rent types of data transmission channels exhibit characteristics such that so-called raw digital data is not easily recorded/reproduced or transmitted/received with sufficient fidelity. To avoid distortion and 105s of information, various encoding techniques have been proposed whereby the usual binary "l"s and "0"s are converted to suitably coded form which is more accurately recorded or .
transmltted. One example of such an encoding techni~ue converts an m-bit data word, formed of m binary bits, into a _-bit data word, as disclosed i~ United States Patent No. 4,323,931. Another encoding technique is known as a "three position modulation" encoder, whereby digital data is encoded in a so-called look-ahead code by which the dens~ity o~ the recorded data is increased.
In the three position modulation encoder, succeeding binary "l"s are separated from each other by at least two binary "0"s. By reason of this s~paration, the minimum interval .
.
-79~
between succeeding transitions is equal to three bit cell intervals, wherein a bit cell is an interval, or duration, occupied by a binary bit. That is, if a binary "l" is represented by, for example, a signal voltage that is greater than the signal voltage representiny a binary "~", th~ transitions between "l"s and "O"s are separated by at least 3T, wherein T is equal to the bit cell interval.
If the digital signal which is produced by the three position modulation encoding technique is further converted to, for example, NRZI form, then the minimum separation between succeeding transitions, referred to herein as the transition interval, Tmin, and the maximum transition inter-max' are setat Tmi ~ l 5: T a ~ T
When digital data is recorded on a magnetic medium, certain constraints must be placed upon the minimum transition interval Tmin. That is, where a high recording data density is desired, the minimum transit~ion interval Tmin must be of sufficient duration to avoid a possible misinterpretation ~; of succeeding trans1tions that are spaced too closely to each other. That is; a transition that may-be spaced too closely to another may:be missed, or skippedt during a signal repro-ducing operation, thereby distorting the information which can be recovered. Although the minimum transition interval Tmin of the aforementioned three position modulation encoder : 25 is satisfactory, the maximum tran~ition interval TmaX of that encoder is, in many applications, too long. For example, ~a max1mum transition interval TmaX of 6T is not favorably disposed for~self-clocking. Hence, the synchronous reproduction ~ 2 -: .
7~
of data which has been encoded in three position modulation format may not be easily attained. Consequently, the reproduced data may be distorted, and valuable information may be lost.
OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved data encoding technique which avoids the aforenoted disadvantages of the prior art.
Another object of this invention is to provide a data encoding technique which can be used to record digital information with relatively high density, which information can be readily reproduced by means of self-clocking arrange-ments.
A further object of this invention is to provide a data encoding technique which is a marked improvement over the aforementioned three position modulation technique.
An additional object of this invention is to provide a data encoding technique wherein successive binary bits are represented by succeeding transitions in the encoded digital signal; and wherein the minimum transition interval is on the ord~r of about l.ST and the maximum transition interval is on the order of about 4T or 4.5T.
; Yet another object of this invention is to provide ; a data encoding technique which can be implemented by an encoder of relatively simple construction, and wherein the encoded data can be decoded by a compatible decoder also of simple construction.
A still further object of this invention is to provide an improved data encoding techniq~e wherein the encoded data is readily adaptable for self-clocking.
_ 3 _ '7961~
various other objects, advantages and features of the present invention will become readily apparent from the ensuing detailed description, a~d the novel features will be particularly pointed out in the appended claims.
SUMMARY OF THE INVE TION
In accordance with khis invention, a data encoding technique is described, wherein an encoded digital signal is produced having transitions therein, the separation between succeeding transitions represen~ing successive binary bits of first or second values. A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a blnary bit of the first value. When successive binary bits of the first vaIue are present, a respective second transltion is produced at a second reference point in a bit cell after sensing every
_ This invention rela~es to digital data encoding/decodin~
techniques and, more particularly, to such encoding and decoding techniques wherein successive binary bits of first or second values are represented by the separation between succeeding transitions, these transitions having predetermined minimum and maximum separations. The encoded data is particularly applicable for direct recording on a record medium, such as a magnetic tape, a rotary disc, and the like.
Record media and di~f~rent types of data transmission channels exhibit characteristics such that so-called raw digital data is not easily recorded/reproduced or transmitted/received with sufficient fidelity. To avoid distortion and 105s of information, various encoding techniques have been proposed whereby the usual binary "l"s and "0"s are converted to suitably coded form which is more accurately recorded or .
transmltted. One example of such an encoding techni~ue converts an m-bit data word, formed of m binary bits, into a _-bit data word, as disclosed i~ United States Patent No. 4,323,931. Another encoding technique is known as a "three position modulation" encoder, whereby digital data is encoded in a so-called look-ahead code by which the dens~ity o~ the recorded data is increased.
In the three position modulation encoder, succeeding binary "l"s are separated from each other by at least two binary "0"s. By reason of this s~paration, the minimum interval .
.
-79~
between succeeding transitions is equal to three bit cell intervals, wherein a bit cell is an interval, or duration, occupied by a binary bit. That is, if a binary "l" is represented by, for example, a signal voltage that is greater than the signal voltage representiny a binary "~", th~ transitions between "l"s and "O"s are separated by at least 3T, wherein T is equal to the bit cell interval.
If the digital signal which is produced by the three position modulation encoding technique is further converted to, for example, NRZI form, then the minimum separation between succeeding transitions, referred to herein as the transition interval, Tmin, and the maximum transition inter-max' are setat Tmi ~ l 5: T a ~ T
When digital data is recorded on a magnetic medium, certain constraints must be placed upon the minimum transition interval Tmin. That is, where a high recording data density is desired, the minimum transit~ion interval Tmin must be of sufficient duration to avoid a possible misinterpretation ~; of succeeding trans1tions that are spaced too closely to each other. That is; a transition that may-be spaced too closely to another may:be missed, or skippedt during a signal repro-ducing operation, thereby distorting the information which can be recovered. Although the minimum transition interval Tmin of the aforementioned three position modulation encoder : 25 is satisfactory, the maximum tran~ition interval TmaX of that encoder is, in many applications, too long. For example, ~a max1mum transition interval TmaX of 6T is not favorably disposed for~self-clocking. Hence, the synchronous reproduction ~ 2 -: .
7~
of data which has been encoded in three position modulation format may not be easily attained. Consequently, the reproduced data may be distorted, and valuable information may be lost.
OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved data encoding technique which avoids the aforenoted disadvantages of the prior art.
Another object of this invention is to provide a data encoding technique which can be used to record digital information with relatively high density, which information can be readily reproduced by means of self-clocking arrange-ments.
A further object of this invention is to provide a data encoding technique which is a marked improvement over the aforementioned three position modulation technique.
An additional object of this invention is to provide a data encoding technique wherein successive binary bits are represented by succeeding transitions in the encoded digital signal; and wherein the minimum transition interval is on the ord~r of about l.ST and the maximum transition interval is on the order of about 4T or 4.5T.
; Yet another object of this invention is to provide ; a data encoding technique which can be implemented by an encoder of relatively simple construction, and wherein the encoded data can be decoded by a compatible decoder also of simple construction.
A still further object of this invention is to provide an improved data encoding techniq~e wherein the encoded data is readily adaptable for self-clocking.
_ 3 _ '7961~
various other objects, advantages and features of the present invention will become readily apparent from the ensuing detailed description, a~d the novel features will be particularly pointed out in the appended claims.
SUMMARY OF THE INVE TION
In accordance with khis invention, a data encoding technique is described, wherein an encoded digital signal is produced having transitions therein, the separation between succeeding transitions represen~ing successive binary bits of first or second values. A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a blnary bit of the first value. When successive binary bits of the first vaIue are present, a respective second transltion is produced at a second reference point in a bit cell after sensing every
2 or 3 binary~bits of the first value. When successive binary bits of the second value are present, a respective second transition is produced at~the second reference point in a bit cell when at least two successive binary bits of the first value are followed by a binary bit of the second value and al:o~after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned :econd ~ransition is separated from a first transition by at least 1.5 bit cell intervals but no more than 4.5 bit ; 25 cell intervals and successive onès of these second transi-tions~are :eparated from each other by no more than 4 bit cell interval:. In a preferred embodiment, when successive binary bits~of the first value are present, a second transition is produced after every two of these bits. If the total nu~ber of successive bits is odd, then one o~ the second transitions is produced a:Etex three such bits and, there-after, a second transition is produced after sensing each two successive bits. When the total number of successive bits of the second binary value is greater than 4, a second transition is produced, in one embodiment, after three such bits and, thereafter, after every four such bitso In another embodiment, the aforementioned second transition is produced after every 4 bits.
BRIEF DESCRIPTION OF THE DRAWINGS
The following detailed description, given by way of example, will best be understood in conjunction with the accompanying drawings in which:
FIGS. lA-lK, 2A-2H and 3A-3I are timing diagrams which are useful in understanding the encoding technique of the present invention;
FIG. 4 is a block diagram of one embodiment of the encoder in accordance with the present invention;
FIG. 5 is a table which is useful in understanding the operation of the encoder shown in FIG. 4;
FIGS. 6A-6C are timing diagrams which represent the various timing signals used in the encoder of FIG. 4;
FIGS. 7A :and 7B are timing diagrams which represent a synchronizing signal which can be inserted into the encoded data, in~accordance with the present invention;
FIG. 8 is a block diagram of one embodiment of a decoder which can be used to decode the data that has been encoded by the present invention;
i75~68 FIG. 9 is a timing diagram representing a modifi-cation of the encoding technique of the present invention;
FIGS. lOA-lOK and llA-llK are timing diagrams which represent another embodiment of the encoding technique of the present in~ention;
FIG. 12 is a block diagram of an encoder which can be used to carry out the encoding technique represented by the timing diagrams of FIGS. 10 and lli FIG. 13 is a timing diagram representing a synchro-nizing signal which can be inserted into the data encoded in accordan~e with the format represented by FIGS. 10 and 11;
and FIG. 14 is a block dLagram of a decoder which is compatible with the encoder shown in FIG. 12.
I)ETAILED iDEscRIpTIoN OF PREFERRED EMBODIMENTS
.. .. _ .. _ .. . . . . .. . _ ..
Referring now to the drawings, FIGS. lA-lK represent the encoding technique by which successive bi.nary "l"s are encoded into the preferred format by which succeeding transi-tions in the encoded digital signal, that is, the digital signal produced by way of the present invention, represents successive binary "l"s. In each of these figures, an initial~ transition lS produced when the input digital slgnal undergoes a change-over~from a binary "0" to a binary~ This transition is referred to herein as the "first transition" or "first-type" transition, and is produaed in substantially the middle portion o~ a bit cell. As used -hereinj~the expression "bit cell" reers to the interval or duration occupied by a binary bit of either "1" or "0"
; value.
3L1~7~6~3 When successive binary "l"s are encoded, after the first transition is produced at -the middle portion of a bit cell, the next-following transition is produced at the trailing edge of a b.it cell, ~hat is, this next-following transition, which is referred to herein as the "second"
or "second-type" transition, is produced at the boundary be-tween adjacent bit cells. For the purpose of the present description, a "first" transition is produced at a first reference point, that is, at the middle portion of a bit cell, and a "second" transition is produced at a second reference point, that is, at the trailing edge of a bit cell. This location of the transitions in the encoded data is si.milar - to that of the NRZI format. However, in the NRZI code, the minimum transition interval T that is produced in response to successive binary "l"s is equal to lT, and the maximum transition interval that is produced in response to successive binary "O'ls has no limitation. The present invention differs from these conditions of the NRZI code in that the minimum transition interval Tmin that is produced in response to successive binary "l"s is equal to 1.5T (wherein T is equal to the bit cell interval), and the maximum transition interval TmaX is equal to 4.5T or even 4T in response to successive binary ""s.
~ In the encoded data produced in response to the 25 lnput digital signal ~010] shown in ~'IG. lA, only a single transition in the encoded signal is produced, this single transition aoinciding with the middle portion of the bit 96~
cell which is occupied by the binary "1". The waveform produced by this encoded data is shown benea~h the repre-sentation of ~010~, and a digitized version o this wave-form is represented therebeneath. This digitized version of the waveform contains bits whose bit cells are equal to one-half the bit cell duration of the input digital data; and a transition in the encoded data waveform is represented by a binary "0" bit of one-half bit cell duration followed by a binary "1" bit of one-half bit cell duration. Although not shown herein, it may be appreciated that the transition ln the waveform shown in FIG. lA may be a negative transition, that is, the waveform may undergo a change from its relatively higher level to its lower level.
Nevertheless, the digitized representation of such a transi-tion is represented by digitized bits 01.
As shown in FIG. lB, input digital data [0110]
is encoded in a manner such that a first transition is produced in the middle of the bit cell containing the first binary "1", and a second transition is produced at the trail-ing edge of the bit cell containing the last binary "1", that is this second transition is produced at the bo~nda~y of the bit cells~containing the binary signals 10. The separa-tion between these first and second transitions is equal -to 1.5T, wherein T is equal to the bit cell interval. It will be apprec~a-ted that a "first" transition is produced in the middle of a bit cell interval when the input digital data ~undergoes a changeover from a b~nary "0" value to a binary "1" value. A "second" tra~sition is produced at the trailing edge~of a bit cell interval in accordance with the following condi~ions: (a) a changaover from a binary "1" to a binary "0"; or (b) after a predetermined number of successive binary "l"s or "0" have been received, provided that succeeding transitions are separated by no less than Tmin = 1 5T. These conditions are not mutually exclusive and, as will be explained in greater detail below, a "second" transition is not produced in accordance with condition (a) if such a second transition would follow a "first" transition by less than a predetermined amount. In encoding the input digital data shown in FIG. lB, the irst and second transitions are separated by 1.5T, that is, by 1.5 bit cell intervals.
Referring to FIG. lC, the input digital data[011.10]
is encoded such that a first transition is produced in the ~iddle of the bit cell inter~aL containing the first binary :: 15 "1'l/ and a second transition.:is.produced at the trailing edge o the bit cell containing the last binary "1". Thus~ the total.separatiQn between these transitions is seen to be equal to 2.5T. ~ binary "1" is not~produced at the boundary separating the bit cells containing the second and third 20. binary "l."s because this would result in a separation between two transitlons by an amount equal l.OT. In the present in~ention, the predetermined minimum separation Tmin ibetween succeeding transitions is equal .1.5T. Thus, the ., requirement of condition (b) above would prohibit the production, 25 ~-in:encoding the data shown in FIG. lC, of a transition between , the second and third binary "l"s.
When the number o successive binary "l"s is ~rea.ter than 3, a "second" transition is produced after every 2 or:3 successi~e "l"s~ as will be described.
_g_ 7~
Stated otherwise, a "~irst" transition is produced in the middle of the bit cell containing the first of the binary "l"s (that is, following the change over from a binary "0" to a binary "1") and a second transition is produced after every : 5 n successive binary "l"s wherein n = 2 or 3, _ provided that condition (b) above is satisfied. Thus, to encode the input digital signal [011110], the first transition is produced in the middle of the bit cell containing the first binary "1", and a respective second transition is produced after every 2 successi~e binary "l"s.
Consequently, the first two transitions in the encoded data are separated by 1.5T, and the next two transitions are separated by 2T.
:In FIG. lE,~the first transition is produced in the middle o~ the bit celI containing the ~irst binary "1", and then a:second transition;is produced at the trailing edge of the bit cell containing the~second binary "1". Then, the next ."second" transition is produced follo~ing the next.3 binary "l"s. It is recognized that a "second" transition cannot~be produced after every 2 binary "l"s to encode the~data.shown in FIG~ lE because this would result in a separation between the last two transitions by an amount : equal to lT~.
From FIGS. lF-lK, it is seen that if the total number of successive binary "l."s in the input digi.tal data lS an even number in excess of 3, then a respective transition . is produced after every two successive binary "l"s. However, if the total number of successive binary "l"s is an odd number.in excess of 3, then a transition is produced after 1.~l :i'~96Z~
every two successive binary "l"s, except that the last five binary "l"s are divided into two groups, the first group consisting of 2 binary "l"s and the second group consisting of 3 binary "l"s. Hence, if the total number of successive binary "l'is is an odd number in excess of 3, then two transi-: tions will be separated from each other by a maximum of 3T.
In FIGS. lG, lI and lK, this maximum separation is provided between the last two transitions. If desired, this maximum separation can be provided between any other pair of trans-L0 tions, such as between the second and third transitions, the third and ourth transitions, the fourth and fifth transitions, and the like. Of course, the separation between the first two transitions, as shown in FIGS. lD-IK, is equal to Tmi = 1.5T.
~s a.modification o~.the example represented by ~Ies. lP-IK, a transition can be produced after every 3 .successi~e binary "l"s. This.would result in the encoded wa~eforms shown in FIGS.. lD-lG. Howe~er, if the input digital data.is as.sho~n in FIG. lH, then, a~ter the initial minimum separation of l.5T between the first two transitions, as shown, the next transition would be produced after 3 binary "l"s and then another transition would be produced after the next-f:ollowing 3 binary "l"s. This would result in the usual minimum.separation o~ 105T between the ~irst two transitions, ~25 and then the remain.ing transitions would be separated by 3T.
:~To encode the input digital data shown in FIG. lI, the first two transitions would be separated by 1.5T, then the next-;following transition would be separated by 3T, and `
~7~6~
then the remaining transitions would bP separated by 2T. To encode the input digltal data shown in FIG. lJ, the first two transitions would be separated by 1.5T, the next-following transitions would be separated by 3T, the next-following transition also would be separated by 3T, and then the final transition would be separated by 2T. To encode the input digital data shown in FIG. lK, th0 first two transitions would be separated by 1.5T, and then all of the following transitions would be separated by 3T. Thus, where possible, a transit:ion is produced a~ter e~ery 3 binary "l"s, provided that thi~s does not result in a separation between succeeding : transitions which is less than the minimum separation of 1.5T.
As yet another example, successive binary "l"s can be divided into groups of three "l"s and groups of two lS "l"s alternately. Hence, lf the input digital data contains 9 successive binary "l"s~ these successive bits may be divided . into a group of 2, followed by another group of 2 bits, followed by a group of 3 biis~ and then followed by a group~
of 2 bits,::wlth a transition being produced at the trailing edge of each group. The encoded:waveform thus will exhibit transitions which~are separated by 1.5T, 2T, 3T and 2T, respectively. If the input digital data contains ten successive binary "l"s, these bits may be divided into a group of 2, , fo~lowed by a group of 3, followed by a group of 2 and ;~ 25 ~ollowed by a group of 3 such bits. The encoded waveform thus :~. wi~l be provlded with transitions which are separated by 1.5T, 3T, 2T and 3T, respectlvely. Nevertheless, even in this mDdified e~ample, `, ; ' :
~ -12-. i ;'79~8 the minimum separation between succeeding transitions is seen to be 1.5T.
The foregoing has described the encoding of input digital data wherein that data contains successive binary "I"s.
FIGS. 2 and 3 represent the encoding of data which contains successive binary "o"s. FIGS . 2A-2H represent the encoding of input digital data in which successiye binary "O"s are preceded ~: by the combination 01. FIGS. 3A-3I represent the encoding of input digital data in which the successive binary "o"s are preceded~by the combination 11. In PIGS. 2A-2H, a "first!'-type transition is produced in the middle of the bit cell containing the first binary "1". Of course, another "first" transition is produced in the middle of the bit~ cell containing the binary "1" which ollows the successi~e binary "O"s. In FIGS. 3A-3I, the initial.transition is.a "second"-type transition which is produced at the trailing edge of the blt cell containing the : binar~. "1" which precedes the successi~e "O"s. A "irst"-type transition is produced in the middle of the bit cell containing .the.binary 'll" which follows the.successive "O"s.
In FIG. 2A, a transition is produced in the middle o~
each bit cell containing a binary "1"~ and these transitions are seen to be sep rated by 2T. In FIG. 3AJ the initial transition is produced at the boundary between the bit cells containing the binary "l"
and binary '0", =espectively, and the next-following .
transition is produced in the middle of the bit cell containing the next binary "1". Hence, in FIG. 3A, the illustrated transitions are separated by 1.5T.
In FIG. 2s, transitions are produced in response to the change-over of a binary "0" to a binary "1", thereby resulting in a separation of 3T between these transitions.
It is preferred that a transition not be produced at the boundary between successiye binary "o"s because this will result in two succeeding "transition intexvals" exhibiting 10 minimum separation Tmin = 1.5T. In FIG. 3B, the initial ., ; transition is produced at the boundary between the prefix 11 : and the successive binary "O."s; and the next-following transition is produced in response to the change-over from binary "0" to "1", ;This latter transition is a "first!',.type transition and, thus, occurs in the ~iddle of the bit cell containing the changed-over binary "1".
As shown in FIG. 2C, ~hen the input digital data is ~,010001], transitions are produced at the middle of those bit cells which contain a binary "1". Hence, these transi-tions are separated by the txansition interval of 4T. It is . preferred that a transition not be produced at the trailing ¦ edge of the bit cell containing the first of the successive l} binary "O"s in order to distinguish successive binary "o"s ., from successive binary "l"s. It is recalled that, in response to successlve binary "l"s, the first two transitions areseparated by:the min~m transition interval ~min = 1.5T. Also, to improve such discr~Dation between succes ive "l"s and "o"s, it is preferred that a 96~
transition not be produced at the trailing edge of the bit cell containing the second binary "0". Likewise, in FIG. 3C, the beginning of the successive binary "o"s is represented by a "second"-type transition, and it is preferred not to produce another of these "second"-type transitions at the trailing edge of the bit cell containing the second binary "0".
FIG. 2D represenis the input digital data [0100001].
If this data is encoded by producing transitions only in the middle of the bit cells containing the illustrated binary "l"s, then the separation between such transitions would be equal to 5T. In the present invention, the maximum separation, or transition interval Tmax, is.selected to be 4.5T. Hence, if.t~e input digital data of FIG. 2D.is encoded in the aforementioned manner, the separation between transitions would exceed TmaX. To a~oid this possibility,.a.."second"-type transition is produced at the trailing edge of the bit cell containing the third binary "0", as illustrated.
This resuIts in a separation between the first two transi-ti~ns of 3.5T, and a~separation.between the last two 20..transitions of 1.5T. Thus, the illustrated transition inter~als are greater than Tmin and less than TmaX.
In ~IG..3D, i~: a transition is produced at the -txailing edge of the bit cell containing the third binary "o", the resultant transition inter~als in the encoded waveform will be greater than Tmin and less than TmaX However, f a "second"-type transition is produced at the beginning of the~successive binary "0"s, and then the next transition is not produced until a~ter the change over from binary "0"
-I5~
-to binary "1", as illustrated/ the .resultant transition interval will be equal to T = 4.5T. This latter encoding is max preferred.
From FIGS. 2C and 2D, and also from FIGS. 3C and 3D, it is obs~rved that, if the input digital data contains three or more successive binary "O"s, then the transition interval between the first two transitions should be no less than 3. 5T .
In view of this condition, a transition is not provided at the boundary between the last two.binary "O"s in FIG. 3D.
From FIGS. 2E-2H,.it is appreciated that, if successive binary "O"s are preceded by the combination 01, then,:a~ter the ~irst transi~ion (which is produced at the middle of the b.it cell containing the binary "1"), the next transition i5 produced after three successive binary "o"s, and, therea~terj a "second"-type transitlon is produced after the next 4.seccessive binary "o"s. Howe~er, a ."second"-type transition is not produced a~ter 4.successive binary "O"s i to do so would result in a.separation thereof from a "first!'-type transition by less than Tmin = 1.~5T. It is for this 20. reason:that a ."second!'-type transition is not produced after the final 4 binary "O"s in FIG. 2G. However, since this minimum separation requirement is not violated in FIG. 2H, a !':second!'-type transition is produced at the trailing edge of the bit cell containing the fourth binary "0" in the group of four "0"8, as illustrated. Thus, if the input diyital data contains 4 or more successive binary "O"s which are preceded by the combination 01~ then the transition interval defined by the first two transitions which are used as an encoded representation of the input digital data is equal to 3.5T.
~i'7~3168 :
From FIGS. 3D-3I, it is seen that, if 4 or m~re successive binary "o"s are preceded by the combination 11, an initial transition is produced at ~he boundary between the bit cells containing the chanye-over from binary "1"
to binary "0", and another transition is produced at the I trailing edge of the bit cell containing the fourth binary "0", ! provided that the transition interval between this transition and the next-following transition is not less than Tmin = 1.5T.
In FIG. 3D, if a transition is produced at the trailing edge of the bit cell containing the fourth binary "0"~, the transition interval be~ween this transition and the "first!'-type transition produced at the middle of the next-following bit cell will~be less than Tm1n. Hence, and as shown in FIG. 3D, a "second"-type transition is not produced at the trailing edge of the bit cell containi~g the fourth binary "0", resulting in a transition ~interval equal to TmaX - 4.5T. But, since the minimum transitlon inter~al Tmin-~is equaled or exceeded when 5 or more successi~e binary "O"s are present,-as shown in FIGS. 3E-3I, a "second"-type transition is produced at the trailing edge of the bit cell`containing the fourth binary "0".
Consequently, in FIGS. 3E-3I, the transition interval between the first two transitions of the encoded , waYeform is equal to 4T. Thereafter, another l'second"-type : : tran~sltion~is produced after every 4 binary "O"s, unless the:separation between this "second"-type transition and the :` :
, ~I7-;l ~7961!3 next-following transi.ti.on, such as the "first"-type transition shown in FIG. 3H, is less than Tmin- 1.5T.
A comparison between FIGS. 2D-2H and 3E-3I indicates that the transition interval bekween the first two transitions in the encoded waveform representing successive binary "O"s is equal to elther 3.5T or 4T. From FIG. 1, it is recalled that this ini-tial transition interval is on the order of l.5T. Hence,.
depending upon the inital transition interval, the encoded waveform representing successive binary 'il"s can be distinguished easily from the encoded waveform representing successi~e binary " 0 '~
: ~ Also, it is seen that,~ when successive binary IlO'ls are;encoded in the manner discussed above,~the maximum transition interval Tmax is limited to 4.5T, as shown in FIG. 2G and FIGS.
3D and 3H.
The encoding technique represented in FIGS. 2 and:3 may be described, generally, as pxoducing a l'first"-type :
transition at the middle of a bit cell containing a binary ; when the input digital:data ahanges over from a binary ~0 to a:binary~ and:a "second"-type transition~is produced :
: at~ the~trailing edge of a bit cell after every m successive binary "O"s wh~erein:m ~ 3 ~or 4. This general description is further~limited by the condition that a transition interval will~not exce~ed TmaX = 4.5T, nor will a transition interval 25~be~1ess~than Tmin = 1.5T. Furthermore, m - 3 to define the f~irst~trans~ition interval when successive binary "O"s are preceded by the c:ombination 01 and m = 4 to define the first transition~interval when sucaessive binary "O"s are preceded .
, i7~8 by the comb~tion 11. Thereafter, the transition interval between succeeding "second"-type transitions is seen to be 4T, as shown in FIG. 2H and FIGS. 3E 3I. Also, it is preferred that, where possible, the transition interval between the first two transitions in the encoded waveform be less than TmaX = 4.5T.
In any seguence of successive bits, minimum and maximum transition intervals Tmin and Tma occur only once in a sequence. That is, in the encoded waveform representing successive binary "l"s or "O"s, the minimum transition interval is not present more than once and, likewise~ the maximum transition interval also is not present more than once. It is appreciated that input digital data contalning successive binary "O"s may be encoded as:represented by FIG. 2 or FIG. 3, depending upon whether the successive binary "O"s are preceded by the combination 01 or by the combination 11.
In any event, when 3 or more successive binary "O"s are present, the initial transition interval is no less than 3.5T.
However, when the input digital data contains successive binary "l"s, the largest transition interval contained in the encoded waveform is 3T,:as shown in FIGS. lE, lG, lI and lK.
Therefore, in order to distinguish the encoded representation of successive binary "O"s from successive binary "l"s, the received . :
transition lntervals are compared to a reference predetermined interval which, in the present e~ample, is selected to be e~ual to 3.5T.
25 Ihat is, in order to decode the waveforms produced by the enox~r of the .' , present invention, the separation be-tween succeeding transi-tions is compared to this 3.5T standard. If the detected separation is less than 3.5Tr it is assumed that the encoded waveform represents successive binary "l"s. Conversely, if the detected separation between succeeding transitions in the encoded waveform is ~reater than 3.5T, the transitions are assumed to represent successive binary "0"s.
One embodiment of encoding apparatus which is readily adapted to carry out the encoding technique discussed hereinabo~e with respect to FIGS~ 1-3 is illustrated in FIG. 4. Encoder 1 is comprised of a shift register 2, a read only~memory (ROM) 5, a shift register 6, a multi-stage shl~t register 8 and a logic gating circuit 11. Shi~t register 2 is illustrated as a three-stage register having an input terminal 3 to ~hich input digital data lS
supplied, and a shift pulse input 4 connected to receive timing pulses, also referred to as clock pulses CPl.
Digital data is shifted from right-to-le~t, one stage at a ti~e,~in response to each timing pulse supplied to shi~t reglster 2. As illustrated, an input bit is shi~ted ihto~stage a3j and then~from stage a3 to stage a2, and then from~;stage,a2 to stage alr all in synchronism with successi~e timing pulses CPl. The contents of stages al, a2 and a3 are supplied~as three bits o~ a 4-bit address siynal to ROM 5. The fourth,bit of this address signal is designated as bit x,supplied to ROM 5 by logic gating circuit 11, to be described.
- -2,0-ROM 5 may be a conventional read only memory having, for example, sixteen separate storage locations, each storage location being addressed by the 4-bit address signal supplied thereto, and each of the sixteen storage locations storing a 2-bit signal. This 2-bit signal is read out from the addressed storage location of ROM 5 and loaded, parallel-by-bit, into shift register 6. AS illustrated, shift register 6 is a 2-bit shift register having stages bl and b2 therein.
Shift register 6 includes a load input terminal 7 LO adapted to recei~e a load:pulse~LD for loading the 2-bit signal read out of ROM 5 into stages bl and b2. This shift register also lncludes a shlft~pulse input coupled to a clock puLse texminal 9 for receiving clock, or timing pulses CP2.
The contents of shift register.6 are shifted ln synchronism with cLock pulses CP2 in t~e xight-to-left direction. Hence, in response to two successiYe clock,.:pulses CP2, the bit loaded . .
:.into~stage bl is shifted out~therefrom ~hile the bit which had been loaded into stage b2~is shifted~thereinto, and then this bit lS shifted out of:stage bl. The output of shift reglster.6:~1s supplled serially-by-bit to multi-stage shift register 8 ~hich, in the illustrated embodiment, is an 8~stage shift register~including:.stages A-H. Thls shift register ~lso includes a shift pulse input connected to clock pulse ~ input:~terminal 9 to receive clock'..pulses CP2 so as to :~ 25~synchronously shit~bits therethrough in the right-to-left ~direction in response to each clock pulse. An output ~terminal 10 lS coupled to the left-most stage A to receive the contents of shift register 8 which has been seriall~
shifted therethrough.
':
. -21-36~
Each stage A-H of shift register 8 is coupled to a respective input of logic gating circuit 11. An additional input of this logic gating c.ircuit is coupled to stage al of shift register 2. The logic gating circuit combines the various bits supplied thereto from shift registers 2 and 8 to produce bit x of the 4-bit address supplied to ROM 5.
This logic gating circuit implements the Boolean equation:
x~ +B). (C~D). (E~F)~ (G+H). al + (G~H). al (1 ~lthough not described in detail herein, one of ordinary skill in the art would be enabled to construct a suitable logic gating circuit to lmplement the foregoing equation.
In operation, clock pulses CPl are supplied ~ia clock input texminal 4 to shift re~ister 2. These clock pulses serve to.serially shift into shift register 2 the 15 particuIar digital data.supplied:thereto.~ia input termina~ 3. ~:
Clock pulses CPl are illustrated.in FIG~ 6A. For the purpose of the present discussion, it may be assumed that a binary bi.t is.shifted into.stage a3 of.shift register 2 in response to the positlve-going transition o~ olock pulse CPl. ~.-:......
Furthermore,:~each positi~e transition of:clock pulse CP
ser~es to shift the con.tents of shift reglster 2 to the left by one.stage. Prior to loading the next bit of the lnput~dlgital data into.shift register 2, the contents of ROM:5 are read out therefrom in response to the 4-bit address suppl~ied thereto, this 4-bit address being constituted as (xala2a3). This data read out of ROM 5 is loaded into .shift register 6 in response to the load pulse LD, shown in FIG. 6C. Then, after shift register 6 is loaded with data xepresented as blb2~ this 2-bit data is shifted into shift register 8 in response to the next 2 successive clock pulses CP2 shown in FIG. 6B. The contents of shift register 8 (ABCDEFGH?, together with bit al in shift register 2, are supplied to logic gating circuit 11 to produce bit x~ Thereaftex, the ~-bit address (xala2a3) reads out bits blb2 from ROM 5, these bits being loaded into shift register 6. The foregoing cycle is repeated periodically at the rate determined by clock pulses CPl. This cycle interval ECC is illustrated in FIG.:6.
As an example:of the operation of the encoder shown }n FIG.:4, let it be assume~ that the input digital data ~ ~011:1110~, shown in FIG. lE, is supplied to input terminal 3.
: Let lt be further assumed. that~, initially, the contents of shift reglster 8 are reset to zexo, b~its blb2 are (00) and bits.ala2:a3 are (000)O It.is fuxther:assumed that successi~e clock pulses CP2 axe generated at times to~ tl, t2 ..., and clock pulses CPl, which are one-half the frequency of clock pulses CP2, are generated at times to~-t2, t4 ... . At time to, the binary ~0~ of.the input digital data is.loaded into 20. stage a3 of shift reglster 2. Also, at times to and tl, bits blb2, which are assumed tQ be (?, are shifted into stages : G and H, respectively. Thus, at time tl, logic gating circuit 11 is supplied with bits A-H and al, all of which are a binary "0".i F:rom the foregoing equation, it is appreciated that bit : 25 x also is a~binary l~0~l. FIG. 5 illustrates the "memory map~
of ROM-5,~ from which it is appreciated that bits (00) are read : ~ out there~rom. These bits are loaded into shift register 6 in response to the load pulse LD following time point tl.
i'79~8 At time t2, the binary "l" included in the input digital data is loaded into stage a3. At times t2 and t3, the contents (00) o shift register 6 are loaded into stages G and H of shift register 8, and the contents (00) : 5 previously stored in stages G and H are shifted into stages E
and F, respectively. Logic gating circuit ll produces a binary "O" as bit x, such that ROM 5 now is addressed by the address signal (OOOl). AS shown in FIG. 5, ROM.5 now supplies the bits (00) to shift register 6 in response to the load pulse LD which ls produced after tlme point t3.
At time t4, the next binary "l" of the input digital data is loaded into stage a3, and the binary "l" previously .
-` stored in stage a3 is loaded into stage a2. Bits (00) which had been loaded into shift register 6 in response to the load pulse LD preceding time point t4 are.shifted into stages G and H at times: t4 and t5. At-these times, the contents:of stages E and F are~shifted into.stages C.and D, and the contents pre~iousLy stored in stages G and H are shifted into stages E
and F. Logic gating circuit ll still is supplied with 0...0 to produce a~binary "O" as bit.x. Now, however, ROM 5 is addressed by.the address signal ~OOll) to supply bits (Ol) to shift register 6. These blts are loaded into the shift register in response to the:next load pulse LD which precedes time point t6.
At time t6, the third binary "l" of the input.
digital data is shifted into stage a3, the binary "l"
`~`
;
:
.
7~
previously stored in this stage is shifted into stage a2, and the binary "1" previously stored in stage a2 is shifted into stage al. Furthermore, at times t6 and t7, .~ the contents (01) of shift register 6 are shifted into stages G and H, respectively, and, of course, the contents of stages C
and D are shifted into stages A and B, the contents of stages : E and F are shifted into.stages C and D, and the contents previously stored in stages G and H are shifted into stages E and F. Now, logic gating circuit 11 is supplied with a binary "1" from stage H and also with a binary "1" fram stage al of shift reglster 2. In accordance with the preceding Boolean ; equatlon, logic ~ating circuit ll produces a binary "1" as bit x. Consequently, ROM~S now is addressed~with the address signal (1111~ to supply bits :(00) to shift register 6. The load : 15 pulse LP~produced between.times t7 and t8 loads shift register 6 with:this (00) information.
The~foregoing operation.is repeated cyclically as the input digital data is shifted through shift register 2. Hence . encoder l~operates such that,:at times tl5, tl8 and t24, ~a binaxy "1", whose duration is equal to one-half the period of clock`pulses CPl,~is shifted to output terminal 10 from shift reglster 8. Thus, a binary "1" of duration 0.5T is produced at .
times tL5,~tl8 and t24. These binary "l"s represent the transi-tions of.the eneoded waveform; and if supplied to a flip-flop circuit~, a~toggle circuit, or the like will result in the ~a~e~orm illustrated in FIG. lE.
, .-25-~
'75~
It will be appreciated that encoder 1 functions to encode successive binary "l"s and successive binary "0"s in the manner described hereinabove with respect to FIGS. 1-3.
Thus, transitions having the aforenoted transition intervals are produced as encoded representations of the input digital data supplied to i.nput terminal 3.
In the foregoing description of encoder 1, it has been assumed that a read only memory is used to supply shift:register 6 with bits blb2 in response to the 4-bit address:signal ,(xala2a3). If,desired,:this read only memory may be rep}aced by a logic gating circuit to implement the table shown in FIG. 5. More par*icularly, the logic gating circuit ma~ be used to implement the ~ollowing Boolean equations:
bl = x.al. (a2 ~ a3) ~ x - al 2 (2) b2 al a2 (3) : It is seen that.the combination of shi~t register 2 an:d logic gating circuit l~ functions to sense the presence and~number:of,successi~e.binary~"l"s or "0"s,:.in the digital data.supplied to input terminal,3. ROM 5 is addressed in .
response~ to the.:sensing of such data to read out tharefrom ~si~na}s which are used.to,pxoduce "first"-type transitions the bit b2 is a binary "~l'i) or "second"-type transitions ~(if~the bit bl is a binary ''.l"). The foregoing equation (1) : , in aombination with reading out of the stored contents of : 25 ROM:5 insures a minimum transtion interval Tmin = 1.5T, 7~36~3 a maximum transition interval TmaX = 4.5T and a transition interval no greater than 4T hetween '~second"-type transitions, in the encoded data produced at output terminal 10. This combination also serves to determine if the total number of successive binary "1" s, for example, is greater than 3, is odd or is even. Furthermore, encoder 1 functions to sense the appropriate number of successive binary "0"s in order to produce the respective transitions discussed above with respect to FIGS. 2 and 3.
The encoded wa~e~orm derived by encoder 1 may be recorded on a.suitable record medium,.such as magnetic tape, - a magnetic disc, or the like. As one example, the encoded wa~eform may be recorded on a disc similar to a typical video disc. When recorded.in.this manner, it is desirable -15 that a frame.synchroniæing.signal FS:also be recorded. This ~rame synchronizlng signal lS used during a reproduction operation to synchron.ize..timing pulses which are used to decode - the encoded wa~e~orm, and thus.recover the original digital data. Preferably, the rame.s~nchronizing signal FS is insert-ed into the encoded waveform. That is, it is not recorded in aseparate location as a distinctive signal on the record medium.
Consequently, it is necessary that the frame synchronizing signal FS be distinguishable from the encoded data, yet it should:be o~ a similar ~ormat. One example of a suitable frame -25 .synchronizing signal;is illu~trated in FIGS. 7A and 7B.
The frame synchronizing signal is constituted by three transitions defining two.successive transition intervals -2.7-~179~8 equal to TmaX = 4.5T. As mentioned above, the encoded datawaveform representing successive binary "l"s and "O"s does not include consecutive transi-tion intervals equal to T
max Hence, the frame synchronizing signal FS is seen to be unique and may be readily detected when the encoded data waveform is reproduced or otherwise received.
The relationship between the frame synchronizing sign FS and a number of successive bit cells is illustrated in FIGS. 7A and 7B. It is seen.that the beginning and ending transitions of:the frame synchxonizing signal each coincides with.the middle o~ a bit cell, and the middle, or intermediate transition:of.the frame synchronizing signal coincides with the boundar~ between, adjacent~bit cells. With this relationship,.
clock pulses may be,synchroni.zed with the respective frame synchroniziny signal transitions. More particularly,~clock pulses having a frequency.similar to that of aforedescribed clock pulses CPl (FIG 6A)~may~be~synchronized with the intermediate,transition of the frame synchronizing signal; and clock pulses having a ~requency.similar to the aforedescribed clock puIses CP2 (FIG. 6B) may be synchronized with the beginning and:ending~transitions of the frame synchronizing signal.~ As.:~will be described below, such synchronized clock pulses may be used to decode the encoded data waveform so as to rec~er the original digital data.
: The frame,synchronizing signal comprises two .successive~:txansition inter~als, each equal to TmaX, which ~: are present~during.an.overall duration equal to 12T.
' : -2.8-~ l6'7~6~
It will be appreciated that encoder 1 does not produce an encoded waveform whereby two transition intervals T
max are produced during a duration of 12T. Hence, the frame synchronizing signal may be readily detected merely by establishing a refere.nce duration equal to 12T (or, if desired, equal to 11T) and by sensing consecutive transi-tion intervals TmaX during such a reference duration. This frame synchronizing signal is used to synchronize the code bits which~represent the transitions of the encoded data wa~eform, as well as the recovered binary bits. Furthermore, .the frame synchronizing.~slgnal may be used to synchronize fxame intexvals which,-in.some.applications, establish timing inter~als ln which data is recorded or tranzmitted.
One embodiment of,a decoder which is compatible with encoder 1 and which may,be used to recoYer,the original digital data from the,encoded:data waveforms shown in FIGS~ 1-3 is illustrated:in FIG:~ 8. This~decoder 12 is comprized of.a multi-stage.shift register 14 haYing an input .term3nal 13 connected to receive a digitized.version of the encoded data~wa~eform, and a shi~t pulse~input 1.8 connected ,to recei~e clockj or timing, pulses CP3. Timing pulses CP3:may~be simil~ar to aforedescribed~timing pulses CP2, .
ha~ing a frequency equal to twice the original data bit rate.
Encoder 12:also includes a logic gating circuit 15, which : :
~ay~be: comprised of Gonventional gating circuitry, adapted .to implement the following Boolean equation:
: : :
2 C6~C5 ~(Cg~ Cll ~ ~ ~C4 -~ C3) (C7-~Cg) ~ (C2~cl) C7 : :
(4) :
:-2.9~, wherein Y is the output produced by the logic yating circuit in response to bits Cl ... Cll supplied thereto. These bits are the contents of corresponding stages in multi-stage shift register 14.
5 The output of logic gating circuit 15 is coupled to a latch circuit 16, which may comprise a timing pulse controlled flip-flop circuit, or the like, coupled to a clock, or timing, pulse input 19 to receive clock pulses CP4.
The output produced by latch circuit 16 may be either a binary "1" or a binary "0", depending upon the state of the input:supplied thereto at the time of receipt of a clock pulse CP4. .This output is supplied to an output .terminal 17.
Clock pulses CP3 axe synchronized with the beginning and ending..transitions of.frame synchronl:zing signal FS, and clock:~pulses CP4 are synchronized:with the intermediate .transition~of this fxame.~synchronizing signal. It may be appreciated, therefore, that i the digitized.version of the encoded data~wa~eform;supp.lie~ to input terminal 13 represents each transition as a blnary ~ i of onè-half bit cell duration, when the binary "l" representing the beginning transition of the frame.synchronizing:signal shown in FIG. 7B is shifted from stage Cll to stage C~0 in shift register 14, a clock pulse CP4 .ls produced. Then, when this binary "1" is 2S :shlfted from stage Cg to stage C8, and then rom staye C7 to.stage C6, and then stage C5 to stage C~, and then from .s:tage C3~to stage C2, a respecti~e clock pulse CP4 is generated in timed synchronism therewith. It is further - appreciated that successive clock pulses CP3 serve to shift these bits from stagé-to-sta~e of shift register 14 in the , -30- ~
~167~
right-to-left direction.
As one example of the operation of decoder 12, let it be assumed that the encoded data waveform shown in FIG. 2G has been recorded. The original digital data ~100000001] thus is represented by the waveform wherein a "firs~"-type transition is produced in the middle of a bit cell interval, the next-following transition is separated therefrom by 3..5T, and an ending transition is a "firs~'type tra~sition spaced from the intermediate transition by 4.5T. This encoded waYeform is further con~erted b~ conventional means (not shown) to code bits of the.type shown in FIGS. lA, 2A, 3A
and 7B, wherein.a transi,tion is represented by a binary "1"
code bit whose dûration is~equal to one-half of a bit cell inter.~al. Thus, it is appreciated.that the encoded data 15 bits whic~ represent.the encoded~wa~e~orm of ~IG. 2G are ?
constituted:by a binaxy ~ i bit in the second-half portion o~,a first bit cell inter~al, a binary "1" code bit in the first-hal~,portion o~ the next-~ollowing fifth bit cell inter,~aL,.and a binary~ "1" code bit in the.second-half 20 portion of.the next-cllowing ninth bit cell interval.
Stated otherwise,,let it be assumed that clock pulses CP3 are~enerated at times to~ tl,~t2 -- tl6~ tl7/ tl8~ 22 The encoded data bits thus are present as binary 'il"s in the intervals tl-t2, t8~tg and tl7-tl8.
Clock pulses CP4 are generated at one-half the rate o~ c.lock pulses CP3 and are syn~hronized by the frame .synchronizing signal FS such that these clock pulses are generated at times to~ t2, t4 -- tl8' t20' ~22-
BRIEF DESCRIPTION OF THE DRAWINGS
The following detailed description, given by way of example, will best be understood in conjunction with the accompanying drawings in which:
FIGS. lA-lK, 2A-2H and 3A-3I are timing diagrams which are useful in understanding the encoding technique of the present invention;
FIG. 4 is a block diagram of one embodiment of the encoder in accordance with the present invention;
FIG. 5 is a table which is useful in understanding the operation of the encoder shown in FIG. 4;
FIGS. 6A-6C are timing diagrams which represent the various timing signals used in the encoder of FIG. 4;
FIGS. 7A :and 7B are timing diagrams which represent a synchronizing signal which can be inserted into the encoded data, in~accordance with the present invention;
FIG. 8 is a block diagram of one embodiment of a decoder which can be used to decode the data that has been encoded by the present invention;
i75~68 FIG. 9 is a timing diagram representing a modifi-cation of the encoding technique of the present invention;
FIGS. lOA-lOK and llA-llK are timing diagrams which represent another embodiment of the encoding technique of the present in~ention;
FIG. 12 is a block diagram of an encoder which can be used to carry out the encoding technique represented by the timing diagrams of FIGS. 10 and lli FIG. 13 is a timing diagram representing a synchro-nizing signal which can be inserted into the data encoded in accordan~e with the format represented by FIGS. 10 and 11;
and FIG. 14 is a block dLagram of a decoder which is compatible with the encoder shown in FIG. 12.
I)ETAILED iDEscRIpTIoN OF PREFERRED EMBODIMENTS
.. .. _ .. _ .. . . . . .. . _ ..
Referring now to the drawings, FIGS. lA-lK represent the encoding technique by which successive bi.nary "l"s are encoded into the preferred format by which succeeding transi-tions in the encoded digital signal, that is, the digital signal produced by way of the present invention, represents successive binary "l"s. In each of these figures, an initial~ transition lS produced when the input digital slgnal undergoes a change-over~from a binary "0" to a binary~ This transition is referred to herein as the "first transition" or "first-type" transition, and is produaed in substantially the middle portion o~ a bit cell. As used -hereinj~the expression "bit cell" reers to the interval or duration occupied by a binary bit of either "1" or "0"
; value.
3L1~7~6~3 When successive binary "l"s are encoded, after the first transition is produced at -the middle portion of a bit cell, the next-following transition is produced at the trailing edge of a b.it cell, ~hat is, this next-following transition, which is referred to herein as the "second"
or "second-type" transition, is produced at the boundary be-tween adjacent bit cells. For the purpose of the present description, a "first" transition is produced at a first reference point, that is, at the middle portion of a bit cell, and a "second" transition is produced at a second reference point, that is, at the trailing edge of a bit cell. This location of the transitions in the encoded data is si.milar - to that of the NRZI format. However, in the NRZI code, the minimum transition interval T that is produced in response to successive binary "l"s is equal to lT, and the maximum transition interval that is produced in response to successive binary "O'ls has no limitation. The present invention differs from these conditions of the NRZI code in that the minimum transition interval Tmin that is produced in response to successive binary "l"s is equal to 1.5T (wherein T is equal to the bit cell interval), and the maximum transition interval TmaX is equal to 4.5T or even 4T in response to successive binary ""s.
~ In the encoded data produced in response to the 25 lnput digital signal ~010] shown in ~'IG. lA, only a single transition in the encoded signal is produced, this single transition aoinciding with the middle portion of the bit 96~
cell which is occupied by the binary "1". The waveform produced by this encoded data is shown benea~h the repre-sentation of ~010~, and a digitized version o this wave-form is represented therebeneath. This digitized version of the waveform contains bits whose bit cells are equal to one-half the bit cell duration of the input digital data; and a transition in the encoded data waveform is represented by a binary "0" bit of one-half bit cell duration followed by a binary "1" bit of one-half bit cell duration. Although not shown herein, it may be appreciated that the transition ln the waveform shown in FIG. lA may be a negative transition, that is, the waveform may undergo a change from its relatively higher level to its lower level.
Nevertheless, the digitized representation of such a transi-tion is represented by digitized bits 01.
As shown in FIG. lB, input digital data [0110]
is encoded in a manner such that a first transition is produced in the middle of the bit cell containing the first binary "1", and a second transition is produced at the trail-ing edge of the bit cell containing the last binary "1", that is this second transition is produced at the bo~nda~y of the bit cells~containing the binary signals 10. The separa-tion between these first and second transitions is equal -to 1.5T, wherein T is equal to the bit cell interval. It will be apprec~a-ted that a "first" transition is produced in the middle of a bit cell interval when the input digital data ~undergoes a changeover from a b~nary "0" value to a binary "1" value. A "second" tra~sition is produced at the trailing edge~of a bit cell interval in accordance with the following condi~ions: (a) a changaover from a binary "1" to a binary "0"; or (b) after a predetermined number of successive binary "l"s or "0" have been received, provided that succeeding transitions are separated by no less than Tmin = 1 5T. These conditions are not mutually exclusive and, as will be explained in greater detail below, a "second" transition is not produced in accordance with condition (a) if such a second transition would follow a "first" transition by less than a predetermined amount. In encoding the input digital data shown in FIG. lB, the irst and second transitions are separated by 1.5T, that is, by 1.5 bit cell intervals.
Referring to FIG. lC, the input digital data[011.10]
is encoded such that a first transition is produced in the ~iddle of the bit cell inter~aL containing the first binary :: 15 "1'l/ and a second transition.:is.produced at the trailing edge o the bit cell containing the last binary "1". Thus~ the total.separatiQn between these transitions is seen to be equal to 2.5T. ~ binary "1" is not~produced at the boundary separating the bit cells containing the second and third 20. binary "l."s because this would result in a separation between two transitlons by an amount equal l.OT. In the present in~ention, the predetermined minimum separation Tmin ibetween succeeding transitions is equal .1.5T. Thus, the ., requirement of condition (b) above would prohibit the production, 25 ~-in:encoding the data shown in FIG. lC, of a transition between , the second and third binary "l"s.
When the number o successive binary "l"s is ~rea.ter than 3, a "second" transition is produced after every 2 or:3 successi~e "l"s~ as will be described.
_g_ 7~
Stated otherwise, a "~irst" transition is produced in the middle of the bit cell containing the first of the binary "l"s (that is, following the change over from a binary "0" to a binary "1") and a second transition is produced after every : 5 n successive binary "l"s wherein n = 2 or 3, _ provided that condition (b) above is satisfied. Thus, to encode the input digital signal [011110], the first transition is produced in the middle of the bit cell containing the first binary "1", and a respective second transition is produced after every 2 successi~e binary "l"s.
Consequently, the first two transitions in the encoded data are separated by 1.5T, and the next two transitions are separated by 2T.
:In FIG. lE,~the first transition is produced in the middle o~ the bit celI containing the ~irst binary "1", and then a:second transition;is produced at the trailing edge of the bit cell containing the~second binary "1". Then, the next ."second" transition is produced follo~ing the next.3 binary "l"s. It is recognized that a "second" transition cannot~be produced after every 2 binary "l"s to encode the~data.shown in FIG~ lE because this would result in a separation between the last two transitions by an amount : equal to lT~.
From FIGS. lF-lK, it is seen that if the total number of successive binary "l."s in the input digi.tal data lS an even number in excess of 3, then a respective transition . is produced after every two successive binary "l"s. However, if the total number of successive binary "l"s is an odd number.in excess of 3, then a transition is produced after 1.~l :i'~96Z~
every two successive binary "l"s, except that the last five binary "l"s are divided into two groups, the first group consisting of 2 binary "l"s and the second group consisting of 3 binary "l"s. Hence, if the total number of successive binary "l'is is an odd number in excess of 3, then two transi-: tions will be separated from each other by a maximum of 3T.
In FIGS. lG, lI and lK, this maximum separation is provided between the last two transitions. If desired, this maximum separation can be provided between any other pair of trans-L0 tions, such as between the second and third transitions, the third and ourth transitions, the fourth and fifth transitions, and the like. Of course, the separation between the first two transitions, as shown in FIGS. lD-IK, is equal to Tmi = 1.5T.
~s a.modification o~.the example represented by ~Ies. lP-IK, a transition can be produced after every 3 .successi~e binary "l"s. This.would result in the encoded wa~eforms shown in FIGS.. lD-lG. Howe~er, if the input digital data.is as.sho~n in FIG. lH, then, a~ter the initial minimum separation of l.5T between the first two transitions, as shown, the next transition would be produced after 3 binary "l"s and then another transition would be produced after the next-f:ollowing 3 binary "l"s. This would result in the usual minimum.separation o~ 105T between the ~irst two transitions, ~25 and then the remain.ing transitions would be separated by 3T.
:~To encode the input digital data shown in FIG. lI, the first two transitions would be separated by 1.5T, then the next-;following transition would be separated by 3T, and `
~7~6~
then the remaining transitions would bP separated by 2T. To encode the input digltal data shown in FIG. lJ, the first two transitions would be separated by 1.5T, the next-following transitions would be separated by 3T, the next-following transition also would be separated by 3T, and then the final transition would be separated by 2T. To encode the input digital data shown in FIG. lK, th0 first two transitions would be separated by 1.5T, and then all of the following transitions would be separated by 3T. Thus, where possible, a transit:ion is produced a~ter e~ery 3 binary "l"s, provided that thi~s does not result in a separation between succeeding : transitions which is less than the minimum separation of 1.5T.
As yet another example, successive binary "l"s can be divided into groups of three "l"s and groups of two lS "l"s alternately. Hence, lf the input digital data contains 9 successive binary "l"s~ these successive bits may be divided . into a group of 2, followed by another group of 2 bits, followed by a group of 3 biis~ and then followed by a group~
of 2 bits,::wlth a transition being produced at the trailing edge of each group. The encoded:waveform thus will exhibit transitions which~are separated by 1.5T, 2T, 3T and 2T, respectively. If the input digital data contains ten successive binary "l"s, these bits may be divided into a group of 2, , fo~lowed by a group of 3, followed by a group of 2 and ;~ 25 ~ollowed by a group of 3 such bits. The encoded waveform thus :~. wi~l be provlded with transitions which are separated by 1.5T, 3T, 2T and 3T, respectlvely. Nevertheless, even in this mDdified e~ample, `, ; ' :
~ -12-. i ;'79~8 the minimum separation between succeeding transitions is seen to be 1.5T.
The foregoing has described the encoding of input digital data wherein that data contains successive binary "I"s.
FIGS. 2 and 3 represent the encoding of data which contains successive binary "o"s. FIGS . 2A-2H represent the encoding of input digital data in which successiye binary "O"s are preceded ~: by the combination 01. FIGS. 3A-3I represent the encoding of input digital data in which the successive binary "o"s are preceded~by the combination 11. In PIGS. 2A-2H, a "first!'-type transition is produced in the middle of the bit cell containing the first binary "1". Of course, another "first" transition is produced in the middle of the bit~ cell containing the binary "1" which ollows the successi~e binary "O"s. In FIGS. 3A-3I, the initial.transition is.a "second"-type transition which is produced at the trailing edge of the blt cell containing the : binar~. "1" which precedes the successi~e "O"s. A "irst"-type transition is produced in the middle of the bit cell containing .the.binary 'll" which follows the.successive "O"s.
In FIG. 2A, a transition is produced in the middle o~
each bit cell containing a binary "1"~ and these transitions are seen to be sep rated by 2T. In FIG. 3AJ the initial transition is produced at the boundary between the bit cells containing the binary "l"
and binary '0", =espectively, and the next-following .
transition is produced in the middle of the bit cell containing the next binary "1". Hence, in FIG. 3A, the illustrated transitions are separated by 1.5T.
In FIG. 2s, transitions are produced in response to the change-over of a binary "0" to a binary "1", thereby resulting in a separation of 3T between these transitions.
It is preferred that a transition not be produced at the boundary between successiye binary "o"s because this will result in two succeeding "transition intexvals" exhibiting 10 minimum separation Tmin = 1.5T. In FIG. 3B, the initial ., ; transition is produced at the boundary between the prefix 11 : and the successive binary "O."s; and the next-following transition is produced in response to the change-over from binary "0" to "1", ;This latter transition is a "first!',.type transition and, thus, occurs in the ~iddle of the bit cell containing the changed-over binary "1".
As shown in FIG. 2C, ~hen the input digital data is ~,010001], transitions are produced at the middle of those bit cells which contain a binary "1". Hence, these transi-tions are separated by the txansition interval of 4T. It is . preferred that a transition not be produced at the trailing ¦ edge of the bit cell containing the first of the successive l} binary "O"s in order to distinguish successive binary "o"s ., from successive binary "l"s. It is recalled that, in response to successlve binary "l"s, the first two transitions areseparated by:the min~m transition interval ~min = 1.5T. Also, to improve such discr~Dation between succes ive "l"s and "o"s, it is preferred that a 96~
transition not be produced at the trailing edge of the bit cell containing the second binary "0". Likewise, in FIG. 3C, the beginning of the successive binary "o"s is represented by a "second"-type transition, and it is preferred not to produce another of these "second"-type transitions at the trailing edge of the bit cell containing the second binary "0".
FIG. 2D represenis the input digital data [0100001].
If this data is encoded by producing transitions only in the middle of the bit cells containing the illustrated binary "l"s, then the separation between such transitions would be equal to 5T. In the present invention, the maximum separation, or transition interval Tmax, is.selected to be 4.5T. Hence, if.t~e input digital data of FIG. 2D.is encoded in the aforementioned manner, the separation between transitions would exceed TmaX. To a~oid this possibility,.a.."second"-type transition is produced at the trailing edge of the bit cell containing the third binary "0", as illustrated.
This resuIts in a separation between the first two transi-ti~ns of 3.5T, and a~separation.between the last two 20..transitions of 1.5T. Thus, the illustrated transition inter~als are greater than Tmin and less than TmaX.
In ~IG..3D, i~: a transition is produced at the -txailing edge of the bit cell containing the third binary "o", the resultant transition inter~als in the encoded waveform will be greater than Tmin and less than TmaX However, f a "second"-type transition is produced at the beginning of the~successive binary "0"s, and then the next transition is not produced until a~ter the change over from binary "0"
-I5~
-to binary "1", as illustrated/ the .resultant transition interval will be equal to T = 4.5T. This latter encoding is max preferred.
From FIGS. 2C and 2D, and also from FIGS. 3C and 3D, it is obs~rved that, if the input digital data contains three or more successive binary "O"s, then the transition interval between the first two transitions should be no less than 3. 5T .
In view of this condition, a transition is not provided at the boundary between the last two.binary "O"s in FIG. 3D.
From FIGS. 2E-2H,.it is appreciated that, if successive binary "O"s are preceded by the combination 01, then,:a~ter the ~irst transi~ion (which is produced at the middle of the b.it cell containing the binary "1"), the next transition i5 produced after three successive binary "o"s, and, therea~terj a "second"-type transitlon is produced after the next 4.seccessive binary "o"s. Howe~er, a ."second"-type transition is not produced a~ter 4.successive binary "O"s i to do so would result in a.separation thereof from a "first!'-type transition by less than Tmin = 1.~5T. It is for this 20. reason:that a ."second!'-type transition is not produced after the final 4 binary "O"s in FIG. 2G. However, since this minimum separation requirement is not violated in FIG. 2H, a !':second!'-type transition is produced at the trailing edge of the bit cell containing the fourth binary "0" in the group of four "0"8, as illustrated. Thus, if the input diyital data contains 4 or more successive binary "O"s which are preceded by the combination 01~ then the transition interval defined by the first two transitions which are used as an encoded representation of the input digital data is equal to 3.5T.
~i'7~3168 :
From FIGS. 3D-3I, it is seen that, if 4 or m~re successive binary "o"s are preceded by the combination 11, an initial transition is produced at ~he boundary between the bit cells containing the chanye-over from binary "1"
to binary "0", and another transition is produced at the I trailing edge of the bit cell containing the fourth binary "0", ! provided that the transition interval between this transition and the next-following transition is not less than Tmin = 1.5T.
In FIG. 3D, if a transition is produced at the trailing edge of the bit cell containing the fourth binary "0"~, the transition interval be~ween this transition and the "first!'-type transition produced at the middle of the next-following bit cell will~be less than Tm1n. Hence, and as shown in FIG. 3D, a "second"-type transition is not produced at the trailing edge of the bit cell containi~g the fourth binary "0", resulting in a transition ~interval equal to TmaX - 4.5T. But, since the minimum transitlon inter~al Tmin-~is equaled or exceeded when 5 or more successi~e binary "O"s are present,-as shown in FIGS. 3E-3I, a "second"-type transition is produced at the trailing edge of the bit cell`containing the fourth binary "0".
Consequently, in FIGS. 3E-3I, the transition interval between the first two transitions of the encoded , waYeform is equal to 4T. Thereafter, another l'second"-type : : tran~sltion~is produced after every 4 binary "O"s, unless the:separation between this "second"-type transition and the :` :
, ~I7-;l ~7961!3 next-following transi.ti.on, such as the "first"-type transition shown in FIG. 3H, is less than Tmin- 1.5T.
A comparison between FIGS. 2D-2H and 3E-3I indicates that the transition interval bekween the first two transitions in the encoded waveform representing successive binary "O"s is equal to elther 3.5T or 4T. From FIG. 1, it is recalled that this ini-tial transition interval is on the order of l.5T. Hence,.
depending upon the inital transition interval, the encoded waveform representing successive binary 'il"s can be distinguished easily from the encoded waveform representing successi~e binary " 0 '~
: ~ Also, it is seen that,~ when successive binary IlO'ls are;encoded in the manner discussed above,~the maximum transition interval Tmax is limited to 4.5T, as shown in FIG. 2G and FIGS.
3D and 3H.
The encoding technique represented in FIGS. 2 and:3 may be described, generally, as pxoducing a l'first"-type :
transition at the middle of a bit cell containing a binary ; when the input digital:data ahanges over from a binary ~0 to a:binary~ and:a "second"-type transition~is produced :
: at~ the~trailing edge of a bit cell after every m successive binary "O"s wh~erein:m ~ 3 ~or 4. This general description is further~limited by the condition that a transition interval will~not exce~ed TmaX = 4.5T, nor will a transition interval 25~be~1ess~than Tmin = 1.5T. Furthermore, m - 3 to define the f~irst~trans~ition interval when successive binary "O"s are preceded by the c:ombination 01 and m = 4 to define the first transition~interval when sucaessive binary "O"s are preceded .
, i7~8 by the comb~tion 11. Thereafter, the transition interval between succeeding "second"-type transitions is seen to be 4T, as shown in FIG. 2H and FIGS. 3E 3I. Also, it is preferred that, where possible, the transition interval between the first two transitions in the encoded waveform be less than TmaX = 4.5T.
In any seguence of successive bits, minimum and maximum transition intervals Tmin and Tma occur only once in a sequence. That is, in the encoded waveform representing successive binary "l"s or "O"s, the minimum transition interval is not present more than once and, likewise~ the maximum transition interval also is not present more than once. It is appreciated that input digital data contalning successive binary "O"s may be encoded as:represented by FIG. 2 or FIG. 3, depending upon whether the successive binary "O"s are preceded by the combination 01 or by the combination 11.
In any event, when 3 or more successive binary "O"s are present, the initial transition interval is no less than 3.5T.
However, when the input digital data contains successive binary "l"s, the largest transition interval contained in the encoded waveform is 3T,:as shown in FIGS. lE, lG, lI and lK.
Therefore, in order to distinguish the encoded representation of successive binary "O"s from successive binary "l"s, the received . :
transition lntervals are compared to a reference predetermined interval which, in the present e~ample, is selected to be e~ual to 3.5T.
25 Ihat is, in order to decode the waveforms produced by the enox~r of the .' , present invention, the separation be-tween succeeding transi-tions is compared to this 3.5T standard. If the detected separation is less than 3.5Tr it is assumed that the encoded waveform represents successive binary "l"s. Conversely, if the detected separation between succeeding transitions in the encoded waveform is ~reater than 3.5T, the transitions are assumed to represent successive binary "0"s.
One embodiment of encoding apparatus which is readily adapted to carry out the encoding technique discussed hereinabo~e with respect to FIGS~ 1-3 is illustrated in FIG. 4. Encoder 1 is comprised of a shift register 2, a read only~memory (ROM) 5, a shift register 6, a multi-stage shl~t register 8 and a logic gating circuit 11. Shi~t register 2 is illustrated as a three-stage register having an input terminal 3 to ~hich input digital data lS
supplied, and a shift pulse input 4 connected to receive timing pulses, also referred to as clock pulses CPl.
Digital data is shifted from right-to-le~t, one stage at a ti~e,~in response to each timing pulse supplied to shi~t reglster 2. As illustrated, an input bit is shi~ted ihto~stage a3j and then~from stage a3 to stage a2, and then from~;stage,a2 to stage alr all in synchronism with successi~e timing pulses CPl. The contents of stages al, a2 and a3 are supplied~as three bits o~ a 4-bit address siynal to ROM 5. The fourth,bit of this address signal is designated as bit x,supplied to ROM 5 by logic gating circuit 11, to be described.
- -2,0-ROM 5 may be a conventional read only memory having, for example, sixteen separate storage locations, each storage location being addressed by the 4-bit address signal supplied thereto, and each of the sixteen storage locations storing a 2-bit signal. This 2-bit signal is read out from the addressed storage location of ROM 5 and loaded, parallel-by-bit, into shift register 6. AS illustrated, shift register 6 is a 2-bit shift register having stages bl and b2 therein.
Shift register 6 includes a load input terminal 7 LO adapted to recei~e a load:pulse~LD for loading the 2-bit signal read out of ROM 5 into stages bl and b2. This shift register also lncludes a shlft~pulse input coupled to a clock puLse texminal 9 for receiving clock, or timing pulses CP2.
The contents of shift register.6 are shifted ln synchronism with cLock pulses CP2 in t~e xight-to-left direction. Hence, in response to two successiYe clock,.:pulses CP2, the bit loaded . .
:.into~stage bl is shifted out~therefrom ~hile the bit which had been loaded into stage b2~is shifted~thereinto, and then this bit lS shifted out of:stage bl. The output of shift reglster.6:~1s supplled serially-by-bit to multi-stage shift register 8 ~hich, in the illustrated embodiment, is an 8~stage shift register~including:.stages A-H. Thls shift register ~lso includes a shift pulse input connected to clock pulse ~ input:~terminal 9 to receive clock'..pulses CP2 so as to :~ 25~synchronously shit~bits therethrough in the right-to-left ~direction in response to each clock pulse. An output ~terminal 10 lS coupled to the left-most stage A to receive the contents of shift register 8 which has been seriall~
shifted therethrough.
':
. -21-36~
Each stage A-H of shift register 8 is coupled to a respective input of logic gating circuit 11. An additional input of this logic gating c.ircuit is coupled to stage al of shift register 2. The logic gating circuit combines the various bits supplied thereto from shift registers 2 and 8 to produce bit x of the 4-bit address supplied to ROM 5.
This logic gating circuit implements the Boolean equation:
x~ +B). (C~D). (E~F)~ (G+H). al + (G~H). al (1 ~lthough not described in detail herein, one of ordinary skill in the art would be enabled to construct a suitable logic gating circuit to lmplement the foregoing equation.
In operation, clock pulses CPl are supplied ~ia clock input texminal 4 to shift re~ister 2. These clock pulses serve to.serially shift into shift register 2 the 15 particuIar digital data.supplied:thereto.~ia input termina~ 3. ~:
Clock pulses CPl are illustrated.in FIG~ 6A. For the purpose of the present discussion, it may be assumed that a binary bi.t is.shifted into.stage a3 of.shift register 2 in response to the positlve-going transition o~ olock pulse CPl. ~.-:......
Furthermore,:~each positi~e transition of:clock pulse CP
ser~es to shift the con.tents of shift reglster 2 to the left by one.stage. Prior to loading the next bit of the lnput~dlgital data into.shift register 2, the contents of ROM:5 are read out therefrom in response to the 4-bit address suppl~ied thereto, this 4-bit address being constituted as (xala2a3). This data read out of ROM 5 is loaded into .shift register 6 in response to the load pulse LD, shown in FIG. 6C. Then, after shift register 6 is loaded with data xepresented as blb2~ this 2-bit data is shifted into shift register 8 in response to the next 2 successive clock pulses CP2 shown in FIG. 6B. The contents of shift register 8 (ABCDEFGH?, together with bit al in shift register 2, are supplied to logic gating circuit 11 to produce bit x~ Thereaftex, the ~-bit address (xala2a3) reads out bits blb2 from ROM 5, these bits being loaded into shift register 6. The foregoing cycle is repeated periodically at the rate determined by clock pulses CPl. This cycle interval ECC is illustrated in FIG.:6.
As an example:of the operation of the encoder shown }n FIG.:4, let it be assume~ that the input digital data ~ ~011:1110~, shown in FIG. lE, is supplied to input terminal 3.
: Let lt be further assumed. that~, initially, the contents of shift reglster 8 are reset to zexo, b~its blb2 are (00) and bits.ala2:a3 are (000)O It.is fuxther:assumed that successi~e clock pulses CP2 axe generated at times to~ tl, t2 ..., and clock pulses CPl, which are one-half the frequency of clock pulses CP2, are generated at times to~-t2, t4 ... . At time to, the binary ~0~ of.the input digital data is.loaded into 20. stage a3 of shift reglster 2. Also, at times to and tl, bits blb2, which are assumed tQ be (?, are shifted into stages : G and H, respectively. Thus, at time tl, logic gating circuit 11 is supplied with bits A-H and al, all of which are a binary "0".i F:rom the foregoing equation, it is appreciated that bit : 25 x also is a~binary l~0~l. FIG. 5 illustrates the "memory map~
of ROM-5,~ from which it is appreciated that bits (00) are read : ~ out there~rom. These bits are loaded into shift register 6 in response to the load pulse LD following time point tl.
i'79~8 At time t2, the binary "l" included in the input digital data is loaded into stage a3. At times t2 and t3, the contents (00) o shift register 6 are loaded into stages G and H of shift register 8, and the contents (00) : 5 previously stored in stages G and H are shifted into stages E
and F, respectively. Logic gating circuit ll produces a binary "O" as bit x, such that ROM 5 now is addressed by the address signal (OOOl). AS shown in FIG. 5, ROM.5 now supplies the bits (00) to shift register 6 in response to the load pulse LD which ls produced after tlme point t3.
At time t4, the next binary "l" of the input digital data is loaded into stage a3, and the binary "l" previously .
-` stored in stage a3 is loaded into stage a2. Bits (00) which had been loaded into shift register 6 in response to the load pulse LD preceding time point t4 are.shifted into stages G and H at times: t4 and t5. At-these times, the contents:of stages E and F are~shifted into.stages C.and D, and the contents pre~iousLy stored in stages G and H are shifted into stages E
and F. Logic gating circuit ll still is supplied with 0...0 to produce a~binary "O" as bit.x. Now, however, ROM 5 is addressed by.the address signal ~OOll) to supply bits (Ol) to shift register 6. These blts are loaded into the shift register in response to the:next load pulse LD which precedes time point t6.
At time t6, the third binary "l" of the input.
digital data is shifted into stage a3, the binary "l"
`~`
;
:
.
7~
previously stored in this stage is shifted into stage a2, and the binary "1" previously stored in stage a2 is shifted into stage al. Furthermore, at times t6 and t7, .~ the contents (01) of shift register 6 are shifted into stages G and H, respectively, and, of course, the contents of stages C
and D are shifted into stages A and B, the contents of stages : E and F are shifted into.stages C and D, and the contents previously stored in stages G and H are shifted into stages E and F. Now, logic gating circuit 11 is supplied with a binary "1" from stage H and also with a binary "1" fram stage al of shift reglster 2. In accordance with the preceding Boolean ; equatlon, logic ~ating circuit ll produces a binary "1" as bit x. Consequently, ROM~S now is addressed~with the address signal (1111~ to supply bits :(00) to shift register 6. The load : 15 pulse LP~produced between.times t7 and t8 loads shift register 6 with:this (00) information.
The~foregoing operation.is repeated cyclically as the input digital data is shifted through shift register 2. Hence . encoder l~operates such that,:at times tl5, tl8 and t24, ~a binaxy "1", whose duration is equal to one-half the period of clock`pulses CPl,~is shifted to output terminal 10 from shift reglster 8. Thus, a binary "1" of duration 0.5T is produced at .
times tL5,~tl8 and t24. These binary "l"s represent the transi-tions of.the eneoded waveform; and if supplied to a flip-flop circuit~, a~toggle circuit, or the like will result in the ~a~e~orm illustrated in FIG. lE.
, .-25-~
'75~
It will be appreciated that encoder 1 functions to encode successive binary "l"s and successive binary "0"s in the manner described hereinabove with respect to FIGS. 1-3.
Thus, transitions having the aforenoted transition intervals are produced as encoded representations of the input digital data supplied to i.nput terminal 3.
In the foregoing description of encoder 1, it has been assumed that a read only memory is used to supply shift:register 6 with bits blb2 in response to the 4-bit address:signal ,(xala2a3). If,desired,:this read only memory may be rep}aced by a logic gating circuit to implement the table shown in FIG. 5. More par*icularly, the logic gating circuit ma~ be used to implement the ~ollowing Boolean equations:
bl = x.al. (a2 ~ a3) ~ x - al 2 (2) b2 al a2 (3) : It is seen that.the combination of shi~t register 2 an:d logic gating circuit l~ functions to sense the presence and~number:of,successi~e.binary~"l"s or "0"s,:.in the digital data.supplied to input terminal,3. ROM 5 is addressed in .
response~ to the.:sensing of such data to read out tharefrom ~si~na}s which are used.to,pxoduce "first"-type transitions the bit b2 is a binary "~l'i) or "second"-type transitions ~(if~the bit bl is a binary ''.l"). The foregoing equation (1) : , in aombination with reading out of the stored contents of : 25 ROM:5 insures a minimum transtion interval Tmin = 1.5T, 7~36~3 a maximum transition interval TmaX = 4.5T and a transition interval no greater than 4T hetween '~second"-type transitions, in the encoded data produced at output terminal 10. This combination also serves to determine if the total number of successive binary "1" s, for example, is greater than 3, is odd or is even. Furthermore, encoder 1 functions to sense the appropriate number of successive binary "0"s in order to produce the respective transitions discussed above with respect to FIGS. 2 and 3.
The encoded wa~e~orm derived by encoder 1 may be recorded on a.suitable record medium,.such as magnetic tape, - a magnetic disc, or the like. As one example, the encoded wa~eform may be recorded on a disc similar to a typical video disc. When recorded.in.this manner, it is desirable -15 that a frame.synchroniæing.signal FS:also be recorded. This ~rame synchronizlng signal lS used during a reproduction operation to synchron.ize..timing pulses which are used to decode - the encoded wa~e~orm, and thus.recover the original digital data. Preferably, the rame.s~nchronizing signal FS is insert-ed into the encoded waveform. That is, it is not recorded in aseparate location as a distinctive signal on the record medium.
Consequently, it is necessary that the frame synchronizing signal FS be distinguishable from the encoded data, yet it should:be o~ a similar ~ormat. One example of a suitable frame -25 .synchronizing signal;is illu~trated in FIGS. 7A and 7B.
The frame synchronizing signal is constituted by three transitions defining two.successive transition intervals -2.7-~179~8 equal to TmaX = 4.5T. As mentioned above, the encoded datawaveform representing successive binary "l"s and "O"s does not include consecutive transi-tion intervals equal to T
max Hence, the frame synchronizing signal FS is seen to be unique and may be readily detected when the encoded data waveform is reproduced or otherwise received.
The relationship between the frame synchronizing sign FS and a number of successive bit cells is illustrated in FIGS. 7A and 7B. It is seen.that the beginning and ending transitions of:the frame synchxonizing signal each coincides with.the middle o~ a bit cell, and the middle, or intermediate transition:of.the frame synchronizing signal coincides with the boundar~ between, adjacent~bit cells. With this relationship,.
clock pulses may be,synchroni.zed with the respective frame synchroniziny signal transitions. More particularly,~clock pulses having a frequency.similar to that of aforedescribed clock pulses CPl (FIG 6A)~may~be~synchronized with the intermediate,transition of the frame synchronizing signal; and clock pulses having a ~requency.similar to the aforedescribed clock puIses CP2 (FIG. 6B) may be synchronized with the beginning and:ending~transitions of the frame synchronizing signal.~ As.:~will be described below, such synchronized clock pulses may be used to decode the encoded data waveform so as to rec~er the original digital data.
: The frame,synchronizing signal comprises two .successive~:txansition inter~als, each equal to TmaX, which ~: are present~during.an.overall duration equal to 12T.
' : -2.8-~ l6'7~6~
It will be appreciated that encoder 1 does not produce an encoded waveform whereby two transition intervals T
max are produced during a duration of 12T. Hence, the frame synchronizing signal may be readily detected merely by establishing a refere.nce duration equal to 12T (or, if desired, equal to 11T) and by sensing consecutive transi-tion intervals TmaX during such a reference duration. This frame synchronizing signal is used to synchronize the code bits which~represent the transitions of the encoded data wa~eform, as well as the recovered binary bits. Furthermore, .the frame synchronizing.~slgnal may be used to synchronize fxame intexvals which,-in.some.applications, establish timing inter~als ln which data is recorded or tranzmitted.
One embodiment of,a decoder which is compatible with encoder 1 and which may,be used to recoYer,the original digital data from the,encoded:data waveforms shown in FIGS~ 1-3 is illustrated:in FIG:~ 8. This~decoder 12 is comprized of.a multi-stage.shift register 14 haYing an input .term3nal 13 connected to receive a digitized.version of the encoded data~wa~eform, and a shi~t pulse~input 1.8 connected ,to recei~e clockj or timing, pulses CP3. Timing pulses CP3:may~be simil~ar to aforedescribed~timing pulses CP2, .
ha~ing a frequency equal to twice the original data bit rate.
Encoder 12:also includes a logic gating circuit 15, which : :
~ay~be: comprised of Gonventional gating circuitry, adapted .to implement the following Boolean equation:
: : :
2 C6~C5 ~(Cg~ Cll ~ ~ ~C4 -~ C3) (C7-~Cg) ~ (C2~cl) C7 : :
(4) :
:-2.9~, wherein Y is the output produced by the logic yating circuit in response to bits Cl ... Cll supplied thereto. These bits are the contents of corresponding stages in multi-stage shift register 14.
5 The output of logic gating circuit 15 is coupled to a latch circuit 16, which may comprise a timing pulse controlled flip-flop circuit, or the like, coupled to a clock, or timing, pulse input 19 to receive clock pulses CP4.
The output produced by latch circuit 16 may be either a binary "1" or a binary "0", depending upon the state of the input:supplied thereto at the time of receipt of a clock pulse CP4. .This output is supplied to an output .terminal 17.
Clock pulses CP3 axe synchronized with the beginning and ending..transitions of.frame synchronl:zing signal FS, and clock:~pulses CP4 are synchronized:with the intermediate .transition~of this fxame.~synchronizing signal. It may be appreciated, therefore, that i the digitized.version of the encoded data~wa~eform;supp.lie~ to input terminal 13 represents each transition as a blnary ~ i of onè-half bit cell duration, when the binary "l" representing the beginning transition of the frame.synchronizing:signal shown in FIG. 7B is shifted from stage Cll to stage C~0 in shift register 14, a clock pulse CP4 .ls produced. Then, when this binary "1" is 2S :shlfted from stage Cg to stage C8, and then rom staye C7 to.stage C6, and then stage C5 to stage C~, and then from .s:tage C3~to stage C2, a respecti~e clock pulse CP4 is generated in timed synchronism therewith. It is further - appreciated that successive clock pulses CP3 serve to shift these bits from stagé-to-sta~e of shift register 14 in the , -30- ~
~167~
right-to-left direction.
As one example of the operation of decoder 12, let it be assumed that the encoded data waveform shown in FIG. 2G has been recorded. The original digital data ~100000001] thus is represented by the waveform wherein a "firs~"-type transition is produced in the middle of a bit cell interval, the next-following transition is separated therefrom by 3..5T, and an ending transition is a "firs~'type tra~sition spaced from the intermediate transition by 4.5T. This encoded waYeform is further con~erted b~ conventional means (not shown) to code bits of the.type shown in FIGS. lA, 2A, 3A
and 7B, wherein.a transi,tion is represented by a binary "1"
code bit whose dûration is~equal to one-half of a bit cell inter.~al. Thus, it is appreciated.that the encoded data 15 bits whic~ represent.the encoded~wa~e~orm of ~IG. 2G are ?
constituted:by a binaxy ~ i bit in the second-half portion o~,a first bit cell inter~al, a binary "1" code bit in the first-hal~,portion o~ the next-~ollowing fifth bit cell inter,~aL,.and a binary~ "1" code bit in the.second-half 20 portion of.the next-cllowing ninth bit cell interval.
Stated otherwise,,let it be assumed that clock pulses CP3 are~enerated at times to~ tl,~t2 -- tl6~ tl7/ tl8~ 22 The encoded data bits thus are present as binary 'il"s in the intervals tl-t2, t8~tg and tl7-tl8.
Clock pulses CP4 are generated at one-half the rate o~ c.lock pulses CP3 and are syn~hronized by the frame .synchronizing signal FS such that these clock pulses are generated at times to~ t2, t4 -- tl8' t20' ~22-
-3.1-6~3 Now, at time to/ a binary "O"code bit is shifted into stage Cll of shift register 14. ~t time tl, the binary "1" code bit is shifted into this stage. This binary "1~ code bit is shifted into stage C10 at time t2, into stage Cg at time t3, into stage C8 at time t4, into stage C7 at time tS/ and into stage C6 at time t6. From equation (4), it is appreciated that an output y is produced by logic gate circuit 15 when a binary ','1" is shifted into stage C6.
Hence, a binary "1" is.produced as output y during the ti~e inter~al t6-t7. At time t7, the~binary "1" in stage C6 ~is shifted into stage C5~ and.at time t~, the binary "1"
, ls shifted from stage C5 into.stage C4. At this samP time t8, ... the:next blnary "1" code,bit is shifted into stage Cll, and the aforedescribed sh.i~tin.g process is repeated.
From equation~ (4?, it is.seen. that a binary "1"
is produced at output ~ at time tl3,~that is, at the time ` when the next binary,"l" code bit.which had been shifted into `~ stage Cll lS shifted into:stage C6. Thereafter, a binary "1" is produced at output y,at~:time~t22. This is in response to the last:binary "1" code bit which lS shifted into stage ; Cll at time~tl7, this last binary "1" code bit being shifted ,sequentially until it reaches stage C6. Thus, a binary "1"
:
LS produced at output y at times t6, tl3 and t22.
, The binary "1" output ~ serves to set latch circuit 16 to a binary "1" condition only if the output y . .is a binary "1" concurrent with a clock pulse CP~. When output y is a binary "0", latch circuit 16 is reset in response to clock pulses CP4~ Accordingly, in the foregoing :-32-~7~68 example, latch circuit 16 is set in response to the binary "1" output.y at time t6, and then the latch circuit is reset 8' tl0~ tl2' tl4~ tl6, tl8 and t20- At the next clock pulse CP4, which occurs at time t22, the output y once again is a binary "1" to set latch circuit 16. Con-sequently, latch circuit 16 recovers the digital data signal ~0100000001] at output terminal 17. This, of course, corresponds to the original input data shown in FIG. 2G.
Decoder 12 functions in a manner similar to that discussed hereinaboYe in order to recover the original digital data siynal which may be supplied thereto as the encoded representations.shown in FIGS. 1-3. In the interest of bre~it~, ~urther description of the operation of decoder 12 is not provlded. ~e~ertheless, it.should be appreciated that lo~ic gate circuit l5 ~unctions to compare the repxesentations of the trans~itions which are.shlfted to shift register 14 to predetermined "~ind~w".intervals. One of these window :
intervals effectively "measures" the.separation between the first two transitions to determine if this.separation is of an amount corresponding to a series of binary "l"s or a : .series of blnary "0"s, as mentioned above. It is recalled that the transitions which represent successive binary "l"s are separated ~rom each other by an amount:less than the : transitions: which represent successive binary"0"s. In 2`5 this~regard, logic gating circuit 15 e~fectively compares :the.separation between transitions to two sets of "window"
.inter~als: one.set of "window" intervals representing the various separations which are associ.ated with binary "l"s;
and the other set of "window" intervals representing the separations associated with successive binary "0"s, as mentioned above. More particularly/ these "window"
intervals are substantially equal to the expected separations representing successive binary "l"s and "O"s. It is recalled that the expected separations representing successive binary 5 "O"s are wider than the expected separations representing successive binary "l"s~ When the actual separations correspond to a~.particular "window" interval, the corresponding binary bits are produced at output terminal 17 of latch circuit 16.
Hence, deccder 12 serves to compare the separation between transitions, as represented by the code bits, to the aforementioned standard, or refexence interval, whereby successive binary "l"s are produced when the transition intervals are less than this.standard, and successive binary "O."s are produced when.the:transi,tion intexvals exceed this standard.
- It is reccgnized that,~the ll-stage storage capaclty of.shift register 14 i.s suf~icient:to accommodate the code bits.which represent at~least three succeeding transitions in the encoded.version of successive binary "l"s. That is, shift ' register 14 is suf~icient to accommodate at least the encoded representation of the wàveform shown ln FIG. lE. This shift register also has su~ficlen-t capacity to accommodate the encoded.vers:ions.shown in FIGS. 2D and 3D.
~ Various modiications and changes may be made 25 ~ to decoder:12. For example, logic cixcuit 15 and logic : ~ circuit 16 may be replaced by a read only memory, similar : to:that used in encoder 1.
~'79~;8 As discussed above, and as is apparenk from FIGS. lD, lF, lH and lJ, if the total number of successive binary "l"s in the input digital data is an even number, the binary "l"s may be divided into groups of two, and a "second"-type transition 5 is produced in response to each group~ If the total number of successive binary "l"s is an odd number, then the last group of binary "l"s will be constituted by three such bits. In that event, the "second"-type transition is produced after these three bits have been sensed. It is seen, therefore, that the ~reatest transition inter~al in the encoded version of successive binary "l"s is equal to.3T. Therefore, to distinguish :successive binary "l"s from "O."s, the aforementioned reference, or standard, interval is selected as being equal to 3.5T. A
txansition in.terval that is less than this.standard thus is - 15 representative of successi~e binary "l"s; and a txansition interval that exceeds this standard is xepresentati~e of successive:binary "O."s.
~ s an alternati~e, if.the odd or even nature of the tota~l number of successive binary ~"l"s is known~prior to encoding, the aforementioned.standard interval can be reduced from 3.5T to 2 . 5T . As shown in FIG. 9, if it is known that the : total number of successive binary "l"s is an odd number, then the bits may be divided into a first group of three binary "l"s, followed by succeeding groups of two binary "l"s. If "second!'-type transitions are produced at the boundaries between adjacent ~ gxoups, the encoded waveform will appear as shown in - FIG 9. As~illustrated, the iniiial transition interval 79~
is equal to 2 . 5T because it is derived from the group of three binary "l"s. This initial transition interval is followed by succeeding transition intervals, all equal to 2T, because these latter transition intervals are derived from groups of two binary "l"s. Thus, a transition intexval of 3T is avoided. The original input data shown in FIG. 9 corresponds to that shown in FIG. lK, and.the difference between these encoding schemes are readily apparent. Of course, if it is known that the total number of successive binary "l"s is an even number, then these bits are divided into groups of two, resuIt~ing-in the encoded ~aveforms shown in, for example,~FIGS. lF, lH and 13. Thus, for an odd number o binary "l"s, the iniiial transition inkerval is equal to 2 . 5T, whereas for an e~en number of successive binary "1"SJ the initial transiti~on interval is equal to 1.5T.
With this modification, if the reference, or standard interval which is used to discriminate the encoded representations of successive binary "l"s and "O"s is reduced from:3.5T to.3T, the maximum transition interval TmaX may be correspondingly reduced from 4. ST to 4T. As a result, the.second~transition i.nterval shown in FIG. 2G
would be reduced from 4..5T to-3:.5T, the second transition :i~ter~al shown in FIG. 2H would be reduced from 4T to 3T, the transition shown ~n FIG. 3D would be replaced by a - ;first transition inter~al of 3T followed by a second transition.in.terval of l..ST~ and the like.
Of course, to best implement the foregoing modi~ication, a buffer memory should be provided so as ' .:-36-'7~~8 to store the successive binary "l"s of the input digital data, thereby indicating whether the successive binary "l"s constitute an odd or even number. Since, in a practical application, an infinite number of successive binary "1"5 is not provided, suitable buffer memories are readily available.
As yet another alternative to the encoding technique described hereinabove, rather than determine, ini~ially, if the total number of successive binary "l"s : 10 is odd or even, these data bits may be divided into groups of.two and, if the "remainder" of one bit remains, then the last.5 bits in the sequence are divided into two.groups: one group of;3 bits and one group of 2 bits.
A:"second''-type transition.is provided at the boundary between these.two.groups~ In the e~ample descr~ibed absve with respect to FIGS. lE, lG~ lI and lK, the group of three .successive binar~ "l"s was designated the last of the groups.
In.the example.shown ln FIGS. lOE, lOG, lOI and 10K, the group of three binary "l"s is designated the penultimate 20. ~roup, and the final group of binary "I"s is formed of two successive;binary:"l"s.
In the~examples represented by the timing ~iagrams of FIG. 10, FIGS. lOA~lOD are seen to be substantially ~identlcal to ~IGS. lA-lD, respectively. Howe~er, when the number of~suaces~sive.binary ."I"s is 5 or greater, the ~ -last five of these bits are divided into two groups: a - first group of three bits.followed by a second group of : tWo bits. Thus, in FIG. lOE, the first transition interval of 2.5T is derived from the first group of three bits, and the next-following transition interval of 2T is derived from '7~6~
the final group of two bits. In FIG. lE, the illustratedfive binary "l"s are divided into a first group of two bits, from which the transition interval of 1.5T is derived, followed by a final group of three bits, from which the transition lnterval of 3T is derived.
In the timing diagrams shown in FIG. 10, the encoded waveforms representing an even number of successive binary "l"s are substantially identical to the encoded waveforms of FIG. 1 which also represent an e~en number of successive binary "l"s. This i.s observed by~comparing FIGS. lOF and lFr lOH and lH, and lOJ and lJ. However, when the input digital data contains~an odd number of successive ~binary "l"s in excess of 4, FIG. lO illustrates a final `: :
transition inter~al equal to 2T, derived ~rom a final group of ,two successi~e binary""l'~'s, preceded~by a transition interval of either 2,.5T (FIG. lOE) or,3T, derived from the penultimate,group of thxee,successlve binary~"l"s. This arrangeme~t~is reverse~ ~in FIG. 1, as~may be observed by comparing FIGS.~lOE and lE~ 10G~and lG, 10I and lI, and lOK and~lK.
,, A similar modification in the encoding scheme may be used to encode~successive binary "o"s, as indicated in FIG. 11. More particularly, in FIG. 11, successlve binary "O"s~are divided ,into groups of three; and a "second"-type~transition,is produced at the trailing edge of a bit cell~in response to,each group, provided that the minimum separation between transitions is not less than 1.5T. For ~` :
-the case of a single binary "O", as shown in FIGS. llA
and llA'j the encoded wa~eform is similar to that discussed ,-38-~16'7968 hereinabove with respect to FIGS. 2A and 3A, respectively.
If the input digital data consists of only two successive binary "O"s, as shown in FIGS. 11B and 11B ~, the encoded waveforms are similar to those shown in FIGS. 2B and 3B, respectively. Likewise, if the input digital data is constituted by three successive binary "o"s, these three bits constitute a single group, resulting in the encoded waveform shown in FIG. llC, similar to the encoded waveforms shown in FIGS. 2C and 3C.
In FIGS. llC-llK, the encoded waveform having the flrst transition shown by the solid~Iine represents that successive binary "O"s are preceded by the combination 01.
The encoded waveform having the first transition shown by the broken line represents that successive binary "o"s are pxeceded by the combination Ll. ~ -In FIGS. llD-llK, four or more successive binary "o"s are present. In accordance~with the illustrated encoding scheme, the successive binary "O"s are divided into groups of three. After the first group of three binary "O"s, a "second"-type transitlon is produced.
Thereafter, another "second"-type transitlon is produced ; after the next group of three binary "O"s, only if the separation~between this last-mentioned "second"-type transition and the final "first"-type transition is not less than 1.5T~ In FIG. llF, if a "second"-type transition is produced in response to the second group of three binary "O"s, this "second"-type transition will be spaced frorl~the final "first"-type transition by 0.5T. Since this condition is to be avoided, FIG. 11F illustrates that such a "second'l-type transition is not produced in `--~
response to the last yroup of three binary "O"s.
However, in FIG. llG, a "second"-type transition is produced ln response to the second group of three binary "O"s; and this "second"-type trans.ition is spaced from the final "first"-type transition by 1.5T.
It is seen from the waveforms shown in FI~. 11 that the maximum transition interval TmaX in this embodiment is equal to 4T. If four or more successive binary "O"s are present in the inpu-t digital data, the initial transi-tion interval is equal to 3.5T if the binary "O"s arepreceded by the combination 01, and the initial transition interval is equal to 3.0T when the binary "O''s are preceded by ~he combination 11. Thereafter, a "second"-type transi- -tion is produced in response to each group of three successive binary "O"s, provided that the minimum separation between succeeding transitions is no less than l.ST. When this . :~ .
condition does not obtain, as shown in ~IGS. llF and llI, the "second"-type transition is not pxoduced.
The encoded waveforms shown in FIGS. 10 and 11 are distinguishable from each other in that, for example, .
except for FIG. llA, a~transition interval of 2T is not , present in the encoded representation of successive binary "O"s. Furthermore, in the encoded representation of successive binary "L"s, the initial transition interval is equal to 1.5T, whereas the initial transition interval associated with the encoded representation of successive binary "O"s is either 3T or 3.5T. Still further, for an even number of successive binary "l"s, succeeding transition `; :
,:
:
- ~ O -.
~1~i'7~
intervals of 2T are present, .Ind for an odd number of successive binary "l"s, the ~ast two transition intervals are seen to be 3T followed by 2T~ These characteristics are no~ present in the encoded representations of successive binary "0"s. These differences can be used in a modification of the decoder shown in FIG. 8, whereby successive binary "0"s can be distinguished from successive binary "l"s as represented by the encoded waveforms.
FIG. 12 ls a block diagram of.an encoder 21 which is readily adapted to carry out the encoding scheme represented by the timing diagrams of FIGS. 10 and 11. It is appreciated that encoder 21 is similar to encoder 1 of FIG. 4, and includes a shift register 22, similar to shift register 2, but comprised of five stages al ... a5, a logic circuit 25, which performs a function analogous to ROM 5, a shift register 26, similar to aforedescribed shift register 6, a multi-stage shift register 28, similar to shift register 8,~and a logic gating circuit~31, similar to aforedescribed logic gating circuit ll. Shift re~ister 22 is coupled to a data input terminal 23:~ from which successive binary bits of the~input digital data are received. The shift register also is coupled to a clock pulse input terminal 24 to recelve clock pulses CPl, described above.
. The~contents of stages~ ala2a3a4a5 of shift register 22, together with bit x, are supplied to logic circuit 25.
Dependin~ upon the status of the respective bits supplied thereto, this log-ic circuit generates bits blb2, which bits~are supplled in parallel to shift register 26. More ,' ~ ~` ' ' ~ ' ' ' :
; ~ .
.
7~
particularly, logic circuit 25 produces bits bl and b in accordance with the following Boolean equations:
al a2 + X al (a2 + a3 . a4 . a5) (5) b2 = al ^ a2 (6) .
As before, bits bl and b2 are loaded, parallel-by-bit into shift register 26 in response to a load pulse LD (FIG. 6C).
Shift register 26, as well as multi-stage shl~t regi.ster 28, is coupled to a clock pulse input terminal 29 to receive clock pulses CP2 (FIG. 6B). Thus. in response to successive ones of clock pulses CP2, bits bl and b2 are shifted from shift register 26 into sequential stages GFEDCBA
of shift register 28. As each bit blb2 lS: shifted out of stage A of the multi-stage shift register,~ code blts of one-half bit cell duratio~ are generated, sequentlally, at output termlnal 30.
The contents of stages A...G of shift register 28, ; toaether with the contents of stage al of shift register 22, are supplied to logic gating circuit 31. Thls logic gatlng clrcuit~ implements the~followlng Boolean eauatlon to produce bit x:
~ x = ~(A+B) . (D*E) . (F~G) . al + ~F~G) . al (7) . ~
Of~course, blt x, in conjunction with bits ala~a3a4aS
in shift register 22 are u sed by logic circuit 25 to generate .
.
: ~ ~
-: ~ :
:
4a 7~6~
bits bl and b2 in accordance ~ith equations (5) and (6).
In the interest of brevity, and to avoid sub-stantial duplication of explanation, a detailed description . of the operation of encoder 21 is not provided. It will be readily apparent to those of ordinary skill in the art that this encoder operates in a manner similar to tha~
described hereinabove with respect to the embodiment of encoder 1.
If desired, logic circuit 25 may be replaced by, for example, a read only memory having 64 storage locatlons, each being addressed by the 6-bit signal xala2a3a4a5, and each storage location storing ~pPropriate bits bl and b2, so as to read out these bits to shift register 26 in response to the particular address signals supplied to the ROM.
It is appreclated that encoder 21 generates the ..
encoded verslons of successive binary "l"s and "0"s as illustrated in FIGS. 10 and 11. Advantageously, a frame synchronizing signal FS, fully distinguishable from the encoded data, is inserted into the encoded representat}OnS
of digital data in order to synchronize the operation of a decoder which is compatible with the encoder shown in FIG. 12. It would appear that the frame synchronizing . signal shown in FIG. 7B may be used with the encoder of 25 FIG. 12. Another pattern of transition intervals:which can be~used as the frame svnchronizing signal FS is illus-trated in FIG. 13, together with the coded bits representing such transitions. Successive transition intervals o 4T, followed by 3.5T, followed by 2T, are not present in the -~3-~, .
,'' ' , ~1~'7,~3~
encoded waveforrns showrl in l~lGS. 10 and 11. Thus, the frame synchronizing signal represented in FIG. 13 is easily distinguished from the encoded data. The initial transition of this frame synchronizing signal may coincide with the middle of a bit cell interval or, alternatively, may coincide with the boundary between adjacent bit cell intervals.
. FIG. 14 illustrates an embodiment of a decoder 32 which is compatible with encoder 21 and which is readily adapted to recover the original digital data in response to receiving coded bits corresponding to the encoded .
waveforms of FIGS. 10 and ll. Decoder 32 includes a shlft register 3-4, comprised of stage5 Cl O.. Cl5, a logic circuit 35 and a logic circuit 36. It is seen that this is similar to shi~t register 14, logic circuit 15 and logic circuit 16, r~espectively~, of FIG. 8. Shift register 34 is connected to an input terminal 33 to receive coded bits representing the transitions of the~ encoded data. ~;~
A shift pulse lnput of shift register 34 is coupled to an input terminal:38 to receive clock~pulses CP3. ~hese clock~pulses~are slmilar to those descrlbed hereinabove with respect to FIG. 8.
The outputs of stages Cl-Cg, Cll, Cl3 and C15 all are coupled to respective inputs of logic circuit 35.
This logic circuit implements the following Boolean equation:
6 5'-8 Cll C15+Cg (C3-Cl3~c4~C5) ~ c7,(cl.c (8) ' ~ .
, :
.
s ~
The resultant outpUt y produced by logic circuit 35 is supplied to latch circuit 36. This latch circuit, being similar to af~redescribed latch circuit 16, is set or reset in timed synchronism with clock pulses CP4, depending upon whether output y is a binary "1" or "0", respectively. The state of the latch circuit, that is, whether it is set or reset, is represented by an output signal supplied to output terminal 37. This output signal corresponds to the original input digital data which is recovered from the coded bits serialIy shifted into shift register 34.
The operation of decoder 32 is similar to that set out in detail hereinabove with respect to decoder 12.
Therefore, in the lnterest of brevity, this explanation is not repeated. Suffice it to say, however, that as the representations of transitions are serlally shifted through shift register 34, logic circuit 35 serves to compare the separation between such transitions to predetermined "window" intervals to produce an output y dependlng upon the relationship between the measured transition intervals and these "window" intervals.
If desired, logic circuit 35 may be replaced by a suitable ROM which is addressed by the contents o~ shiEt register 34 to read out a corresponding output y, consistent~with equation (8). ~
If the encoded version of the input digital data, as produced by the embodiments of the encoder , -discussed hereinabove, are recorded as an audio PCM signal . on, for example, a vide disc record rnediurn, the frame synchronizing signal FS, discussed above, miyht not be recorded. In that event, clock pulses CP3 and CP4 must be derived from the reproduced data s-tream. Since the maximum transition interval TmaX is relatively short, in accordance with one advantageous feature of the present invention, such synchronous reproduction is readily obtained.
Even if the actual transi.tion interval in the reproduced data stream exceeds the aforementioned maximum, due to time base fluctuations, or the like, the encoded data nevertheless may be readily decoded.
While the present invention has been particularIy shown and described.with reference to certain preferred embodiments,~it should be readily apparent to those of ordinary skill in the art that:various changes and modifi-cations in form and details may be made without departing from the spirit and s~ope of the inventlon. It is, therefore, intended: that the appended claims be lnterpreted as including all suah changes and modlfLcations.
~ .
..
:; : :
,: ~
Hence, a binary "1" is.produced as output y during the ti~e inter~al t6-t7. At time t7, the~binary "1" in stage C6 ~is shifted into stage C5~ and.at time t~, the binary "1"
, ls shifted from stage C5 into.stage C4. At this samP time t8, ... the:next blnary "1" code,bit is shifted into stage Cll, and the aforedescribed sh.i~tin.g process is repeated.
From equation~ (4?, it is.seen. that a binary "1"
is produced at output ~ at time tl3,~that is, at the time ` when the next binary,"l" code bit.which had been shifted into `~ stage Cll lS shifted into:stage C6. Thereafter, a binary "1" is produced at output y,at~:time~t22. This is in response to the last:binary "1" code bit which lS shifted into stage ; Cll at time~tl7, this last binary "1" code bit being shifted ,sequentially until it reaches stage C6. Thus, a binary "1"
:
LS produced at output y at times t6, tl3 and t22.
, The binary "1" output ~ serves to set latch circuit 16 to a binary "1" condition only if the output y . .is a binary "1" concurrent with a clock pulse CP~. When output y is a binary "0", latch circuit 16 is reset in response to clock pulses CP4~ Accordingly, in the foregoing :-32-~7~68 example, latch circuit 16 is set in response to the binary "1" output.y at time t6, and then the latch circuit is reset 8' tl0~ tl2' tl4~ tl6, tl8 and t20- At the next clock pulse CP4, which occurs at time t22, the output y once again is a binary "1" to set latch circuit 16. Con-sequently, latch circuit 16 recovers the digital data signal ~0100000001] at output terminal 17. This, of course, corresponds to the original input data shown in FIG. 2G.
Decoder 12 functions in a manner similar to that discussed hereinaboYe in order to recover the original digital data siynal which may be supplied thereto as the encoded representations.shown in FIGS. 1-3. In the interest of bre~it~, ~urther description of the operation of decoder 12 is not provlded. ~e~ertheless, it.should be appreciated that lo~ic gate circuit l5 ~unctions to compare the repxesentations of the trans~itions which are.shlfted to shift register 14 to predetermined "~ind~w".intervals. One of these window :
intervals effectively "measures" the.separation between the first two transitions to determine if this.separation is of an amount corresponding to a series of binary "l"s or a : .series of blnary "0"s, as mentioned above. It is recalled that the transitions which represent successive binary "l"s are separated ~rom each other by an amount:less than the : transitions: which represent successive binary"0"s. In 2`5 this~regard, logic gating circuit 15 e~fectively compares :the.separation between transitions to two sets of "window"
.inter~als: one.set of "window" intervals representing the various separations which are associ.ated with binary "l"s;
and the other set of "window" intervals representing the separations associated with successive binary "0"s, as mentioned above. More particularly/ these "window"
intervals are substantially equal to the expected separations representing successive binary "l"s and "O"s. It is recalled that the expected separations representing successive binary 5 "O"s are wider than the expected separations representing successive binary "l"s~ When the actual separations correspond to a~.particular "window" interval, the corresponding binary bits are produced at output terminal 17 of latch circuit 16.
Hence, deccder 12 serves to compare the separation between transitions, as represented by the code bits, to the aforementioned standard, or refexence interval, whereby successive binary "l"s are produced when the transition intervals are less than this.standard, and successive binary "O."s are produced when.the:transi,tion intexvals exceed this standard.
- It is reccgnized that,~the ll-stage storage capaclty of.shift register 14 i.s suf~icient:to accommodate the code bits.which represent at~least three succeeding transitions in the encoded.version of successive binary "l"s. That is, shift ' register 14 is suf~icient to accommodate at least the encoded representation of the wàveform shown ln FIG. lE. This shift register also has su~ficlen-t capacity to accommodate the encoded.vers:ions.shown in FIGS. 2D and 3D.
~ Various modiications and changes may be made 25 ~ to decoder:12. For example, logic cixcuit 15 and logic : ~ circuit 16 may be replaced by a read only memory, similar : to:that used in encoder 1.
~'79~;8 As discussed above, and as is apparenk from FIGS. lD, lF, lH and lJ, if the total number of successive binary "l"s in the input digital data is an even number, the binary "l"s may be divided into groups of two, and a "second"-type transition 5 is produced in response to each group~ If the total number of successive binary "l"s is an odd number, then the last group of binary "l"s will be constituted by three such bits. In that event, the "second"-type transition is produced after these three bits have been sensed. It is seen, therefore, that the ~reatest transition inter~al in the encoded version of successive binary "l"s is equal to.3T. Therefore, to distinguish :successive binary "l"s from "O."s, the aforementioned reference, or standard, interval is selected as being equal to 3.5T. A
txansition in.terval that is less than this.standard thus is - 15 representative of successi~e binary "l"s; and a txansition interval that exceeds this standard is xepresentati~e of successive:binary "O."s.
~ s an alternati~e, if.the odd or even nature of the tota~l number of successive binary ~"l"s is known~prior to encoding, the aforementioned.standard interval can be reduced from 3.5T to 2 . 5T . As shown in FIG. 9, if it is known that the : total number of successive binary "l"s is an odd number, then the bits may be divided into a first group of three binary "l"s, followed by succeeding groups of two binary "l"s. If "second!'-type transitions are produced at the boundaries between adjacent ~ gxoups, the encoded waveform will appear as shown in - FIG 9. As~illustrated, the iniiial transition interval 79~
is equal to 2 . 5T because it is derived from the group of three binary "l"s. This initial transition interval is followed by succeeding transition intervals, all equal to 2T, because these latter transition intervals are derived from groups of two binary "l"s. Thus, a transition intexval of 3T is avoided. The original input data shown in FIG. 9 corresponds to that shown in FIG. lK, and.the difference between these encoding schemes are readily apparent. Of course, if it is known that the total number of successive binary "l"s is an even number, then these bits are divided into groups of two, resuIt~ing-in the encoded ~aveforms shown in, for example,~FIGS. lF, lH and 13. Thus, for an odd number o binary "l"s, the iniiial transition inkerval is equal to 2 . 5T, whereas for an e~en number of successive binary "1"SJ the initial transiti~on interval is equal to 1.5T.
With this modification, if the reference, or standard interval which is used to discriminate the encoded representations of successive binary "l"s and "O"s is reduced from:3.5T to.3T, the maximum transition interval TmaX may be correspondingly reduced from 4. ST to 4T. As a result, the.second~transition i.nterval shown in FIG. 2G
would be reduced from 4..5T to-3:.5T, the second transition :i~ter~al shown in FIG. 2H would be reduced from 4T to 3T, the transition shown ~n FIG. 3D would be replaced by a - ;first transition inter~al of 3T followed by a second transition.in.terval of l..ST~ and the like.
Of course, to best implement the foregoing modi~ication, a buffer memory should be provided so as ' .:-36-'7~~8 to store the successive binary "l"s of the input digital data, thereby indicating whether the successive binary "l"s constitute an odd or even number. Since, in a practical application, an infinite number of successive binary "1"5 is not provided, suitable buffer memories are readily available.
As yet another alternative to the encoding technique described hereinabove, rather than determine, ini~ially, if the total number of successive binary "l"s : 10 is odd or even, these data bits may be divided into groups of.two and, if the "remainder" of one bit remains, then the last.5 bits in the sequence are divided into two.groups: one group of;3 bits and one group of 2 bits.
A:"second''-type transition.is provided at the boundary between these.two.groups~ In the e~ample descr~ibed absve with respect to FIGS. lE, lG~ lI and lK, the group of three .successive binar~ "l"s was designated the last of the groups.
In.the example.shown ln FIGS. lOE, lOG, lOI and 10K, the group of three binary "l"s is designated the penultimate 20. ~roup, and the final group of binary "I"s is formed of two successive;binary:"l"s.
In the~examples represented by the timing ~iagrams of FIG. 10, FIGS. lOA~lOD are seen to be substantially ~identlcal to ~IGS. lA-lD, respectively. Howe~er, when the number of~suaces~sive.binary ."I"s is 5 or greater, the ~ -last five of these bits are divided into two groups: a - first group of three bits.followed by a second group of : tWo bits. Thus, in FIG. lOE, the first transition interval of 2.5T is derived from the first group of three bits, and the next-following transition interval of 2T is derived from '7~6~
the final group of two bits. In FIG. lE, the illustratedfive binary "l"s are divided into a first group of two bits, from which the transition interval of 1.5T is derived, followed by a final group of three bits, from which the transition lnterval of 3T is derived.
In the timing diagrams shown in FIG. 10, the encoded waveforms representing an even number of successive binary "l"s are substantially identical to the encoded waveforms of FIG. 1 which also represent an e~en number of successive binary "l"s. This i.s observed by~comparing FIGS. lOF and lFr lOH and lH, and lOJ and lJ. However, when the input digital data contains~an odd number of successive ~binary "l"s in excess of 4, FIG. lO illustrates a final `: :
transition inter~al equal to 2T, derived ~rom a final group of ,two successi~e binary""l'~'s, preceded~by a transition interval of either 2,.5T (FIG. lOE) or,3T, derived from the penultimate,group of thxee,successlve binary~"l"s. This arrangeme~t~is reverse~ ~in FIG. 1, as~may be observed by comparing FIGS.~lOE and lE~ 10G~and lG, 10I and lI, and lOK and~lK.
,, A similar modification in the encoding scheme may be used to encode~successive binary "o"s, as indicated in FIG. 11. More particularly, in FIG. 11, successlve binary "O"s~are divided ,into groups of three; and a "second"-type~transition,is produced at the trailing edge of a bit cell~in response to,each group, provided that the minimum separation between transitions is not less than 1.5T. For ~` :
-the case of a single binary "O", as shown in FIGS. llA
and llA'j the encoded wa~eform is similar to that discussed ,-38-~16'7968 hereinabove with respect to FIGS. 2A and 3A, respectively.
If the input digital data consists of only two successive binary "O"s, as shown in FIGS. 11B and 11B ~, the encoded waveforms are similar to those shown in FIGS. 2B and 3B, respectively. Likewise, if the input digital data is constituted by three successive binary "o"s, these three bits constitute a single group, resulting in the encoded waveform shown in FIG. llC, similar to the encoded waveforms shown in FIGS. 2C and 3C.
In FIGS. llC-llK, the encoded waveform having the flrst transition shown by the solid~Iine represents that successive binary "O"s are preceded by the combination 01.
The encoded waveform having the first transition shown by the broken line represents that successive binary "o"s are pxeceded by the combination Ll. ~ -In FIGS. llD-llK, four or more successive binary "o"s are present. In accordance~with the illustrated encoding scheme, the successive binary "O"s are divided into groups of three. After the first group of three binary "O"s, a "second"-type transitlon is produced.
Thereafter, another "second"-type transitlon is produced ; after the next group of three binary "O"s, only if the separation~between this last-mentioned "second"-type transition and the final "first"-type transition is not less than 1.5T~ In FIG. llF, if a "second"-type transition is produced in response to the second group of three binary "O"s, this "second"-type transition will be spaced frorl~the final "first"-type transition by 0.5T. Since this condition is to be avoided, FIG. 11F illustrates that such a "second'l-type transition is not produced in `--~
response to the last yroup of three binary "O"s.
However, in FIG. llG, a "second"-type transition is produced ln response to the second group of three binary "O"s; and this "second"-type trans.ition is spaced from the final "first"-type transition by 1.5T.
It is seen from the waveforms shown in FI~. 11 that the maximum transition interval TmaX in this embodiment is equal to 4T. If four or more successive binary "O"s are present in the inpu-t digital data, the initial transi-tion interval is equal to 3.5T if the binary "O"s arepreceded by the combination 01, and the initial transition interval is equal to 3.0T when the binary "O''s are preceded by ~he combination 11. Thereafter, a "second"-type transi- -tion is produced in response to each group of three successive binary "O"s, provided that the minimum separation between succeeding transitions is no less than l.ST. When this . :~ .
condition does not obtain, as shown in ~IGS. llF and llI, the "second"-type transition is not pxoduced.
The encoded waveforms shown in FIGS. 10 and 11 are distinguishable from each other in that, for example, .
except for FIG. llA, a~transition interval of 2T is not , present in the encoded representation of successive binary "O"s. Furthermore, in the encoded representation of successive binary "L"s, the initial transition interval is equal to 1.5T, whereas the initial transition interval associated with the encoded representation of successive binary "O"s is either 3T or 3.5T. Still further, for an even number of successive binary "l"s, succeeding transition `; :
,:
:
- ~ O -.
~1~i'7~
intervals of 2T are present, .Ind for an odd number of successive binary "l"s, the ~ast two transition intervals are seen to be 3T followed by 2T~ These characteristics are no~ present in the encoded representations of successive binary "0"s. These differences can be used in a modification of the decoder shown in FIG. 8, whereby successive binary "0"s can be distinguished from successive binary "l"s as represented by the encoded waveforms.
FIG. 12 ls a block diagram of.an encoder 21 which is readily adapted to carry out the encoding scheme represented by the timing diagrams of FIGS. 10 and 11. It is appreciated that encoder 21 is similar to encoder 1 of FIG. 4, and includes a shift register 22, similar to shift register 2, but comprised of five stages al ... a5, a logic circuit 25, which performs a function analogous to ROM 5, a shift register 26, similar to aforedescribed shift register 6, a multi-stage shift register 28, similar to shift register 8,~and a logic gating circuit~31, similar to aforedescribed logic gating circuit ll. Shift re~ister 22 is coupled to a data input terminal 23:~ from which successive binary bits of the~input digital data are received. The shift register also is coupled to a clock pulse input terminal 24 to recelve clock pulses CPl, described above.
. The~contents of stages~ ala2a3a4a5 of shift register 22, together with bit x, are supplied to logic circuit 25.
Dependin~ upon the status of the respective bits supplied thereto, this log-ic circuit generates bits blb2, which bits~are supplled in parallel to shift register 26. More ,' ~ ~` ' ' ~ ' ' ' :
; ~ .
.
7~
particularly, logic circuit 25 produces bits bl and b in accordance with the following Boolean equations:
al a2 + X al (a2 + a3 . a4 . a5) (5) b2 = al ^ a2 (6) .
As before, bits bl and b2 are loaded, parallel-by-bit into shift register 26 in response to a load pulse LD (FIG. 6C).
Shift register 26, as well as multi-stage shl~t regi.ster 28, is coupled to a clock pulse input terminal 29 to receive clock pulses CP2 (FIG. 6B). Thus. in response to successive ones of clock pulses CP2, bits bl and b2 are shifted from shift register 26 into sequential stages GFEDCBA
of shift register 28. As each bit blb2 lS: shifted out of stage A of the multi-stage shift register,~ code blts of one-half bit cell duratio~ are generated, sequentlally, at output termlnal 30.
The contents of stages A...G of shift register 28, ; toaether with the contents of stage al of shift register 22, are supplied to logic gating circuit 31. Thls logic gatlng clrcuit~ implements the~followlng Boolean eauatlon to produce bit x:
~ x = ~(A+B) . (D*E) . (F~G) . al + ~F~G) . al (7) . ~
Of~course, blt x, in conjunction with bits ala~a3a4aS
in shift register 22 are u sed by logic circuit 25 to generate .
.
: ~ ~
-: ~ :
:
4a 7~6~
bits bl and b2 in accordance ~ith equations (5) and (6).
In the interest of brevity, and to avoid sub-stantial duplication of explanation, a detailed description . of the operation of encoder 21 is not provided. It will be readily apparent to those of ordinary skill in the art that this encoder operates in a manner similar to tha~
described hereinabove with respect to the embodiment of encoder 1.
If desired, logic circuit 25 may be replaced by, for example, a read only memory having 64 storage locatlons, each being addressed by the 6-bit signal xala2a3a4a5, and each storage location storing ~pPropriate bits bl and b2, so as to read out these bits to shift register 26 in response to the particular address signals supplied to the ROM.
It is appreclated that encoder 21 generates the ..
encoded verslons of successive binary "l"s and "0"s as illustrated in FIGS. 10 and 11. Advantageously, a frame synchronizing signal FS, fully distinguishable from the encoded data, is inserted into the encoded representat}OnS
of digital data in order to synchronize the operation of a decoder which is compatible with the encoder shown in FIG. 12. It would appear that the frame synchronizing . signal shown in FIG. 7B may be used with the encoder of 25 FIG. 12. Another pattern of transition intervals:which can be~used as the frame svnchronizing signal FS is illus-trated in FIG. 13, together with the coded bits representing such transitions. Successive transition intervals o 4T, followed by 3.5T, followed by 2T, are not present in the -~3-~, .
,'' ' , ~1~'7,~3~
encoded waveforrns showrl in l~lGS. 10 and 11. Thus, the frame synchronizing signal represented in FIG. 13 is easily distinguished from the encoded data. The initial transition of this frame synchronizing signal may coincide with the middle of a bit cell interval or, alternatively, may coincide with the boundary between adjacent bit cell intervals.
. FIG. 14 illustrates an embodiment of a decoder 32 which is compatible with encoder 21 and which is readily adapted to recover the original digital data in response to receiving coded bits corresponding to the encoded .
waveforms of FIGS. 10 and ll. Decoder 32 includes a shlft register 3-4, comprised of stage5 Cl O.. Cl5, a logic circuit 35 and a logic circuit 36. It is seen that this is similar to shi~t register 14, logic circuit 15 and logic circuit 16, r~espectively~, of FIG. 8. Shift register 34 is connected to an input terminal 33 to receive coded bits representing the transitions of the~ encoded data. ~;~
A shift pulse lnput of shift register 34 is coupled to an input terminal:38 to receive clock~pulses CP3. ~hese clock~pulses~are slmilar to those descrlbed hereinabove with respect to FIG. 8.
The outputs of stages Cl-Cg, Cll, Cl3 and C15 all are coupled to respective inputs of logic circuit 35.
This logic circuit implements the following Boolean equation:
6 5'-8 Cll C15+Cg (C3-Cl3~c4~C5) ~ c7,(cl.c (8) ' ~ .
, :
.
s ~
The resultant outpUt y produced by logic circuit 35 is supplied to latch circuit 36. This latch circuit, being similar to af~redescribed latch circuit 16, is set or reset in timed synchronism with clock pulses CP4, depending upon whether output y is a binary "1" or "0", respectively. The state of the latch circuit, that is, whether it is set or reset, is represented by an output signal supplied to output terminal 37. This output signal corresponds to the original input digital data which is recovered from the coded bits serialIy shifted into shift register 34.
The operation of decoder 32 is similar to that set out in detail hereinabove with respect to decoder 12.
Therefore, in the lnterest of brevity, this explanation is not repeated. Suffice it to say, however, that as the representations of transitions are serlally shifted through shift register 34, logic circuit 35 serves to compare the separation between such transitions to predetermined "window" intervals to produce an output y dependlng upon the relationship between the measured transition intervals and these "window" intervals.
If desired, logic circuit 35 may be replaced by a suitable ROM which is addressed by the contents o~ shiEt register 34 to read out a corresponding output y, consistent~with equation (8). ~
If the encoded version of the input digital data, as produced by the embodiments of the encoder , -discussed hereinabove, are recorded as an audio PCM signal . on, for example, a vide disc record rnediurn, the frame synchronizing signal FS, discussed above, miyht not be recorded. In that event, clock pulses CP3 and CP4 must be derived from the reproduced data s-tream. Since the maximum transition interval TmaX is relatively short, in accordance with one advantageous feature of the present invention, such synchronous reproduction is readily obtained.
Even if the actual transi.tion interval in the reproduced data stream exceeds the aforementioned maximum, due to time base fluctuations, or the like, the encoded data nevertheless may be readily decoded.
While the present invention has been particularIy shown and described.with reference to certain preferred embodiments,~it should be readily apparent to those of ordinary skill in the art that:various changes and modifi-cations in form and details may be made without departing from the spirit and s~ope of the inventlon. It is, therefore, intended: that the appended claims be lnterpreted as including all suah changes and modlfLcations.
~ .
..
:; : :
,: ~
Claims (27)
1. A method of encoding digital data formed of binary bits of first and second values occupying consecu-tive bit cells of predetermined intervals, comprising the steps of:
producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value;
sensing successive binary bits of said first value and producing a respective second transition at a second reference point in a bit cell after sensing every n successive binary bits of said first value (n = 2 or 3); and sensing successive binary bits of said second value and producing a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after sensing every m successive binary bits of said second value (m = 3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 4 bit cell intervals.
producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value;
sensing successive binary bits of said first value and producing a respective second transition at a second reference point in a bit cell after sensing every n successive binary bits of said first value (n = 2 or 3); and sensing successive binary bits of said second value and producing a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after sensing every m successive binary bits of said second value (m = 3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 4 bit cell intervals.
2. The method of Claim 1 wherein said first reference point substantially coincides with the middle portion of a bit cell interval.
3. The method of Claim l wherein said second reference point substantially coincides with the trailing edge of a bit cell interval.
4. The method of Claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises producing a said second transition after every 2 binary bits if the total number of successive binary bits of said first value is an even number; and if the total number of successive binary bits of said first value is an odd number greater than 3, producing a said second transition after every 2 binary bits and a said second transition after the final 3 binary bits are sensed.
5. The method of Claim 4 wherein, if the -total number of binary bits of said first value is greater than 3, then the minimum separation between succeeding transitions is no less than 1.5 bit cell intervals, and the separation between remaining succeeding transitions is substantially equal to 2 bit cell intervals and for an odd number of successive binary bits the separation between the final two transitions is substantially equal to 3 bit cell intervals.
6. The method of Claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises determin-ing if the total number of said successive binary bits is odd or even and, if odd and greater than 3, producing a said second transition after sensing the first 3 successive binary bits and thereafter producing a said second transition after sensing each 2 successive binary bits, and if the total number of said successive binary bits is even and greater than 3, producing a said second transition after sensing each 2 suc-cessive binary bits.
7. The method of Claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises producing said second transition at the trailing edge of the last bit cell of said successive binary bits if the total number of said successive binary bits is less than 4.
8. The method of Claim 1 wherein said step of producing a respective second transition after sensing every m successive binary bits of said second value comprises producing a said second transition following the production of a first transition after 3 successive binary bits have been sensed if the total number of said successive binary bits is greater than 3.
9. The method of Claim 8 wherein said step of producing a respective second transition after sensing every m successive binary bits of said second value further comprises producing additional second transitions after each 4 successive binary bits, following the first 3 succes-sive binary bits, have been sensed.
10. The method of Claim 1 wherein said step of producing a respective second transition after sensing m successive binary bits of said second value comprises producing a first of said second transitions after 3 suc-cessive binary bits have been sensed and succeeding ones of said second transitions after every 4 successive binary bits have been sensed thereafter, provided that said succes-sive binary bits of said second value are preceded by a single binary bit of said first value.
11. The method of Claim 10, further comprising the step of inhibiting the production of a second transi-tion after 4 successive binary bits have been sensed if said last mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals
12. The method of Claim 1 wherein m = 4 if said successive binary bits of said second value are preceded by at least two successive binary bits of said first value.
13. The method of Claim 12 further comprising the step of inhibiting the production of a second transition after 4 successive binary bits have been sensed if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.
14. A method of encoding digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising the steps of:
producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value;
sensing successive binary bits of said first value, producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, producing a respective second transition at a second reference point in a bit cell after sensing every 2 successive binary bits of said first value, and detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3 and, if so, dividing the last 5 of said successive binary bits into respective groups of 2 and 3 bits and producing a said second transition at a said second reference point between said groups; and sensing successive binary bits of said second value and producing a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after sensing every 3 successive binary bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.
producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value;
sensing successive binary bits of said first value, producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, producing a respective second transition at a second reference point in a bit cell after sensing every 2 successive binary bits of said first value, and detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3 and, if so, dividing the last 5 of said successive binary bits into respective groups of 2 and 3 bits and producing a said second transition at a said second reference point between said groups; and sensing successive binary bits of said second value and producing a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after sensing every 3 successive binary bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.
15. The method of Claim 14 comprising the step of inhibiting the production of a second transition if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.
16. Apparatus for encoding an input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising:
first transition generating means for producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value;
sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; and second transition generating means for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every n successive binary bits of said first value (n = 2 or 3);
said second transition generating means further producing a respective second transition at said second reference point in 8 bit cell when said sensing means senses at least two successive binary bits of said first value and also after sensing every m successive binary bits of said second value (m = 3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 9 bit cell intervals.
first transition generating means for producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value;
sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; and second transition generating means for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every n successive binary bits of said first value (n = 2 or 3);
said second transition generating means further producing a respective second transition at said second reference point in 8 bit cell when said sensing means senses at least two successive binary bits of said first value and also after sensing every m successive binary bits of said second value (m = 3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 9 bit cell intervals.
17. The apparatus of Claim 16 wherein said first reference point coincides with the middle portion of a bit cell interval.
18. The apparatus of Claim 16 wherein said second reference point substantially coincides with the trailing edge of a bit cell interval.
19. The apparatus of Claim 16 wherein said second transition generating means comprises means for producing a said second transition after every 2 binary bits of said first value if the total number of successive binary bits of said first value is an even number; means for determining when the total number of successive binary bits of said first value is an odd number greater than 3, and means for producing a said second transition after every 2 binary bits and a said second transition after said sensing means senses the first 3 binary bits.
20. The apparatus of Claim 16 wherein said second transition generating means comprises means for determining if the total number of said successive binary bits of said first value is odd or even; means for producing a said second transition after sensing the first 3 successive binary bits and thereafter producing a said second transition after sensing each 2 successive binary bits if said total number of said successive binary bits is odd and greater than 3:
and means for producing a said second transition after sensing each 2 successive binary bits if said total number of said successive binary bits is even and greater than 3.
and means for producing a said second transition after sensing each 2 successive binary bits if said total number of said successive binary bits is even and greater than 3.
21. The apparatus of Claim 16 wherein said second transition generating means comprises means for producing said second transition at the trailing edge of the last bit cell of said successive binary bits of said first value if the total number of successive binary bits is less than 4.
22. The apparatus of Claim 16 wherein said second transition generating means comprises means for producing a said second transition following the production of a first transition after 3 successive binary bits of said second value have been sensed if the total number of said successive binary bits is greater than 3.
23. The apparatus of Claim 22 wherein said second transition generating means further comprises means for pro-ducing additional second transitions after each 4 successive binary bits, following the first 3 successive binary bits, have been sensed.
24. The apparatus of Claim 16 wherein said second transition generating means comprises means for producing a first of said second transitions after 3 successive binary bits of said second value have been sensed, and means for producing succeeding ones of said second transitions after every 4 successive binary bits have been sensed thereafter, provided that said sensing means senses that said successive binary bits of said second value are preceded by a single binary bit of said first value.
25. The apparatus of Claim 24, further comprising inhibit means for inhibiting the production of a second transition after 4 successive binary bits have been sensed if said last mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.
26. Apparatus for encoding input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising:
first transition generating means for producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value;
sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value second transition generating means for producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, and for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every 2 successive binary bits of said first value;
detecting means for detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3, means for dividing the last 5 of said successive binary bits into respective groups of 2 and 3 binary bits if said total number is an odd number in excess of 3 such that said producing means produces a said second. transition at a said second reference point between said groups; and said second transition generating means produces a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after said sensing means senses every 3 successive bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.
first transition generating means for producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value;
sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value second transition generating means for producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, and for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every 2 successive binary bits of said first value;
detecting means for detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3, means for dividing the last 5 of said successive binary bits into respective groups of 2 and 3 binary bits if said total number is an odd number in excess of 3 such that said producing means produces a said second. transition at a said second reference point between said groups; and said second transition generating means produces a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after said sensing means senses every 3 successive bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.
27. The apparatus of Claim 26 further comprising inhibit means for inhibiting the production of a second transition if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.
?
?
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3929/80 | 1980-01-17 | ||
| JP392980A JPS56101614A (en) | 1980-01-17 | 1980-01-17 | Binary code converting method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000435841A Division CA1171180A (en) | 1980-01-17 | 1983-08-31 | Method and apparatus for encoding and decoding digital information |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1167968A true CA1167968A (en) | 1984-05-22 |
Family
ID=11570819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000367992A Expired CA1167968A (en) | 1980-01-17 | 1981-01-07 | Method and apparatus for encoding and decoding digital information |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS56101614A (en) |
| CA (1) | CA1167968A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06133690A (en) * | 1992-03-16 | 1994-05-17 | Suzuki Tekkosho:Kk | Bottom bamboo detachment type tea leaf-crumpling machine |
| JPH06225699A (en) * | 1992-10-16 | 1994-08-16 | Suzuki Tekkosho:Kk | Tea manufacturing machine provided with dividable and detachable tea-rolling bottom |
-
1980
- 1980-01-17 JP JP392980A patent/JPS56101614A/en active Granted
-
1981
- 1981-01-07 CA CA000367992A patent/CA1167968A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56101614A (en) | 1981-08-14 |
| JPS635826B2 (en) | 1988-02-05 |
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